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LVL1::jFEXFPGA Class Reference

The jFEXFPGA class defines the structure of a single jFEX FPGA Its purpose is: More...

#include <jFEXFPGA.h>

Inheritance diagram for LVL1::jFEXFPGA:
Collaboration diagram for LVL1::jFEXFPGA:

Public Member Functions

 jFEXFPGA (const std::string &type, const std::string &name, const IInterface *parent)
 Constructors. More...
 
virtual StatusCode initialize () override
 standard Athena-Algorithm method More...
 
virtual ~jFEXFPGA ()
 Destructor. More...
 
virtual StatusCode init (int id, int efexid) override
 
virtual StatusCode execute (jFEXOutputCollection *inputOutputCollection, const std::pair< unsigned int, const std::vector< int > & > &jetCalibrationParameters) override
 
virtual void reset () override
 
virtual int ID () override
 
virtual void SetTowersAndCells_SG (int[][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]) override
 
virtual void SetTowersAndCells_SG (int[][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]) override
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getSmallRJetTOBs () override
 Form a tob word out of the potential candidate SmallRJet tob. More...
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getLargeRJetTOBs () override
 
virtual std::vector< std::vector< uint32_t > > getFwdElTOBs () override
 sorted Electron tobs More...
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getTauTOBs () override
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getSumEtTOBs () override
 Form a tob word out of the potential candidate SumET tob. More...
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getMetTOBs () override
 Form a tob word out of the potential candidate MET tob. More...
 
int getTTowerET_EM (unsigned int TTID) override
 
int getTTowerET_HAD (unsigned int TTID) override
 
int getTTowerET (unsigned int TTID) override
 
int getTTowerET_forMET (unsigned int TTID) override
 
ServiceHandle< StoreGateSvc > & evtStore ()
 The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc. More...
 
const ServiceHandle< StoreGateSvc > & evtStore () const
 The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc. More...
 
const ServiceHandle< StoreGateSvc > & detStore () const
 The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc. More...
 
virtual StatusCode sysInitialize () override
 Perform system initialization for an algorithm. More...
 
virtual StatusCode sysStart () override
 Handle START transition. More...
 
virtual std::vector< Gaudi::DataHandle * > inputHandles () const override
 Return this algorithm's input handles. More...
 
virtual std::vector< Gaudi::DataHandle * > outputHandles () const override
 Return this algorithm's output handles. More...
 
Gaudi::Details::PropertyBase & declareProperty (Gaudi::Property< T > &t)
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, SG::VarHandleKey &hndl, const std::string &doc, const SG::VarHandleKeyType &)
 Declare a new Gaudi property. More...
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, SG::VarHandleBase &hndl, const std::string &doc, const SG::VarHandleType &)
 Declare a new Gaudi property. More...
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, SG::VarHandleKeyArray &hndArr, const std::string &doc, const SG::VarHandleKeyArrayType &)
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, T &property, const std::string &doc, const SG::NotHandleType &)
 Declare a new Gaudi property. More...
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, T &property, const std::string &doc="none")
 Declare a new Gaudi property. More...
 
void updateVHKA (Gaudi::Details::PropertyBase &)
 
MsgStream & msg () const
 
MsgStream & msg (const MSG::Level lvl) const
 
bool msgLvl (const MSG::Level lvl) const
 

Static Public Member Functions

static const InterfaceID & interfaceID ()
 

Protected Member Functions

void renounceArray (SG::VarHandleKeyArray &handlesArray)
 remove all handles from I/O resolution More...
 
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > renounce (T &h)
 
void extraDeps_update_handler (Gaudi::Details::PropertyBase &ExtraDeps)
 Add StoreName to extra input/output deps as needed. More...
 

Private Types

typedef ServiceHandle< StoreGateSvc > StoreGateSvc_t
 

Private Member Functions

int getTTowerET_SG (unsigned int TTID)
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T > &hndl, const SG::VarHandleKeyType &)
 specialization for handling Gaudi::Property<SG::VarHandleKey> More...
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T > &hndl, const SG::VarHandleKeyArrayType &)
 specialization for handling Gaudi::Property<SG::VarHandleKeyArray> More...
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T > &hndl, const SG::VarHandleType &)
 specialization for handling Gaudi::Property<SG::VarHandleBase> More...
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T > &t, const SG::NotHandleType &)
 specialization for handling everything that's not a Gaudi::Property<SG::VarHandleKey> or a <SG::VarHandleKeyArray> More...
 

Static Private Member Functions

template<class TOBObjectClass >
static bool TOBetSort (const TOBObjectClass &i, const TOBObjectClass &j, uint bits, uint mask)
 Internal data. More...
 
static bool etFwdElSort (const std::vector< uint32_t > &i, const std::vector< uint32_t > &j)
 

Private Attributes

std::vector< std::unique_ptr< jFEXTOB > > m_tau_tobwords
 
std::vector< std::unique_ptr< jFEXTOB > > m_SRJet_tobwords
 
std::vector< std::unique_ptr< jFEXTOB > > m_LRJet_tobwords
 
std::vector< std::unique_ptr< jFEXTOB > > m_sumET_tobwords
 
std::vector< std::unique_ptr< jFEXTOB > > m_Met_tobwords
 
int m_id {}
 
int m_jfexid {}
 
std::vector< std::vector< uint32_t > > m_FwdEl_tobwords
 
int m_jTowersIDs_Wide [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}}
 
int m_jTowersIDs_Thin [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}}
 
std::unordered_map< int, jTower > m_jTowersColl
 
std::unordered_map< int, std::vector< int > > m_map_Etvalues_FPGA
 
std::unordered_map< int, std::vector< int > > m_map_HAD_Etvalues_FPGA
 
std::unordered_map< int, std::vector< int > > m_map_EM_Etvalues_FPGA
 
std::unordered_map< int, jFEXForwardJetsInfo > m_FCALJets
 
std::unordered_map< uint, jFEXForwardElecInfo > m_ForwardElecs
 
int m_SRJetET {}
 
int m_LRJetET {}
 
CaloCellContainer m_sCellsCollection
 
SG::ReadHandleKey< LVL1::jTowerContainer > m_jTowerContainerKey {this, "MyETowers", "jTowerContainer", "Input container for jTowers"}
 
SG::ReadHandleKey< TrigConf::L1Menu > m_l1MenuKey {this, "L1TriggerMenu", "DetectorStore+L1TriggerMenu","Name of the L1Menu object to read configuration from"}
 
ToolHandle< IjFEXSmallRJetAlgo > m_jFEXSmallRJetAlgoTool {this, "jFEXSmallRJetAlgoTool", "LVL1::jFEXSmallRJetAlgo", "Tool that runs the jFEX Small R Jet algorithm"}
 
ToolHandle< IjFEXLargeRJetAlgo > m_jFEXLargeRJetAlgoTool {this, "jFEXLargeRJetAlgoTool", "LVL1::jFEXLargeRJetAlgo", "Tool that runs the jFEX Large R Jet algorithm"}
 
ToolHandle< IjFEXtauAlgo > m_jFEXtauAlgoTool {this, "jFEXtauAlgoTool" , "LVL1::jFEXtauAlgo" , "Tool that runs the jFEX tau algorithm"}
 
ToolHandle< IjFEXsumETAlgo > m_jFEXsumETAlgoTool {this, "jFEXsumETAlgoTool" , "LVL1::jFEXsumETAlgo" , "Tool that runs the jFEX sumET algorithm"}
 
ToolHandle< IjFEXmetAlgo > m_jFEXmetAlgoTool {this, "jFEXmetAlgoTool" , "LVL1::jFEXmetAlgo" , "Tool that runs the jFEX met algorithm"}
 
ToolHandle< IjFEXForwardJetsAlgo > m_jFEXForwardJetsAlgoTool {this, "jFEXForwardJetsAlgoTool" , "LVL1::jFEXForwardJetsAlgo" , "Tool that runs the jFEX FCAL Jets algorithm"}
 
ToolHandle< IjFEXForwardElecAlgo > m_jFEXForwardElecAlgoTool {this, "jFEXForwardElecAlgoTool" , "LVL1::jFEXForwardElecAlgo" , "Tool that runs the jFEX FCAL Electrons algorithm"}
 
ToolHandle< IjFEXPileupAndNoise > m_jFEXPileupAndNoiseTool {this, "jFEXPileupAndNoiseTool", "LVL1::jFEXPileupAndNoise", "Tool that applies Pileup and Noise"}
 
ToolHandle< IjFEXFormTOBs > m_IjFEXFormTOBsTool {this, "IjFEXFormTOBsTool", "LVL1::jFEXFormTOBs", "Tool that forms TOB words"}
 
std::string m_jfex_string [6] = {"1C","2C","3C","3A","2A","1A"}
 
StoreGateSvc_t m_evtStore
 Pointer to StoreGate (event store by default) More...
 
StoreGateSvc_t m_detStore
 Pointer to StoreGate (detector store by default) More...
 
std::vector< SG::VarHandleKeyArray * > m_vhka
 
bool m_varHandleArraysDeclared
 

Detailed Description

The jFEXFPGA class defines the structure of a single jFEX FPGA Its purpose is:

Definition at line 51 of file jFEXFPGA.h.

Member Typedef Documentation

◆ StoreGateSvc_t

typedef ServiceHandle<StoreGateSvc> AthCommonDataStore< AthCommonMsg< AlgTool > >::StoreGateSvc_t
privateinherited

Definition at line 388 of file AthCommonDataStore.h.

Constructor & Destructor Documentation

◆ jFEXFPGA()

LVL1::jFEXFPGA::jFEXFPGA ( const std::string &  type,
const std::string &  name,
const IInterface *  parent 
)

Constructors.

Definition at line 33 of file jFEXFPGA.cxx.

33  : AthAlgTool(type,name,parent) {
34  declareInterface<IjFEXFPGA>(this);
35 }

◆ ~jFEXFPGA()

LVL1::jFEXFPGA::~jFEXFPGA ( )
virtual

Destructor.

Definition at line 38 of file jFEXFPGA.cxx.

39 {
40 }

Member Function Documentation

◆ declareGaudiProperty() [1/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T > &  hndl,
const SG::VarHandleKeyArrayType &   
)
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKeyArray>

Definition at line 170 of file AthCommonDataStore.h.

172  {
173  return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
174  hndl.value(),
175  hndl.documentation());
176 
177  }

◆ declareGaudiProperty() [2/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T > &  hndl,
const SG::VarHandleKeyType &   
)
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKey>

Definition at line 156 of file AthCommonDataStore.h.

158  {
159  return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
160  hndl.value(),
161  hndl.documentation());
162 
163  }

◆ declareGaudiProperty() [3/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T > &  hndl,
const SG::VarHandleType &   
)
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleBase>

Definition at line 184 of file AthCommonDataStore.h.

186  {
187  return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
188  hndl.value(),
189  hndl.documentation());
190  }

◆ declareGaudiProperty() [4/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T > &  t,
const SG::NotHandleType &   
)
inlineprivateinherited

specialization for handling everything that's not a Gaudi::Property<SG::VarHandleKey> or a <SG::VarHandleKeyArray>

Definition at line 199 of file AthCommonDataStore.h.

200  {
201  return PBASE::declareProperty(t);
202  }

◆ declareProperty() [1/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
SG::VarHandleBase &  hndl,
const std::string &  doc,
const SG::VarHandleType &   
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
hndlObject holding the property value.
docDocumentation string for the property.

This is the version for types that derive from SG::VarHandleBase. The property value object is put on the input and output lists as appropriate; then we forward to the base class.

Definition at line 245 of file AthCommonDataStore.h.

249  {
250  this->declare(hndl.vhKey());
251  hndl.vhKey().setOwner(this);
252 
253  return PBASE::declareProperty(name,hndl,doc);
254  }

◆ declareProperty() [2/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
SG::VarHandleKey &  hndl,
const std::string &  doc,
const SG::VarHandleKeyType &   
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
hndlObject holding the property value.
docDocumentation string for the property.

This is the version for types that derive from SG::VarHandleKey. The property value object is put on the input and output lists as appropriate; then we forward to the base class.

Definition at line 221 of file AthCommonDataStore.h.

225  {
226  this->declare(hndl);
227  hndl.setOwner(this);
228 
229  return PBASE::declareProperty(name,hndl,doc);
230  }

◆ declareProperty() [3/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
SG::VarHandleKeyArray &  hndArr,
const std::string &  doc,
const SG::VarHandleKeyArrayType &   
)
inlineinherited

Definition at line 259 of file AthCommonDataStore.h.

263  {
264 
265  // std::ostringstream ost;
266  // ost << Algorithm::name() << " VHKA declareProp: " << name
267  // << " size: " << hndArr.keys().size()
268  // << " mode: " << hndArr.mode()
269  // << " vhka size: " << m_vhka.size()
270  // << "\n";
271  // debug() << ost.str() << endmsg;
272 
273  hndArr.setOwner(this);
274  m_vhka.push_back(&hndArr);
275 
276  Gaudi::Details::PropertyBase* p = PBASE::declareProperty(name, hndArr, doc);
277  if (p != 0) {
278  p->declareUpdateHandler(&AthCommonDataStore<PBASE>::updateVHKA, this);
279  } else {
280  ATH_MSG_ERROR("unable to call declareProperty on VarHandleKeyArray "
281  << name);
282  }
283 
284  return p;
285 
286  }

◆ declareProperty() [4/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
T &  property,
const std::string &  doc,
const SG::NotHandleType &   
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
propertyObject holding the property value.
docDocumentation string for the property.

This is the generic version, for types that do not derive from SG::VarHandleKey. It just forwards to the base class version of declareProperty.

Definition at line 333 of file AthCommonDataStore.h.

337  {
338  return PBASE::declareProperty(name, property, doc);
339  }

◆ declareProperty() [5/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
T &  property,
const std::string &  doc = "none" 
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
propertyObject holding the property value.
docDocumentation string for the property.

This dispatches to either the generic declareProperty or the one for VarHandle/Key/KeyArray.

Definition at line 352 of file AthCommonDataStore.h.

355  {
356  typedef typename SG::HandleClassifier<T>::type htype;
357  return declareProperty (name, property, doc, htype());
358  }

◆ declareProperty() [6/6]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( Gaudi::Property< T > &  t)
inlineinherited

Definition at line 145 of file AthCommonDataStore.h.

145  {
146  typedef typename SG::HandleClassifier<T>::type htype;
147  return AthCommonDataStore<PBASE>::declareGaudiProperty(t, htype());
148  }

◆ detStore()

const ServiceHandle<StoreGateSvc>& AthCommonDataStore< AthCommonMsg< AlgTool > >::detStore ( ) const
inlineinherited

The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 95 of file AthCommonDataStore.h.

95 { return m_detStore; }

◆ etFwdElSort()

static bool LVL1::jFEXFPGA::etFwdElSort ( const std::vector< uint32_t > &  i,
const std::vector< uint32_t > &  j 
)
inlinestaticprivate

Definition at line 101 of file jFEXFPGA.h.

103  { return (((i.at(0) >> FEXAlgoSpaceDefs::jEM_etBit ) & 0x7ff )> ((j.at(0) >> FEXAlgoSpaceDefs::jEM_etBit) & 0x7ff ));}

◆ evtStore() [1/2]

ServiceHandle<StoreGateSvc>& AthCommonDataStore< AthCommonMsg< AlgTool > >::evtStore ( )
inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 85 of file AthCommonDataStore.h.

85 { return m_evtStore; }

◆ evtStore() [2/2]

const ServiceHandle<StoreGateSvc>& AthCommonDataStore< AthCommonMsg< AlgTool > >::evtStore ( ) const
inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 90 of file AthCommonDataStore.h.

90 { return m_evtStore; }

◆ execute()

StatusCode LVL1::jFEXFPGA::execute ( jFEXOutputCollection *  inputOutputCollection,
const std::pair< unsigned int, const std::vector< int > & > &  jetCalibrationParameters 
)
overridevirtual

Retrieve the L1 menu configuration

Implements LVL1::IjFEXFPGA.

Definition at line 75 of file jFEXFPGA.cxx.

75  {
76 
77  // Retrieve the L1 menu configuration
78  SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
79 
80  const TrigConf::L1ThrExtraInfo_jTAU & thr_jTAU = l1Menu->thrExtraInfo().jTAU();
81  const TrigConf::L1ThrExtraInfo_jJ & thr_jJ = l1Menu->thrExtraInfo().jJ();
82  const TrigConf::L1ThrExtraInfo_jLJ & thr_jLJ = l1Menu->thrExtraInfo().jLJ();
83  const TrigConf::L1ThrExtraInfo_jTE & thr_jTE = l1Menu->thrExtraInfo().jTE();
84  const TrigConf::L1ThrExtraInfo_jXE & thr_jXE = l1Menu->thrExtraInfo().jXE();
85 
86  SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey/*,ctx*/);
87  if(!jTowerContainer.isValid()) {
88  ATH_MSG_ERROR("Could not retrieve container " << m_jTowerContainerKey.key() );
89  return StatusCode::FAILURE;
90  }
91 
92  ATH_CHECK( m_jFEXPileupAndNoiseTool->safetyTest());
93  ATH_CHECK( m_jFEXPileupAndNoiseTool->reset());
94  if(m_jfexid == 0 || m_jfexid == 5) {
95  m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Wide);
96  }
97  else {
98  m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Thin);
99  }
100 
101  //Calculating and sustracting pileup
102  const std::vector<int> pileup_rho = m_jFEXPileupAndNoiseTool->CalculatePileup();
103 
104  //From the DB
105  ATH_CHECK(m_jFEXPileupAndNoiseTool->ApplyPileup());
106 
107  //Noise should be always applied
108  m_jFEXPileupAndNoiseTool->ApplyNoise2Jets(true);
109  m_jFEXPileupAndNoiseTool->ApplyNoise2Met(true);
110  //Getting the values
111  m_map_HAD_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_HAD_Et_values();
112  m_map_EM_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_EM_Et_values();
113  m_map_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->GetEt_values();
114  std::vector<int> pileup_ID;
115  std::vector<int> pileup_HAD_jet;
116  std::vector<int> pileup_EM_jet;
117  std::vector<int> pileup_Total_jet;
118  std::vector<int> pileup_HAD_met;
119  std::vector<int> pileup_EM_met;
120  std::vector<int> pileup_Total_met;
121  for (auto const& [key, val] : m_map_HAD_Etvalues_FPGA)
122  {
123  pileup_ID.push_back(key);
124  pileup_HAD_jet.push_back(val[0]);
125  pileup_EM_jet.push_back(m_map_EM_Etvalues_FPGA[key][0]);
126  pileup_Total_jet.push_back(m_map_Etvalues_FPGA[key][0]);
127  pileup_HAD_met.push_back(val[1]);
128  pileup_EM_met.push_back(m_map_EM_Etvalues_FPGA[key][1]);
129  pileup_Total_met.push_back(m_map_Etvalues_FPGA[key][1]);
130  }
131 
132  //saving pileup information
133  inputOutputCollection->addValue_pileup("pileup_FPGAid", m_id);
134  inputOutputCollection->addValue_pileup("pileup_jFEXid", m_jfexid);
135  inputOutputCollection->addValue_pileup("pileup_rho_EM", pileup_rho[0]);
136  inputOutputCollection->addValue_pileup("pileup_rho_HAD1", pileup_rho[1]);
137  inputOutputCollection->addValue_pileup("pileup_rho_HAD2", pileup_rho[2]);
138  inputOutputCollection->addValue_pileup("pileup_rho_HAD3", pileup_rho[3]);
139  inputOutputCollection->addValue_pileup("pileup_rho_FCAL", pileup_rho[4]);
140  inputOutputCollection->addValue_pileup("pileup_map_ID" , std::move(pileup_ID));
141  inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_jet" , std::move(pileup_HAD_jet));
142  inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_jet" , std::move(pileup_EM_jet));
143  inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_jet", std::move(pileup_Total_jet));
144  inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_met" , std::move(pileup_HAD_met));
145  inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_met" , std::move(pileup_EM_met));
146  inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_met", std::move(pileup_Total_met));
147  inputOutputCollection->fill_pileup();
148 
149  if(m_id==0 || m_id==3) {
150  ATH_CHECK( m_jFEXsumETAlgoTool->safetyTest());
151  ATH_CHECK( m_jFEXsumETAlgoTool->reset());
152  ATH_CHECK( m_jFEXmetAlgoTool->safetyTest());
153  ATH_CHECK( m_jFEXmetAlgoTool->reset());
154 
155  m_jFEXsumETAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
156  m_jFEXmetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
157 
158  unsigned int bin_pos = thr_jTE.etaBoundary_fw(m_jfex_string[m_jfexid]);
159 
160  std::unique_ptr<jFEXTOB> jXE_tob = std::make_unique<jFEXTOB>();
161  uint32_t jXE_tobword = 0;
162 
163  std::unique_ptr<jFEXTOB> jTE_tob = std::make_unique<jFEXTOB>();
164  uint32_t jTE_tobword = 0;
165 
166 
167  int hemisphere = m_id == 0 ? 1 : -1;
168 
169  if(m_jfexid > 0 && m_jfexid < 5) {
170 
171  //-----------------jFEXsumETAlgo-----------------
172  m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Thin);
173  m_jFEXsumETAlgoTool->buildBarrelSumET();
174 
175  //-----------------jFEXmetAlgo-----------------
176  m_jFEXmetAlgoTool->setup(m_jTowersIDs_Thin, hemisphere);
177  m_jFEXmetAlgoTool->buildBarrelmet();
178  }
179  else if(m_jfexid == 0 ) {
180 
181  int flipped_jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}};
182  int max_phi_it = FEXAlgoSpaceDefs::jFEX_algoSpace_height-1;
183  int max_eta_it = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-1;
184  for(int mphi = 0; mphi <= max_phi_it; mphi++) {
185  for(int meta = 0; meta <= max_eta_it; meta++) {
186  flipped_jTowersIDs[mphi][meta]=m_jTowersIDs_Wide[mphi][max_eta_it-meta];
187  }
188  }
189  //-----------------jFEXsumETAlgo-----------------
190  m_jFEXsumETAlgoTool->setup(flipped_jTowersIDs);
191  m_jFEXsumETAlgoTool->buildFWDSumET();
192 
193  //-----------------jFEXmetAlgo-----------------
194  m_jFEXmetAlgoTool->setup(flipped_jTowersIDs, hemisphere);
195  m_jFEXmetAlgoTool->buildFWDmet();
196  }
197  else if(m_jfexid == 5) {
198 
199  //-----------------jFEXsumETAlgo-----------------
200  m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Wide);
201  m_jFEXsumETAlgoTool->buildFWDSumET();
202 
203  //-----------------jFEXmetAlgo-----------------
204  m_jFEXmetAlgoTool->setup(m_jTowersIDs_Wide, hemisphere);
205  m_jFEXmetAlgoTool->buildFWDmet();
206  }
207 
208  jXE_tobword = m_IjFEXFormTOBsTool->formMetTOB(m_jFEXmetAlgoTool->GetMetXComponent(), m_jFEXmetAlgoTool->GetMetYComponent(),m_jFEXmetAlgoTool->getjXESat(),thr_jXE.resolutionMeV());
209  jXE_tob->initialize(m_id,m_jfexid,jXE_tobword,thr_jXE.resolutionMeV(),0);
210  m_Met_tobwords.push_back(std::move(jXE_tob));
211 
212  std::tuple<int,bool> jTElow;
213  std::tuple<int,bool> jTEhigh;
214 
215  // NOTE: Foward FPGA in the C-side is already flipped, however we still need to flip the jFEX module 1 and 2
216  if(m_jfexid == 1 || m_jfexid == 2){
217  jTElow = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
218  jTEhigh = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
219  }
220  else{
221  jTElow = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
222  jTEhigh = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
223  }
224 
225  jTE_tobword = m_IjFEXFormTOBsTool->formSumETTOB(jTElow,jTEhigh,thr_jTE.resolutionMeV());
226  jTE_tob->initialize(m_id,m_jfexid,jTE_tobword,thr_jTE.resolutionMeV(),0);
227  m_sumET_tobwords.push_back(std::move(jTE_tob));
228  }
229 
230  //-----------jFEXSmallRJet & Large R Jet Algo-----------------
231  ATH_MSG_DEBUG("================ Central Algorithms ================");
232 
233  int srJet_seedThresholdMeV = thr_jJ.seedThresholdMeV(m_jfex_string[m_jfexid]); //jFEX internal granularity, i.e., 25 MeV/count
234 
235 
236  //Central region algorithms
237  if(m_jfexid > 0 && m_jfexid < 5) {
238  m_jFEXSmallRJetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
239  m_jFEXLargeRJetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
240  m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
241 
242  for(int mphi = 8; mphi < FEXAlgoSpaceDefs::jFEX_algoSpace_height-8; mphi++) {
243  for(int meta = 8; meta < FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width-8; meta++) {
244 
245  //definition of arrays
246  int TT_seed_ID[3][3]= {{0}};
247  int TT_First_ETring[36]= {0};
248  int First_ETring_it = 0;
249 
250  int Jet_SearchWindow[7][7] = {{0}};
251  int Jet_SearchWindowDisplaced[7][7] = {{0}};
252  int largeRCluster_IDs[15][15]= {{0}};
253 
254  //filling up array to send them to the algorithms
255  for(int i = -7; i< 8; i++ ) {
256  for(int j = -7; j< 8; j++) {
257 
258  if(std::abs(i)<4 && std::abs(j)<4) {
259  Jet_SearchWindow[3 + i][3 + j] = m_jTowersIDs_Thin[mphi + i][meta +j];
260  Jet_SearchWindowDisplaced[3 + i][3 + j] = m_jTowersIDs_Thin[mphi+i+1][meta+j+1];
261  }
262 
263  uint deltaR = std::sqrt(std::pow(i,2)+std::pow(j,2));
264 
265  if(deltaR<2) {
266  TT_seed_ID[i+1][j+1] = m_jTowersIDs_Thin[mphi +i][meta +j]; // Seed 0.3x0.3 in phi-eta plane
267  }
268  else if(deltaR<4) {
269  TT_First_ETring[First_ETring_it]= m_jTowersIDs_Thin[mphi +i][meta +j]; // First energy ring, will be used as tau ISO
270  ++First_ETring_it;
271 
272  }
273  else if(deltaR<8) {
274  largeRCluster_IDs[7 +i][7 +j] = m_jTowersIDs_Thin[mphi + i][meta +j];
275  }
276  }
277  }
278 
279  // ******** jJ and jLJ algorithms ********
280  ATH_CHECK( m_jFEXSmallRJetAlgoTool->safetyTest());
281  ATH_CHECK( m_jFEXLargeRJetAlgoTool->safetyTest());
282  m_jFEXSmallRJetAlgoTool->setup(Jet_SearchWindow, Jet_SearchWindowDisplaced);
283  m_jFEXLargeRJetAlgoTool->setupCluster(largeRCluster_IDs);
284  m_jFEXSmallRJetAlgoTool->buildSeeds();
285 
286  bool is_Jet_LM = m_jFEXSmallRJetAlgoTool->isSeedLocalMaxima(srJet_seedThresholdMeV);
287 
288  if(is_Jet_LM) {
289 
290  //getting the energies
291  int SRj_Et = m_jFEXSmallRJetAlgoTool->getSmallClusterET();
292  int LRj_Et = m_jFEXLargeRJetAlgoTool->getLargeClusterET(SRj_Et,m_jFEXLargeRJetAlgoTool->getRingET());
293  int seed_Et = m_jFEXSmallRJetAlgoTool->getSeedET();
294 
295  bool SRj_Sat = m_jFEXSmallRJetAlgoTool->getSRjetSat();
296  bool LRj_Sat = SRj_Sat || m_jFEXLargeRJetAlgoTool->getLRjetSat();
297 
298  int meta_LM = meta;
299  int mphi_LM = mphi;
300 
301 
302  //Creating SR TOB
303  uint32_t SRJet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, mphi_LM, meta_LM, SRj_Et, SRj_Sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
304 
305  std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
306  jJ_tob->initialize(m_id,m_jfexid,SRJet_tobword,thr_jJ.resolutionMeV(),m_jTowersIDs_Thin[mphi_LM][meta_LM],seed_Et);
307  if ( SRJet_tobword != 0 ){
308  m_SRJet_tobwords.push_back(std::move(jJ_tob));
309  }
310 
311  //Creating LR TOB
312  uint32_t LRJet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, mphi_LM, meta_LM, LRj_Et, LRj_Sat, thr_jLJ.resolutionMeV(), thr_jLJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
313 
314  std::unique_ptr<jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
315  jLJ_tob->initialize(m_id,m_jfexid,LRJet_tobword,thr_jLJ.resolutionMeV(),m_jTowersIDs_Thin[mphi_LM][meta_LM],seed_Et);
316  if ( LRJet_tobword != 0 ) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
317 
318  }
319  // ******** jTau algorithm ********
320 
321  ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
322  m_jFEXtauAlgoTool->setup(TT_seed_ID);
323  bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima();
324 
325  // Save TOB is tau is a local maxima
326  if ( is_tau_LocalMax ) {
327 
328  //calculates the 1st energy ring
329  m_jFEXtauAlgoTool->setFirstEtRing(TT_First_ETring);
330 
331 
332  uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
333 
334  std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
335  jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),m_jTowersIDs_Thin[mphi][meta]);
336 
337  if ( jTau_tobword != 0 ){
338  m_tau_tobwords.push_back(std::move(jTau_tob));
339  }
340  }
341  }
342  }
343  } //end of if statement for checking if in central jfex modules
344 
345  //FCAL region algorithm
346  if(m_jfexid ==0 || m_jfexid ==5) {
347 
348  //**********Forward Jets***********************
349  ATH_CHECK(m_jFEXForwardJetsAlgoTool->safetyTest());
350  ATH_CHECK(m_jFEXForwardJetsAlgoTool->reset());
351  m_jFEXForwardJetsAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
352  m_jFEXForwardJetsAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid);
353 
354  m_FCALJets = m_jFEXForwardJetsAlgoTool->calculateJetETs(srJet_seedThresholdMeV);
355  for(std::unordered_map<int, jFEXForwardJetsInfo>::iterator it = m_FCALJets.begin(); it!=(m_FCALJets.end()); ++it) {
356 
357  uint32_t TTID = it->first;
358  jFEXForwardJetsInfo FCALJets = it->second;
359 
360  int iphi = FCALJets.getCentreLocalTTPhi();
361  int ieta = FCALJets.getCentreLocalTTEta();
362  m_SRJetET = FCALJets.getSeedET() + FCALJets.getFirstEnergyRingET();
363  m_LRJetET = m_SRJetET + FCALJets.getSecondEnergyRingET();
364  int seedET = FCALJets.getSeedET();
365 
366  bool SRJ_sat = FCALJets.getSRjetSat();
367 
368  uint32_t SRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, iphi, ieta, m_SRJetET, SRJ_sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
369 
370  std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
371  jJ_tob->initialize(m_id,m_jfexid,SRFCAL_Jet_tobword,thr_jJ.resolutionMeV(),TTID,seedET);
372 
373  if ( SRFCAL_Jet_tobword != 0 ){
374  m_SRJet_tobwords.push_back(std::move(jJ_tob));
375  }
376 
377  if(std::fabs(FCALJets.getCentreTTEta())<2.51){
378  bool LRJ_sat = FCALJets.getLRjetSat();
379  uint32_t LRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, iphi, ieta, m_LRJetET, LRJ_sat, thr_jLJ.resolutionMeV(),thr_jLJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
380 
381  std::unique_ptr<jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
382  jLJ_tob->initialize(m_id,m_jfexid,LRFCAL_Jet_tobword,thr_jLJ.resolutionMeV(),TTID);
383  if ( LRFCAL_Jet_tobword != 0 ) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
384  }
385 
386  }
387  //********** Forward Electrons ***********************
388  ATH_CHECK(m_jFEXForwardElecAlgoTool->safetyTest());
389  ATH_CHECK(m_jFEXForwardElecAlgoTool->reset());
390  m_jFEXForwardElecAlgoTool->setFPGAEnergy(m_map_EM_Etvalues_FPGA,m_map_HAD_Etvalues_FPGA);
391  m_jFEXForwardElecAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid,m_id);
392  m_ForwardElecs = m_jFEXForwardElecAlgoTool->calculateEDM();
393 
395  SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
396  const TrigConf::L1ThrExtraInfo_jEM & thr_jEM = l1Menu->thrExtraInfo().jEM();
397  const uint jFEXETResolution = thr_jEM.resolutionMeV();//200
398  std::string str_jfexname = m_jfex_string[m_jfexid];
399  uint minEtThreshold = thr_jEM.ptMinToTopoMeV(str_jfexname)/jFEXETResolution;
400  //uint Cval[9] = {1,2,3,20,30,40,20,30,40};//C values for iso, emfr1 and emfr2
401  std::vector<int> Ciso;
402  std::vector<int> Chad1;
403  std::vector<int> Chad2;
404 
405  for(std::unordered_map<uint, jFEXForwardElecInfo>::iterator itel = m_ForwardElecs.begin(); itel!=(m_ForwardElecs.end()); ++itel) {
406  uint32_t TTID = itel->first;
407  jFEXForwardElecInfo elCluster = itel->second;
408  uint meta = elCluster.getCoreIeta();//check whether this is the one used by the Trigger conf
409 
410  //retrieve jet rejection thresholds from trigger configuration
411  const auto & wp_loose = thr_jEM.isolation(TrigConf::Selection::WP::LOOSE, meta);
412  const auto & wp_medium = thr_jEM.isolation(TrigConf::Selection::WP::MEDIUM, meta);
413  const auto & wp_tight = thr_jEM.isolation(TrigConf::Selection::WP::TIGHT, meta);
414  Ciso.clear();
415  Chad1.clear();
416  Chad2.clear();
417  Ciso.push_back(wp_loose.iso_fw());
418  Ciso.push_back(wp_medium.iso_fw());
419  Ciso.push_back(wp_tight.iso_fw());
420  Chad1.push_back(wp_loose.frac_fw());
421  Chad1.push_back(wp_medium.frac_fw());
422  Chad1.push_back(wp_tight.frac_fw());
423  Chad2.push_back(wp_loose.frac2_fw());
424  Chad2.push_back(wp_medium.frac2_fw());
425  Chad2.push_back(wp_tight.frac2_fw());
426  int Cval[9] = {Ciso[0], Ciso[1], Ciso[2], Chad1[0], Chad1[1], Chad1[2], Chad2[0], Chad2[1], Chad2[2]};
427 
428  elCluster.setup(Cval,jFEXETResolution);
429  elCluster.calcFwdElEDM();
430 
431  uint etEM = elCluster.getEt();
432  uint32_t FwdEl_tobword = elCluster.getTobWord();
433 
434 
435  std::vector<uint32_t> FwdEltob_aux{FwdEl_tobword,TTID};
436  if ( FwdEl_tobword != 0 && etEM>minEtThreshold) m_FwdEl_tobwords.push_back(FwdEltob_aux);
437  }
438 
439  //******************************** TAU **********************************************
440  int jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}};
441  int max_meta=17;
442 
443  if(m_jfexid ==0) {
444  for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
445  for(int j=28; j<(FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-6); j++) { //lower values of j (j<28) are the Fcals not entering in the jFEX tau range
446  jTowersIDs[i][j-28+8]=m_jTowersIDs_Wide[i][j]; // second argument in m_jTowersIDs is to center the FPGA core area in te same region as the central FPGAs
447  }
448  }
449 
450  }
451  else if(m_jfexid ==5 ) {
452 
453  // Filling m_jTowersIDs with the m_jTowersIDs_Wide ID values up to 2.5 eta
454  for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
455  for(int j=4; j<17; j++) { //higher values of j (j>16) are the Fcals not entering in the jFEX tau range
456  jTowersIDs[i][j]=m_jTowersIDs_Wide[i][j];
457  }
458  }
459  }
460  ATH_MSG_DEBUG("============================ jFEXtauAlgo ============================");
461  ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
462  m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
463  for(int mphi = 8; mphi < 24; mphi++) {
464  for(int meta = 8; meta < max_meta; meta++) {
465 
466  bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima_fwd(jTowersIDs[mphi][meta]);
467 
468  // Save TOB is tau is a local maxima
469  if ( is_tau_LocalMax ) {
470 
471  uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
472 
473  std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
474  jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),jTowersIDs[mphi][meta]);
475  if ( jTau_tobword != 0 ){
476  m_tau_tobwords.push_back(std::move(jTau_tob));
477  }
478  }
479  }
480  }
481  } //end of if statement for checking if in central jfex modules
482  return StatusCode::SUCCESS;
483 } //end of the execute function

◆ extraDeps_update_handler()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::extraDeps_update_handler ( Gaudi::Details::PropertyBase &  ExtraDeps)
protectedinherited

Add StoreName to extra input/output deps as needed.

use the logic of the VarHandleKey to parse the DataObjID keys supplied via the ExtraInputs and ExtraOuputs Properties to add the StoreName if it's not explicitly given

◆ getFwdElTOBs()

std::vector< std::vector< uint32_t > > LVL1::jFEXFPGA::getFwdElTOBs ( )
overridevirtual

sorted Electron tobs

Implements LVL1::IjFEXFPGA.

Definition at line 560 of file jFEXFPGA.cxx.

561  {
562  auto tobsSort = m_FwdEl_tobwords;
563 
564  ATH_MSG_DEBUG("number of Forward Elec tobs: " << tobsSort.size() << " in FPGA: " << m_id<< " before truncation");
565  //sort tobs by their et
566  std::sort (tobsSort.begin(), tobsSort.end(), etFwdElSort);
567 
568  return tobsSort;
569 
570  }

◆ getLargeRJetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getLargeRJetTOBs ( )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 542 of file jFEXFPGA.cxx.

543 {
544 
545 
546  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
547  tobsSort.clear();
548 
549  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
550  for(auto &j : m_LRJet_tobwords) {
551  tobsSort.push_back(std::move(j));
552  }
553  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jLJ_etBit, 0x1fff));
554 
555  return tobsSort;
556 
557 }

◆ getMetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getMetTOBs ( )
overridevirtual

Form a tob word out of the potential candidate MET tob.

Implements LVL1::IjFEXFPGA.

Definition at line 603 of file jFEXFPGA.cxx.

603  {
604 
605  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
606  tobsSort.clear();
607 
608  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
609  for(auto &j : m_Met_tobwords) {
610  tobsSort.push_back(std::move(j));
611  }
612 
613  return tobsSort;
614 
615 }

◆ getSmallRJetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getSmallRJetTOBs ( )
overridevirtual

Form a tob word out of the potential candidate SmallRJet tob.

Implements LVL1::IjFEXFPGA.

Definition at line 526 of file jFEXFPGA.cxx.

527 {
528 
529  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
530  tobsSort.clear();
531 
532  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
533  for(auto &j : m_SRJet_tobwords) {
534  tobsSort.push_back(std::move(j));
535  }
536  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jJ_etBit, 0x7ff));
537 
538  return tobsSort;
539 
540 }

◆ getSumEtTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getSumEtTOBs ( )
overridevirtual

Form a tob word out of the potential candidate SumET tob.

Implements LVL1::IjFEXFPGA.

Definition at line 587 of file jFEXFPGA.cxx.

587  {
588 
589  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
590  tobsSort.clear();
591 
592  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
593  for(auto &j : m_sumET_tobwords) {
594  tobsSort.push_back(std::move(j));
595  }
596 
597  return tobsSort;
598 
599 }

◆ getTauTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getTauTOBs ( )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 573 of file jFEXFPGA.cxx.

573  {
574 
575  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
576  tobsSort.clear();
577 
578  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
579  for(auto &j : m_tau_tobwords) {
580  tobsSort.push_back(std::move(j));
581  }
582  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jTau_etBit, 0x7ff));
583 
584  return tobsSort;
585 }

◆ getTTowerET()

int LVL1::jFEXFPGA::getTTowerET ( unsigned int  TTID)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 645 of file jFEXFPGA.cxx.

645  {
646 
647  return getTTowerET_EM(TTID)+getTTowerET_HAD(TTID);
648 
649 }

◆ getTTowerET_EM()

int LVL1::jFEXFPGA::getTTowerET_EM ( unsigned int  TTID)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 619 of file jFEXFPGA.cxx.

619  {
620 
621  if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
622  return m_map_EM_Etvalues_FPGA[TTID][0];
623  }
624 
625  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_EM, TTower ID not found in map: " << TTID );
626  return -99999;
627 
628 }

◆ getTTowerET_forMET()

int LVL1::jFEXFPGA::getTTowerET_forMET ( unsigned int  TTID)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 653 of file jFEXFPGA.cxx.

653  {
654 
655  int tmp_EM = 0;
656  if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
657  tmp_EM = m_map_EM_Etvalues_FPGA[TTID][1];
658  }
659  else{
660  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (EM energy), TTower ID not found in map: " << TTID );
661  tmp_EM = -99999;
662  }
663 
664 
665  int tmp_HAD = 0;
666  if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
667  tmp_HAD = m_map_HAD_Etvalues_FPGA[TTID][1];
668  }
669  else{
670  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (HAD energy), TTower ID not found in map: " << TTID );
671  tmp_HAD = -99999;
672  }
673 
674 
675  return tmp_EM + tmp_HAD;
676 
677 }

◆ getTTowerET_HAD()

int LVL1::jFEXFPGA::getTTowerET_HAD ( unsigned int  TTID)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 632 of file jFEXFPGA.cxx.

632  {
633 
634  if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
635  return m_map_HAD_Etvalues_FPGA[TTID][0];
636  }
637 
638  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_HAD, TTower ID not found in map: " << TTID );
639  return -99999;
640 
641 }

◆ getTTowerET_SG()

int LVL1::jFEXFPGA::getTTowerET_SG ( unsigned int  TTID)
private

Definition at line 681 of file jFEXFPGA.cxx.

681  {
682 
683  if(TTID == 0){
684  return -999;
685  }
686  SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey);
687  const LVL1::jTower * tmpTower = jTowerContainer->findTower(TTID);
688  return tmpTower->getTotalET();
689 }

◆ ID()

virtual int LVL1::jFEXFPGA::ID ( )
inlineoverridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 68 of file jFEXFPGA.h.

68 {return m_id;}

◆ init()

StatusCode LVL1::jFEXFPGA::init ( int  id,
int  efexid 
)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 52 of file jFEXFPGA.cxx.

52  {
53  m_id = id;
54  m_jfexid = jfexid;
55 
56  return StatusCode::SUCCESS;
57 
58 }

◆ initialize()

StatusCode LVL1::jFEXFPGA::initialize ( )
overridevirtual

standard Athena-Algorithm method

Definition at line 44 of file jFEXFPGA.cxx.

44  {
45 
46  ATH_CHECK(m_jTowerContainerKey.initialize());
47  ATH_CHECK(m_l1MenuKey.initialize());
48  ATH_CHECK(m_jFEXtauAlgoTool.retrieve());
49  return StatusCode::SUCCESS;
50 }

◆ inputHandles()

virtual std::vector<Gaudi::DataHandle*> AthCommonDataStore< AthCommonMsg< AlgTool > >::inputHandles ( ) const
overridevirtualinherited

Return this algorithm's input handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ interfaceID()

const InterfaceID & LVL1::IjFEXFPGA::interfaceID ( )
inlinestaticinherited

Definition at line 73 of file IjFEXFPGA.h.

74  {
75  return IID_IjFEXFPGA;
76  }

◆ msg() [1/2]

MsgStream& AthCommonMsg< AlgTool >::msg ( ) const
inlineinherited

Definition at line 24 of file AthCommonMsg.h.

24  {
25  return this->msgStream();
26  }

◆ msg() [2/2]

MsgStream& AthCommonMsg< AlgTool >::msg ( const MSG::Level  lvl) const
inlineinherited

Definition at line 27 of file AthCommonMsg.h.

27  {
28  return this->msgStream(lvl);
29  }

◆ msgLvl()

bool AthCommonMsg< AlgTool >::msgLvl ( const MSG::Level  lvl) const
inlineinherited

Definition at line 30 of file AthCommonMsg.h.

30  {
31  return this->msgLevel(lvl);
32  }

◆ outputHandles()

virtual std::vector<Gaudi::DataHandle*> AthCommonDataStore< AthCommonMsg< AlgTool > >::outputHandles ( ) const
overridevirtualinherited

Return this algorithm's output handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ renounce()

std::enable_if_t<std::is_void_v<std::result_of_t<decltype(&T::renounce)(T)> > && !std::is_base_of_v<SG::VarHandleKeyArray, T> && std::is_base_of_v<Gaudi::DataHandle, T>, void> AthCommonDataStore< AthCommonMsg< AlgTool > >::renounce ( T &  h)
inlineprotectedinherited

Definition at line 380 of file AthCommonDataStore.h.

381  {
382  h.renounce();
383  PBASE::renounce (h);
384  }

◆ renounceArray()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::renounceArray ( SG::VarHandleKeyArray &  handlesArray)
inlineprotectedinherited

remove all handles from I/O resolution

Definition at line 364 of file AthCommonDataStore.h.

364  {
365  handlesArray.renounce();
366  }

◆ reset()

void LVL1::jFEXFPGA::reset ( )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 60 of file jFEXFPGA.cxx.

60  {
61 
62  m_id = -1;
63  m_jfexid = -1;
64  m_tau_tobwords.clear();
65  m_SRJet_tobwords.clear();
66  m_LRJet_tobwords.clear();
67  m_sumET_tobwords.clear();
68  m_Met_tobwords.clear();
69  m_map_Etvalues_FPGA.clear();
70  m_map_EM_Etvalues_FPGA.clear();
71  m_map_HAD_Etvalues_FPGA.clear();
72  m_FwdEl_tobwords.clear();
73 }

◆ SetTowersAndCells_SG() [1/2]

void LVL1::jFEXFPGA::SetTowersAndCells_SG ( int  tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 503 of file jFEXFPGA.cxx.

503  {
504 
505  const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
506  const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
507 
508  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Thin[0][0]);
509 
510  //this prints out the jTower IDs that each FPGA is responsible for
511  ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
512 
513  for (int thisRow=rows-1; thisRow>=0; thisRow--) {
514  for (int thisCol=0; thisCol<cols; thisCol++) {
515  if(thisCol != cols-1) {
516  ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " ");
517  }
518  else {
519  ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " |");
520  }
521  }
522  }
523 
524 }

◆ SetTowersAndCells_SG() [2/2]

void LVL1::jFEXFPGA::SetTowersAndCells_SG ( int  tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 485 of file jFEXFPGA.cxx.

485  {
486 
487  const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
488  const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
489 
490  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Wide[0][0]);
491 
492  ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
493 
494  for (int thisRow=rows-1; thisRow>=0; thisRow--){
495  for (int thisCol=0; thisCol<cols; thisCol++){
496  if(thisCol != cols-1){ ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " "); }
497  else { ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " |"); }
498  }
499  }
500 
501 }

◆ sysInitialize()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysInitialize ( )
overridevirtualinherited

Perform system initialization for an algorithm.

We override this to declare all the elements of handle key arrays at the end of initialization. See comments on updateVHKA.

Reimplemented in DerivationFramework::CfAthAlgTool, AthCheckedComponent< AthAlgTool >, AthCheckedComponent<::AthAlgTool >, and asg::AsgMetadataTool.

◆ sysStart()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysStart ( )
overridevirtualinherited

Handle START transition.

We override this in order to make sure that conditions handle keys can cache a pointer to the conditions container.

◆ TOBetSort()

template<class TOBObjectClass >
static bool LVL1::jFEXFPGA::TOBetSort ( const TOBObjectClass &  i,
const TOBObjectClass &  j,
uint  bits,
uint  mask 
)
inlinestaticprivate

Internal data.

Definition at line 97 of file jFEXFPGA.h.

97  {
98  return (((i->getWord() >> bits ) & mask)>((j->getWord() >> bits ) & mask));
99  }

◆ updateVHKA()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::updateVHKA ( Gaudi::Details::PropertyBase &  )
inlineinherited

Definition at line 308 of file AthCommonDataStore.h.

308  {
309  // debug() << "updateVHKA for property " << p.name() << " " << p.toString()
310  // << " size: " << m_vhka.size() << endmsg;
311  for (auto &a : m_vhka) {
312  std::vector<SG::VarHandleKey*> keys = a->keys();
313  for (auto k : keys) {
314  k->setOwner(this);
315  }
316  }
317  }

Member Data Documentation

◆ m_detStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_detStore
privateinherited

Pointer to StoreGate (detector store by default)

Definition at line 393 of file AthCommonDataStore.h.

◆ m_evtStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_evtStore
privateinherited

Pointer to StoreGate (event store by default)

Definition at line 390 of file AthCommonDataStore.h.

◆ m_FCALJets

std::unordered_map<int, jFEXForwardJetsInfo> LVL1::jFEXFPGA::m_FCALJets
private

Definition at line 125 of file jFEXFPGA.h.

◆ m_ForwardElecs

std::unordered_map<uint, jFEXForwardElecInfo> LVL1::jFEXFPGA::m_ForwardElecs
private

Definition at line 126 of file jFEXFPGA.h.

◆ m_FwdEl_tobwords

std::vector<std::vector<uint32_t> > LVL1::jFEXFPGA::m_FwdEl_tobwords
private

Definition at line 114 of file jFEXFPGA.h.

◆ m_id

int LVL1::jFEXFPGA::m_id {}
private

Definition at line 111 of file jFEXFPGA.h.

◆ m_IjFEXFormTOBsTool

ToolHandle<IjFEXFormTOBs> LVL1::jFEXFPGA::m_IjFEXFormTOBsTool {this, "IjFEXFormTOBsTool", "LVL1::jFEXFormTOBs", "Tool that forms TOB words"}
private

Definition at line 143 of file jFEXFPGA.h.

◆ m_jfex_string

std::string LVL1::jFEXFPGA::m_jfex_string[6] = {"1C","2C","3C","3A","2A","1A"}
private

Definition at line 146 of file jFEXFPGA.h.

◆ m_jFEXForwardElecAlgoTool

ToolHandle<IjFEXForwardElecAlgo> LVL1::jFEXFPGA::m_jFEXForwardElecAlgoTool {this, "jFEXForwardElecAlgoTool" , "LVL1::jFEXForwardElecAlgo" , "Tool that runs the jFEX FCAL Electrons algorithm"}
private

Definition at line 141 of file jFEXFPGA.h.

◆ m_jFEXForwardJetsAlgoTool

ToolHandle<IjFEXForwardJetsAlgo> LVL1::jFEXFPGA::m_jFEXForwardJetsAlgoTool {this, "jFEXForwardJetsAlgoTool" , "LVL1::jFEXForwardJetsAlgo" , "Tool that runs the jFEX FCAL Jets algorithm"}
private

Definition at line 140 of file jFEXFPGA.h.

◆ m_jfexid

int LVL1::jFEXFPGA::m_jfexid {}
private

Definition at line 112 of file jFEXFPGA.h.

◆ m_jFEXLargeRJetAlgoTool

ToolHandle<IjFEXLargeRJetAlgo> LVL1::jFEXFPGA::m_jFEXLargeRJetAlgoTool {this, "jFEXLargeRJetAlgoTool", "LVL1::jFEXLargeRJetAlgo", "Tool that runs the jFEX Large R Jet algorithm"}
private

Definition at line 136 of file jFEXFPGA.h.

◆ m_jFEXmetAlgoTool

ToolHandle<IjFEXmetAlgo> LVL1::jFEXFPGA::m_jFEXmetAlgoTool {this, "jFEXmetAlgoTool" , "LVL1::jFEXmetAlgo" , "Tool that runs the jFEX met algorithm"}
private

Definition at line 139 of file jFEXFPGA.h.

◆ m_jFEXPileupAndNoiseTool

ToolHandle<IjFEXPileupAndNoise> LVL1::jFEXFPGA::m_jFEXPileupAndNoiseTool {this, "jFEXPileupAndNoiseTool", "LVL1::jFEXPileupAndNoise", "Tool that applies Pileup and Noise"}
private

Definition at line 142 of file jFEXFPGA.h.

◆ m_jFEXSmallRJetAlgoTool

ToolHandle<IjFEXSmallRJetAlgo> LVL1::jFEXFPGA::m_jFEXSmallRJetAlgoTool {this, "jFEXSmallRJetAlgoTool", "LVL1::jFEXSmallRJetAlgo", "Tool that runs the jFEX Small R Jet algorithm"}
private

Definition at line 135 of file jFEXFPGA.h.

◆ m_jFEXsumETAlgoTool

ToolHandle<IjFEXsumETAlgo> LVL1::jFEXFPGA::m_jFEXsumETAlgoTool {this, "jFEXsumETAlgoTool" , "LVL1::jFEXsumETAlgo" , "Tool that runs the jFEX sumET algorithm"}
private

Definition at line 138 of file jFEXFPGA.h.

◆ m_jFEXtauAlgoTool

ToolHandle<IjFEXtauAlgo> LVL1::jFEXFPGA::m_jFEXtauAlgoTool {this, "jFEXtauAlgoTool" , "LVL1::jFEXtauAlgo" , "Tool that runs the jFEX tau algorithm"}
private

Definition at line 137 of file jFEXFPGA.h.

◆ m_jTowerContainerKey

SG::ReadHandleKey<LVL1::jTowerContainer> LVL1::jFEXFPGA::m_jTowerContainerKey {this, "MyETowers", "jTowerContainer", "Input container for jTowers"}
private

Definition at line 133 of file jFEXFPGA.h.

◆ m_jTowersColl

std::unordered_map<int,jTower> LVL1::jFEXFPGA::m_jTowersColl
private

Definition at line 119 of file jFEXFPGA.h.

◆ m_jTowersIDs_Thin

int LVL1::jFEXFPGA::m_jTowersIDs_Thin[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}}
private

Definition at line 117 of file jFEXFPGA.h.

◆ m_jTowersIDs_Wide

int LVL1::jFEXFPGA::m_jTowersIDs_Wide[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}}
private

Definition at line 116 of file jFEXFPGA.h.

◆ m_l1MenuKey

SG::ReadHandleKey<TrigConf::L1Menu> LVL1::jFEXFPGA::m_l1MenuKey {this, "L1TriggerMenu", "DetectorStore+L1TriggerMenu","Name of the L1Menu object to read configuration from"}
private

Definition at line 134 of file jFEXFPGA.h.

◆ m_LRJet_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_LRJet_tobwords
private

Definition at line 107 of file jFEXFPGA.h.

◆ m_LRJetET

int LVL1::jFEXFPGA::m_LRJetET {}
private

Definition at line 129 of file jFEXFPGA.h.

◆ m_map_EM_Etvalues_FPGA

std::unordered_map<int,std::vector<int> > LVL1::jFEXFPGA::m_map_EM_Etvalues_FPGA
private

Definition at line 122 of file jFEXFPGA.h.

◆ m_map_Etvalues_FPGA

std::unordered_map<int,std::vector<int> > LVL1::jFEXFPGA::m_map_Etvalues_FPGA
private

Definition at line 120 of file jFEXFPGA.h.

◆ m_map_HAD_Etvalues_FPGA

std::unordered_map<int,std::vector<int> > LVL1::jFEXFPGA::m_map_HAD_Etvalues_FPGA
private

Definition at line 121 of file jFEXFPGA.h.

◆ m_Met_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_Met_tobwords
private

Definition at line 109 of file jFEXFPGA.h.

◆ m_sCellsCollection

CaloCellContainer LVL1::jFEXFPGA::m_sCellsCollection
private

Definition at line 131 of file jFEXFPGA.h.

◆ m_SRJet_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_SRJet_tobwords
private

Definition at line 106 of file jFEXFPGA.h.

◆ m_SRJetET

int LVL1::jFEXFPGA::m_SRJetET {}
private

Definition at line 128 of file jFEXFPGA.h.

◆ m_sumET_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_sumET_tobwords
private

Definition at line 108 of file jFEXFPGA.h.

◆ m_tau_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_tau_tobwords
private

Definition at line 105 of file jFEXFPGA.h.

◆ m_varHandleArraysDeclared

bool AthCommonDataStore< AthCommonMsg< AlgTool > >::m_varHandleArraysDeclared
privateinherited

Definition at line 399 of file AthCommonDataStore.h.

◆ m_vhka

std::vector<SG::VarHandleKeyArray*> AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
privateinherited

Definition at line 398 of file AthCommonDataStore.h.

The documentation for this class was generated from the following files:
xAOD::iterator
JetConstituentVector::iterator iterator
Definition: JetConstituentVector.cxx:68
jTowerContainer
Container class for jTower.
TrigConf::Selection::WP::LOOSE
@ LOOSE
LVL1::jFEXFPGA::m_FwdEl_tobwords
std::vector< std::vector< uint32_t > > m_FwdEl_tobwords
Definition: jFEXFPGA.h:114
LVL1::FEXAlgoSpaceDefs::jJ_etBit
constexpr static int jJ_etBit
Definition: FEXAlgoSpaceDefs.h:119
LVL1::jFEXFPGA::m_l1MenuKey
SG::ReadHandleKey< TrigConf::L1Menu > m_l1MenuKey
Definition: jFEXFPGA.h:134
TrigConf::L1ThrExtraInfo_jJ::seedThresholdMeV
unsigned int seedThresholdMeV(const std::string &module) const
Definition: L1ThrExtraInfo.h:414
LVL1::jFEXFPGA::m_LRJetET
int m_LRJetET
Definition: jFEXFPGA.h:129
LVL1::FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width
constexpr static int jFEX_thin_algoSpace_width
Definition: FEXAlgoSpaceDefs.h:26
LVL1::jFEXFPGA::m_jTowerContainerKey
SG::ReadHandleKey< LVL1::jTowerContainer > m_jTowerContainerKey
Definition: jFEXFPGA.h:133
TrigConf::L1ThrExtraInfo_jEM::isolation
const WorkingPoints_jEM & isolation(TrigConf::Selection::WP wp, int eta) const
Definition: L1ThrExtraInfo.h:215
LVL1::jFEXFPGA::m_jFEXtauAlgoTool
ToolHandle< IjFEXtauAlgo > m_jFEXtauAlgoTool
Definition: jFEXFPGA.h:137
xAOD::uint32_t
setEventNumber uint32_t
Definition: EventInfo_v1.cxx:127
SG::ReadHandle
Definition: StoreGate/StoreGate/ReadHandle.h:70
AthCommonDataStore::declareProperty
Gaudi::Details::PropertyBase & declareProperty(Gaudi::Property< T > &t)
Definition: AthCommonDataStore.h:145
LVL1::jFEXFPGA::m_jfex_string
std::string m_jfex_string[6]
Definition: jFEXFPGA.h:146
TrigConf::L1ThrExtraInfo_jTE
Definition: L1ThrExtraInfo.h:554
LVL1::jFEXFPGA::m_jFEXSmallRJetAlgoTool
ToolHandle< IjFEXSmallRJetAlgo > m_jFEXSmallRJetAlgoTool
Definition: jFEXFPGA.h:135
skel.it
it
Definition: skel.GENtoEVGEN.py:396
TrigConf::L1ThrExtraInfo_jJ::ptMinToTopoMeV
unsigned int ptMinToTopoMeV(const std::string &module) const
Definition: L1ThrExtraInfo.h:398
AthCommonDataStore< AthCommonMsg< AlgTool > >::m_evtStore
StoreGateSvc_t m_evtStore
Pointer to StoreGate (event store by default)
Definition: AthCommonDataStore.h:390
AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
std::vector< SG::VarHandleKeyArray * > m_vhka
Definition: AthCommonDataStore.h:398
LVL1::jFEXFPGA::m_Met_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_Met_tobwords
Definition: jFEXFPGA.h:109
LVL1::jFEXFPGA::m_sumET_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_sumET_tobwords
Definition: jFEXFPGA.h:108
LVL1::FEXAlgoSpaceDefs::jFEX_algoSpace_height
constexpr static int jFEX_algoSpace_height
Definition: FEXAlgoSpaceDefs.h:27
read_hist_ntuple.t
t
Definition: read_hist_ntuple.py:5
LVL1::jFEXFPGA::getTTowerET_HAD
int getTTowerET_HAD(unsigned int TTID) override
Definition: jFEXFPGA.cxx:632
SG::VarHandleKey::key
const std::string & key() const
Return the StoreGate ID for the referenced object.
Definition: AthToolSupport/AsgDataHandles/Root/VarHandleKey.cxx:141
python.utils.AtlRunQueryLookup.mask
string mask
Definition: AtlRunQueryLookup.py:460
SG::VarHandleKeyArray::setOwner
virtual void setOwner(IDataHandleHolder *o)=0
LVL1::jFEXFPGA::m_jFEXForwardJetsAlgoTool
ToolHandle< IjFEXForwardJetsAlgo > m_jFEXForwardJetsAlgoTool
Definition: jFEXFPGA.h:140
IDTPMcnv.htype
htype
Definition: IDTPMcnv.py:29
TrigConf::L1ThrExtraInfo_jXE
Definition: L1ThrExtraInfo.h:542
LVL1::jFEXFPGA::m_SRJet_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_SRJet_tobwords
Definition: jFEXFPGA.h:106
LVL1::jFEXFPGA::m_tau_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_tau_tobwords
Definition: jFEXFPGA.h:105
uint
unsigned int uint
Definition: LArOFPhaseFill.cxx:20
TrigConf::L1ThrExtraInfo_jTAU::ptMinToTopoMeV
unsigned int ptMinToTopoMeV(const std::string &module) const
Definition: L1ThrExtraInfo.h:320
beamspotnt.cols
list cols
Definition: bin/beamspotnt.py:1114
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Return a non-const reference to the HandleKey.
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The jTower class is an interface object for jFEX trigger algorithms The purposes are twofold:
Definition: jTower.h:40
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