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LVL1::jFEXFPGA Class Reference

The jFEXFPGA class defines the structure of a single jFEX FPGA Its purpose is: More...

#include <jFEXFPGA.h>

Inheritance diagram for LVL1::jFEXFPGA:

Public Member Functions

 jFEXFPGA (const std::string &type, const std::string &name, const IInterface *parent)
 Constructors.
virtual StatusCode initialize () override
 standard Athena-Algorithm method
virtual ~jFEXFPGA ()
 Destructor.
virtual StatusCode init (int id, int efexid) override
virtual StatusCode execute (jFEXOutputCollection *inputOutputCollection, const std::pair< unsigned int, const std::vector< int > & > &jetCalibrationParameters) override
virtual void reset () override
virtual int ID () override
virtual void SetTowersAndCells_SG (int[][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]) override
virtual void SetTowersAndCells_SG (int[][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]) override
virtual std::vector< std::unique_ptr< jFEXTOB > > getSmallRJetTOBs () override
 Form a tob word out of the potential candidate SmallRJet tob.
virtual std::vector< std::unique_ptr< jFEXTOB > > getLargeRJetTOBs () override
virtual std::vector< std::vector< uint32_t > > getFwdElTOBs () override
 sorted Electron tobs
virtual std::vector< std::unique_ptr< jFEXTOB > > getTauTOBs () override
virtual std::vector< std::unique_ptr< jFEXTOB > > getSumEtTOBs () override
 Form a tob word out of the potential candidate SumET tob.
virtual std::vector< std::unique_ptr< jFEXTOB > > getMetTOBs () override
 Form a tob word out of the potential candidate MET tob.
int getTTowerET_EM (unsigned int TTID) override
int getTTowerET_HAD (unsigned int TTID) override
int getTTowerET (unsigned int TTID) override
int getTTowerET_forMET (unsigned int TTID) override
ServiceHandle< StoreGateSvc > & evtStore ()
 The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.
const ServiceHandle< StoreGateSvc > & detStore () const
 The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.
virtual StatusCode sysInitialize () override
 Perform system initialization for an algorithm.
virtual StatusCode sysStart () override
 Handle START transition.
virtual std::vector< Gaudi::DataHandle * > inputHandles () const override
 Return this algorithm's input handles.
virtual std::vector< Gaudi::DataHandle * > outputHandles () const override
 Return this algorithm's output handles.
Gaudi::Details::PropertyBase & declareProperty (Gaudi::Property< T, V, H > &t)
void updateVHKA (Gaudi::Details::PropertyBase &)
MsgStream & msg () const
bool msgLvl (const MSG::Level lvl) const

Static Public Member Functions

static const InterfaceID & interfaceID ()

Protected Member Functions

void renounceArray (SG::VarHandleKeyArray &handlesArray)
 remove all handles from I/O resolution
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > renounce (T &h)
void extraDeps_update_handler (Gaudi::Details::PropertyBase &ExtraDeps)
 Add StoreName to extra input/output deps as needed.

Private Types

typedef ServiceHandle< StoreGateSvc > StoreGateSvc_t

Private Member Functions

int getTTowerET_SG (unsigned int TTID)
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyType &)
 specialization for handling Gaudi::Property<SG::VarHandleKey>

Static Private Member Functions

template<class TOBObjectClass>
static bool TOBetSort (const TOBObjectClass &i, const TOBObjectClass &j, uint bits, uint mask)
 Internal data.
static bool etFwdElSort (const std::vector< uint32_t > &i, const std::vector< uint32_t > &j)

Private Attributes

std::vector< std::unique_ptr< jFEXTOB > > m_tau_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_SRJet_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_LRJet_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_sumET_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_Met_tobwords
int m_id {}
int m_jfexid {}
std::vector< std::vector< uint32_t > > m_FwdEl_tobwords
int m_jTowersIDs_Wide [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}}
int m_jTowersIDs_Thin [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}}
std::unordered_map< int, jTower > m_jTowersColl
std::unordered_map< int, std::vector< int > > m_map_Etvalues_FPGA
std::unordered_map< int, std::vector< int > > m_map_HAD_Etvalues_FPGA
std::unordered_map< int, std::vector< int > > m_map_EM_Etvalues_FPGA
std::unordered_map< int, jFEXForwardJetsInfo > m_FCALJets
std::unordered_map< uint, jFEXForwardElecInfo > m_ForwardElecs
int m_SRJetET {}
int m_LRJetET {}
SG::ReadHandleKey< LVL1::jTowerContainer > m_jTowerContainerKey {this, "MyETowers", "jTowerContainer", "Input container for jTowers"}
SG::ReadHandleKey< TrigConf::L1Menu > m_l1MenuKey {this, "L1TriggerMenu", "DetectorStore+L1TriggerMenu","Name of the L1Menu object to read configuration from"}
ToolHandle< IjFEXSmallRJetAlgo > m_jFEXSmallRJetAlgoTool {this, "jFEXSmallRJetAlgoTool", "LVL1::jFEXSmallRJetAlgo", "Tool that runs the jFEX Small R Jet algorithm"}
ToolHandle< IjFEXLargeRJetAlgo > m_jFEXLargeRJetAlgoTool {this, "jFEXLargeRJetAlgoTool", "LVL1::jFEXLargeRJetAlgo", "Tool that runs the jFEX Large R Jet algorithm"}
ToolHandle< IjFEXtauAlgo > m_jFEXtauAlgoTool {this, "jFEXtauAlgoTool" , "LVL1::jFEXtauAlgo" , "Tool that runs the jFEX tau algorithm"}
ToolHandle< IjFEXsumETAlgo > m_jFEXsumETAlgoTool {this, "jFEXsumETAlgoTool" , "LVL1::jFEXsumETAlgo" , "Tool that runs the jFEX sumET algorithm"}
ToolHandle< IjFEXmetAlgo > m_jFEXmetAlgoTool {this, "jFEXmetAlgoTool" , "LVL1::jFEXmetAlgo" , "Tool that runs the jFEX met algorithm"}
ToolHandle< IjFEXForwardJetsAlgo > m_jFEXForwardJetsAlgoTool {this, "jFEXForwardJetsAlgoTool" , "LVL1::jFEXForwardJetsAlgo" , "Tool that runs the jFEX FCAL Jets algorithm"}
ToolHandle< IjFEXForwardElecAlgo > m_jFEXForwardElecAlgoTool {this, "jFEXForwardElecAlgoTool" , "LVL1::jFEXForwardElecAlgo" , "Tool that runs the jFEX FCAL Electrons algorithm"}
ToolHandle< IjFEXPileupAndNoise > m_jFEXPileupAndNoiseTool {this, "jFEXPileupAndNoiseTool", "LVL1::jFEXPileupAndNoise", "Tool that applies Pileup and Noise"}
ToolHandle< IjFEXFormTOBs > m_IjFEXFormTOBsTool {this, "IjFEXFormTOBsTool", "LVL1::jFEXFormTOBs", "Tool that forms TOB words"}
std::string m_jfex_string [6] = {"1C","2C","3C","3A","2A","1A"}
StoreGateSvc_t m_evtStore
 Pointer to StoreGate (event store by default)
StoreGateSvc_t m_detStore
 Pointer to StoreGate (detector store by default)
std::vector< SG::VarHandleKeyArray * > m_vhka
bool m_varHandleArraysDeclared

Detailed Description

The jFEXFPGA class defines the structure of a single jFEX FPGA Its purpose is:

  • to emulate the steps taken in processing data for a single jFEX FPGA in hardware and firmware
  • It will need to interact with jTowers and produce the jTOBs. It will be created and handed data by jFEXSim

Definition at line 51 of file jFEXFPGA.h.

Member Typedef Documentation

◆ StoreGateSvc_t

typedef ServiceHandle<StoreGateSvc> AthCommonDataStore< AthCommonMsg< AlgTool > >::StoreGateSvc_t
privateinherited

Definition at line 388 of file AthCommonDataStore.h.

Constructor & Destructor Documentation

◆ jFEXFPGA()

LVL1::jFEXFPGA::jFEXFPGA ( const std::string & type,
const std::string & name,
const IInterface * parent )

Constructors.

Definition at line 36 of file jFEXFPGA.cxx.

36 : AthAlgTool(type,name,parent) {
37 declareInterface<IjFEXFPGA>(this);
38}
AthAlgTool::AthAlgTool
AthAlgTool()
Default constructor:

◆ ~jFEXFPGA()

LVL1::jFEXFPGA::~jFEXFPGA ( )
virtual

Destructor.

Definition at line 41 of file jFEXFPGA.cxx.

42{
43}

Member Function Documentation

◆ declareGaudiProperty()

Gaudi::Details::PropertyBase & AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T, V, H > & hndl,
const SG::VarHandleKeyType &  )
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKey>

Definition at line 156 of file AthCommonDataStore.h.

158 {
159 return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
160 hndl.value(),
161 hndl.documentation());
162
163 }
AthCommonDataStore::declareProperty
Gaudi::Details::PropertyBase & declareProperty(Gaudi::Property< T, V, H > &t)
Definition AthCommonDataStore.h:145

◆ declareProperty()

Gaudi::Details::PropertyBase & AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( Gaudi::Property< T, V, H > & t)
inlineinherited

Definition at line 145 of file AthCommonDataStore.h.

145 {
146 typedef typename SG::HandleClassifier<T>::type htype;
147 return AthCommonDataStore<PBASE>::declareGaudiProperty(t, htype());
148 }
AthCommonDataStore::declareGaudiProperty
Gaudi::Details::PropertyBase & declareGaudiProperty(Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyType &)
specialization for handling Gaudi::Property<SG::VarHandleKey>
Definition AthCommonDataStore.h:156

◆ detStore()

const ServiceHandle< StoreGateSvc > & AthCommonDataStore< AthCommonMsg< AlgTool > >::detStore ( ) const
inlineinherited

The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 95 of file AthCommonDataStore.h.

95{ return m_detStore; }

◆ etFwdElSort()

bool LVL1::jFEXFPGA::etFwdElSort ( const std::vector< uint32_t > & i,
const std::vector< uint32_t > & j )
inlinestaticprivate

Definition at line 101 of file jFEXFPGA.h.

101{ return (((i.at(0) >> FEXAlgoSpaceDefs::jEM_etBit ) & 0x7ff )> ((j.at(0) >> FEXAlgoSpaceDefs::jEM_etBit) & 0x7ff ));}
LVL1::FEXAlgoSpaceDefs::jEM_etBit
static constexpr int jEM_etBit
Definition FEXAlgoSpaceDefs.h:113

◆ evtStore()

ServiceHandle< StoreGateSvc > & AthCommonDataStore< AthCommonMsg< AlgTool > >::evtStore ( )
inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 85 of file AthCommonDataStore.h.

85{ return m_evtStore; }

◆ execute()

StatusCode LVL1::jFEXFPGA::execute ( jFEXOutputCollection * inputOutputCollection,
const std::pair< unsigned int, const std::vector< int > & > & jetCalibrationParameters )
overridevirtual

Retrieve the L1 menu configuration

Implements LVL1::IjFEXFPGA.

Definition at line 78 of file jFEXFPGA.cxx.

78 {
79
80 // Retrieve the L1 menu configuration
81 SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
82
83 const TrigConf::L1ThrExtraInfo_jTAU & thr_jTAU = l1Menu->thrExtraInfo().jTAU();
84 const TrigConf::L1ThrExtraInfo_jJ & thr_jJ = l1Menu->thrExtraInfo().jJ();
85 const TrigConf::L1ThrExtraInfo_jLJ & thr_jLJ = l1Menu->thrExtraInfo().jLJ();
86 const TrigConf::L1ThrExtraInfo_jTE & thr_jTE = l1Menu->thrExtraInfo().jTE();
87 const TrigConf::L1ThrExtraInfo_jXE & thr_jXE = l1Menu->thrExtraInfo().jXE();
88
89 SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey/*,ctx*/);
90 if(!jTowerContainer.isValid()) {
91 ATH_MSG_ERROR("Could not retrieve container " << m_jTowerContainerKey.key() );
92 return StatusCode::FAILURE;
93 }
94
95 ATH_CHECK( m_jFEXPileupAndNoiseTool->safetyTest());
96 ATH_CHECK( m_jFEXPileupAndNoiseTool->reset());
97 if(m_jfexid == 0 || m_jfexid == 5) {
98 m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Wide);
99 }
100 else {
101 m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Thin);
102 }
103
104 //Calculating and sustracting pileup
105 const std::vector<int> pileup_rho = m_jFEXPileupAndNoiseTool->CalculatePileup();
106
107 //From the DB
108 ATH_CHECK(m_jFEXPileupAndNoiseTool->ApplyPileup());
109
110 //Noise should be always applied
111 m_jFEXPileupAndNoiseTool->ApplyNoise2Jets(true);
112 m_jFEXPileupAndNoiseTool->ApplyNoise2Met(true);
113 //Getting the values
114 m_map_HAD_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_HAD_Et_values();
115 m_map_EM_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_EM_Et_values();
116 m_map_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->GetEt_values();
117 std::vector<int> pileup_ID;
118 std::vector<int> pileup_HAD_jet;
119 std::vector<int> pileup_EM_jet;
120 std::vector<int> pileup_Total_jet;
121 std::vector<int> pileup_HAD_met;
122 std::vector<int> pileup_EM_met;
123 std::vector<int> pileup_Total_met;
124 for (auto const& [key, val] : m_map_HAD_Etvalues_FPGA)
125 {
126 pileup_ID.push_back(key);
127 pileup_HAD_jet.push_back(val[0]);
128 pileup_EM_jet.push_back(m_map_EM_Etvalues_FPGA[key][0]);
129 pileup_Total_jet.push_back(m_map_Etvalues_FPGA[key][0]);
130 pileup_HAD_met.push_back(val[1]);
131 pileup_EM_met.push_back(m_map_EM_Etvalues_FPGA[key][1]);
132 pileup_Total_met.push_back(m_map_Etvalues_FPGA[key][1]);
133 }
134
135 //saving pileup information
136 inputOutputCollection->addValue_pileup("pileup_FPGAid", m_id);
137 inputOutputCollection->addValue_pileup("pileup_jFEXid", m_jfexid);
138 inputOutputCollection->addValue_pileup("pileup_rho_EM", pileup_rho[0]);
139 inputOutputCollection->addValue_pileup("pileup_rho_HAD1", pileup_rho[1]);
140 inputOutputCollection->addValue_pileup("pileup_rho_HAD2", pileup_rho[2]);
141 inputOutputCollection->addValue_pileup("pileup_rho_HAD3", pileup_rho[3]);
142 inputOutputCollection->addValue_pileup("pileup_rho_FCAL", pileup_rho[4]);
143 inputOutputCollection->addValue_pileup("pileup_map_ID" , std::move(pileup_ID));
144 inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_jet" , std::move(pileup_HAD_jet));
145 inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_jet" , std::move(pileup_EM_jet));
146 inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_jet", std::move(pileup_Total_jet));
147 inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_met" , std::move(pileup_HAD_met));
148 inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_met" , std::move(pileup_EM_met));
149 inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_met", std::move(pileup_Total_met));
150 inputOutputCollection->fill_pileup();
151
152 if(m_id==0 || m_id==3) {
153 ATH_CHECK( m_jFEXsumETAlgoTool->safetyTest());
154 ATH_CHECK( m_jFEXsumETAlgoTool->reset());
155 ATH_CHECK( m_jFEXmetAlgoTool->safetyTest());
156 ATH_CHECK( m_jFEXmetAlgoTool->reset());
157
158 m_jFEXsumETAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
159 m_jFEXmetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
160
161 unsigned int bin_pos = thr_jTE.etaBoundary_fw(m_jfex_string[m_jfexid]);
162
163 std::unique_ptr<jFEXTOB> jXE_tob = std::make_unique<jFEXTOB>();
164 uint32_t jXE_tobword = 0;
165
166 std::unique_ptr<jFEXTOB> jTE_tob = std::make_unique<jFEXTOB>();
167 uint32_t jTE_tobword = 0;
168
169
170 int hemisphere = m_id == 0 ? 1 : -1;
171
172 if(m_jfexid > 0 && m_jfexid < 5) {
173
174 //-----------------jFEXsumETAlgo-----------------
175 m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Thin);
176 m_jFEXsumETAlgoTool->buildBarrelSumET();
177
178 //-----------------jFEXmetAlgo-----------------
179 m_jFEXmetAlgoTool->setup(m_jTowersIDs_Thin, hemisphere);
180 m_jFEXmetAlgoTool->buildBarrelmet();
181 }
182 else if(m_jfexid == 0 ) {
183
184 int flipped_jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}};
185 int max_phi_it = FEXAlgoSpaceDefs::jFEX_algoSpace_height-1;
186 int max_eta_it = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-1;
187 for(int mphi = 0; mphi <= max_phi_it; mphi++) {
188 for(int meta = 0; meta <= max_eta_it; meta++) {
189 flipped_jTowersIDs[mphi][meta]=m_jTowersIDs_Wide[mphi][max_eta_it-meta];
190 }
191 }
192 //-----------------jFEXsumETAlgo-----------------
193 m_jFEXsumETAlgoTool->setup(flipped_jTowersIDs);
194 m_jFEXsumETAlgoTool->buildFWDSumET();
195
196 //-----------------jFEXmetAlgo-----------------
197 m_jFEXmetAlgoTool->setup(flipped_jTowersIDs, hemisphere);
198 m_jFEXmetAlgoTool->buildFWDmet();
199 }
200 else if(m_jfexid == 5) {
201
202 //-----------------jFEXsumETAlgo-----------------
203 m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Wide);
204 m_jFEXsumETAlgoTool->buildFWDSumET();
205
206 //-----------------jFEXmetAlgo-----------------
207 m_jFEXmetAlgoTool->setup(m_jTowersIDs_Wide, hemisphere);
208 m_jFEXmetAlgoTool->buildFWDmet();
209 }
210
211 jXE_tobword = m_IjFEXFormTOBsTool->formMetTOB(m_jFEXmetAlgoTool->GetMetXComponent(), m_jFEXmetAlgoTool->GetMetYComponent(),m_jFEXmetAlgoTool->getjXESat(),thr_jXE.resolutionMeV());
212 jXE_tob->initialize(m_id,m_jfexid,jXE_tobword,thr_jXE.resolutionMeV(),0);
213 m_Met_tobwords.push_back(std::move(jXE_tob));
214
215 std::tuple<int,bool> jTElow;
216 std::tuple<int,bool> jTEhigh;
217
218 // NOTE: Foward FPGA in the C-side is already flipped, however we still need to flip the jFEX module 1 and 2
219 if(m_jfexid == 1 || m_jfexid == 2){
220 jTElow = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
221 jTEhigh = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
222 }
223 else{
224 jTElow = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
225 jTEhigh = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
226 }
227
228 jTE_tobword = m_IjFEXFormTOBsTool->formSumETTOB(jTElow,jTEhigh,thr_jTE.resolutionMeV());
229 jTE_tob->initialize(m_id,m_jfexid,jTE_tobword,thr_jTE.resolutionMeV(),0);
230 m_sumET_tobwords.push_back(std::move(jTE_tob));
231 }
232
233 //-----------jFEXSmallRJet & Large R Jet Algo-----------------
234 ATH_MSG_DEBUG("================ Central Algorithms ================");
235
236 int srJet_seedThresholdMeV = thr_jJ.seedThresholdMeV(m_jfex_string[m_jfexid]); //jFEX internal granularity, i.e., 25 MeV/count
237
238
239 //Central region algorithms
240 if(m_jfexid > 0 && m_jfexid < 5) {
241 m_jFEXSmallRJetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
242 if(!m_jFEXLargeRJetAlgoTool.empty()) m_jFEXLargeRJetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
243 m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
244
245 for(int mphi = 8; mphi < FEXAlgoSpaceDefs::jFEX_algoSpace_height-8; mphi++) {
246 for(int meta = 8; meta < FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width-8; meta++) {
247
248 //definition of arrays
249 int TT_seed_ID[3][3]= {{0}};
250 int TT_First_ETring[36]= {0};
251 int First_ETring_it = 0;
252
253 int Jet_SearchWindow[7][7] = {{0}};
254 int Jet_SearchWindowDisplaced[7][7] = {{0}};
255 int largeRCluster_IDs[15][15]= {{0}};
256
257 //filling up array to send them to the algorithms
258 for(int i = -7; i< 8; i++ ) {
259 for(int j = -7; j< 8; j++) {
260
261 if(std::abs(i)<4 && std::abs(j)<4) {
262 Jet_SearchWindow[3 + i][3 + j] = m_jTowersIDs_Thin[mphi + i][meta +j];
263 Jet_SearchWindowDisplaced[3 + i][3 + j] = m_jTowersIDs_Thin[mphi+i+1][meta+j+1];
264 }
265
266 uint deltaR = std::sqrt(std::pow(i,2)+std::pow(j,2));
267
268 if(deltaR<2) {
269 TT_seed_ID[i+1][j+1] = m_jTowersIDs_Thin[mphi +i][meta +j]; // Seed 0.3x0.3 in phi-eta plane
270 }
271 else if(deltaR<4) {
272 TT_First_ETring[First_ETring_it]= m_jTowersIDs_Thin[mphi +i][meta +j]; // First energy ring, will be used as tau ISO
273 ++First_ETring_it;
274
275 }
276 else if(deltaR<8) {
277 largeRCluster_IDs[7 +i][7 +j] = m_jTowersIDs_Thin[mphi + i][meta +j];
278 }
279 }
280 }
281
282 // ******** jJ and jLJ algorithms ********
283 ATH_CHECK( m_jFEXSmallRJetAlgoTool->safetyTest());
284 if(!m_jFEXLargeRJetAlgoTool.empty()) ATH_CHECK( m_jFEXLargeRJetAlgoTool->safetyTest());
285 m_jFEXSmallRJetAlgoTool->setup(Jet_SearchWindow, Jet_SearchWindowDisplaced);
286 if(!m_jFEXLargeRJetAlgoTool.empty()) m_jFEXLargeRJetAlgoTool->setupCluster(largeRCluster_IDs);
287 m_jFEXSmallRJetAlgoTool->buildSeeds();
288
289 bool is_Jet_LM = m_jFEXSmallRJetAlgoTool->isSeedLocalMaxima(srJet_seedThresholdMeV);
290
291 if(is_Jet_LM) {
292
293 //getting the energies
294 int SRj_Et = m_jFEXSmallRJetAlgoTool->getSmallClusterET();
295 int LRj_Et = (m_jFEXLargeRJetAlgoTool.empty()) ? 0 : m_jFEXLargeRJetAlgoTool->getLargeClusterET(SRj_Et,m_jFEXLargeRJetAlgoTool->getRingET());
296 int seed_Et = m_jFEXSmallRJetAlgoTool->getSeedET();
297
298 bool SRj_Sat = m_jFEXSmallRJetAlgoTool->getSRjetSat();
299 bool LRj_Sat = (m_jFEXLargeRJetAlgoTool.empty()) ? false : (SRj_Sat || m_jFEXLargeRJetAlgoTool->getLRjetSat());
300
301 int meta_LM = meta;
302 int mphi_LM = mphi;
303
304
305 //Creating SR TOB
306 uint32_t SRJet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, mphi_LM, meta_LM, SRj_Et, SRj_Sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
307
308 std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
309 jJ_tob->initialize(m_id,m_jfexid,SRJet_tobword,thr_jJ.resolutionMeV(),m_jTowersIDs_Thin[mphi_LM][meta_LM],seed_Et);
310 if ( SRJet_tobword != 0 ){
311 m_SRJet_tobwords.push_back(std::move(jJ_tob));
312 }
313
314 //Creating LR TOB
315 if(!m_jFEXLargeRJetAlgoTool.empty()) {
316 uint32_t LRJet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, mphi_LM, meta_LM, LRj_Et,
317 LRj_Sat, thr_jLJ.resolutionMeV(),
318 thr_jLJ.ptMinToTopoMeV(
319 m_jfex_string[m_jfexid]));
320
321 std::unique_ptr <jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
322 jLJ_tob->initialize(m_id, m_jfexid, LRJet_tobword, thr_jLJ.resolutionMeV(),
323 m_jTowersIDs_Thin[mphi_LM][meta_LM], seed_Et);
324 if (LRJet_tobword != 0) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
325 }
326 }
327 // ******** jTau algorithm ********
328
329 ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
330 m_jFEXtauAlgoTool->setup(TT_seed_ID);
331 bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima();
332
333 // Save TOB is tau is a local maxima
334 if ( is_tau_LocalMax ) {
335
336 //calculates the 1st energy ring
337 m_jFEXtauAlgoTool->setFirstEtRing(TT_First_ETring);
338
339
340 uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
341
342 std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
343 jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),m_jTowersIDs_Thin[mphi][meta]);
344
345 if ( jTau_tobword != 0 ){
346 m_tau_tobwords.push_back(std::move(jTau_tob));
347 }
348 }
349 }
350 }
351 } //end of if statement for checking if in central jfex modules
352
353 //FCAL region algorithm
354 if(m_jfexid ==0 || m_jfexid ==5) {
355
356 //**********Forward Jets***********************
357 ATH_CHECK(m_jFEXForwardJetsAlgoTool->safetyTest());
358 ATH_CHECK(m_jFEXForwardJetsAlgoTool->reset());
359 m_jFEXForwardJetsAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
360 m_jFEXForwardJetsAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid);
361
362 m_FCALJets = m_jFEXForwardJetsAlgoTool->calculateJetETs(srJet_seedThresholdMeV);
363 for(std::unordered_map<int, jFEXForwardJetsInfo>::iterator it = m_FCALJets.begin(); it!=(m_FCALJets.end()); ++it) {
364
365 uint32_t TTID = it->first;
366 jFEXForwardJetsInfo FCALJets = it->second;
367
368 int iphi = FCALJets.getCentreLocalTTPhi();
369 int ieta = FCALJets.getCentreLocalTTEta();
370 m_SRJetET = FCALJets.getSeedET() + FCALJets.getFirstEnergyRingET();
371 m_LRJetET = m_SRJetET + FCALJets.getSecondEnergyRingET();
372 int seedET = FCALJets.getSeedET();
373
374 bool SRJ_sat = FCALJets.getSRjetSat();
375
376 uint32_t SRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, iphi, ieta, m_SRJetET, SRJ_sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
377
378 std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
379 jJ_tob->initialize(m_id,m_jfexid,SRFCAL_Jet_tobword,thr_jJ.resolutionMeV(),TTID,seedET);
380
381 if ( SRFCAL_Jet_tobword != 0 ){
382 m_SRJet_tobwords.push_back(std::move(jJ_tob));
383 }
384
385 if(std::fabs(FCALJets.getCentreTTEta())<2.51 && !m_jFEXLargeRJetAlgoTool.empty()){
386 bool LRJ_sat = FCALJets.getLRjetSat();
387 uint32_t LRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, iphi, ieta, m_LRJetET, LRJ_sat, thr_jLJ.resolutionMeV(),thr_jLJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
388
389 std::unique_ptr<jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
390 jLJ_tob->initialize(m_id,m_jfexid,LRFCAL_Jet_tobword,thr_jLJ.resolutionMeV(),TTID);
391 if ( LRFCAL_Jet_tobword != 0 ) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
392 }
393
394 }
395 //********** Forward Electrons ***********************
396 ATH_CHECK(m_jFEXForwardElecAlgoTool->safetyTest());
397 ATH_CHECK(m_jFEXForwardElecAlgoTool->reset());
398 m_jFEXForwardElecAlgoTool->setFPGAEnergy(m_map_EM_Etvalues_FPGA,m_map_HAD_Etvalues_FPGA);
399 m_jFEXForwardElecAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid,m_id);
400 m_ForwardElecs = m_jFEXForwardElecAlgoTool->calculateEDM();
401
403 SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
404 const TrigConf::L1ThrExtraInfo_jEM & thr_jEM = l1Menu->thrExtraInfo().jEM();
405 const uint jFEXETResolution = thr_jEM.resolutionMeV();//200
406 std::string str_jfexname = m_jfex_string[m_jfexid];
407 uint minEtThreshold = thr_jEM.ptMinToTopoMeV(str_jfexname)/jFEXETResolution;
408 //uint Cval[9] = {1,2,3,20,30,40,20,30,40};//C values for iso, emfr1 and emfr2
409 std::vector<int> Ciso;
410 std::vector<int> Chad1;
411 std::vector<int> Chad2;
412
413 for(std::unordered_map<uint, jFEXForwardElecInfo>::iterator itel = m_ForwardElecs.begin(); itel!=(m_ForwardElecs.end()); ++itel) {
414 uint32_t TTID = itel->first;
415 jFEXForwardElecInfo elCluster = itel->second;
416 uint meta = elCluster.getCoreIeta();//check whether this is the one used by the Trigger conf
417
418 //retrieve jet rejection thresholds from trigger configuration
419 const auto & wp_loose = thr_jEM.isolation(TrigConf::Selection::WP::LOOSE, meta);
420 const auto & wp_medium = thr_jEM.isolation(TrigConf::Selection::WP::MEDIUM, meta);
421 const auto & wp_tight = thr_jEM.isolation(TrigConf::Selection::WP::TIGHT, meta);
422 Ciso.clear();
423 Chad1.clear();
424 Chad2.clear();
425 Ciso.push_back(wp_loose.iso_fw());
426 Ciso.push_back(wp_medium.iso_fw());
427 Ciso.push_back(wp_tight.iso_fw());
428 Chad1.push_back(wp_loose.frac_fw());
429 Chad1.push_back(wp_medium.frac_fw());
430 Chad1.push_back(wp_tight.frac_fw());
431 Chad2.push_back(wp_loose.frac2_fw());
432 Chad2.push_back(wp_medium.frac2_fw());
433 Chad2.push_back(wp_tight.frac2_fw());
434 int Cval[9] = {Ciso[0], Ciso[1], Ciso[2], Chad1[0], Chad1[1], Chad1[2], Chad2[0], Chad2[1], Chad2[2]};
435
436 elCluster.setup(Cval,jFEXETResolution);
437 elCluster.calcFwdElEDM();
438
439 uint etEM = elCluster.getEt();
440 uint32_t FwdEl_tobword = elCluster.getTobWord();
441
442
443 std::vector<uint32_t> FwdEltob_aux{FwdEl_tobword,TTID};
444 if ( FwdEl_tobword != 0 && etEM>minEtThreshold) m_FwdEl_tobwords.push_back(std::move(FwdEltob_aux));
445 }
446
447 //******************************** TAU **********************************************
448 int jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}};
449 int max_meta=17;
450
451 if(m_jfexid ==0) {
452 for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
453 for(int j=28; j<(FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-6); j++) { //lower values of j (j<28) are the Fcals not entering in the jFEX tau range
454 jTowersIDs[i][j-28+8]=m_jTowersIDs_Wide[i][j]; // second argument in m_jTowersIDs is to center the FPGA core area in te same region as the central FPGAs
455 }
456 }
457
458 }
459 else if(m_jfexid ==5 ) {
460
461 // Filling m_jTowersIDs with the m_jTowersIDs_Wide ID values up to 2.5 eta
462 for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
463 for(int j=4; j<17; j++) { //higher values of j (j>16) are the Fcals not entering in the jFEX tau range
464 jTowersIDs[i][j]=m_jTowersIDs_Wide[i][j];
465 }
466 }
467 }
468 ATH_MSG_DEBUG("============================ jFEXtauAlgo ============================");
469 ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
470 m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
471 for(int mphi = 8; mphi < 24; mphi++) {
472 for(int meta = 8; meta < max_meta; meta++) {
473
474 bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima_fwd(jTowersIDs[mphi][meta]);
475
476 // Save TOB is tau is a local maxima
477 if ( is_tau_LocalMax ) {
478
479 uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
480
481 std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
482 jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),jTowersIDs[mphi][meta]);
483 if ( jTau_tobword != 0 ){
484 m_tau_tobwords.push_back(std::move(jTau_tob));
485 }
486 }
487 }
488 }
489 } //end of if statement for checking if in central jfex modules
490 return StatusCode::SUCCESS;
491} //end of the execute function
deltaR
Scalar deltaR(const MatrixBase< Derived > &vec) const
Definition AmgMatrixBasePlugin.h:105
ATH_CHECK
#define ATH_CHECK
Evaluate an expression and check for errors.
Definition AthCheckMacros.h:40
ATH_MSG_ERROR
#define ATH_MSG_ERROR(x)
Definition AthMsgStreamMacros.h:33
ATH_MSG_DEBUG
#define ATH_MSG_DEBUG(x)
Definition AthMsgStreamMacros.h:29
uint
unsigned int uint
Definition LArOFPhaseFill.cxx:20
LVL1::FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width
static constexpr int jFEX_wide_algoSpace_width
Definition FEXAlgoSpaceDefs.h:27
LVL1::FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width
static constexpr int jFEX_thin_algoSpace_width
Definition FEXAlgoSpaceDefs.h:28
LVL1::FEXAlgoSpaceDefs::jFEX_algoSpace_height
static constexpr int jFEX_algoSpace_height
Definition FEXAlgoSpaceDefs.h:29
LVL1::jFEXFPGA::m_FwdEl_tobwords
std::vector< std::vector< uint32_t > > m_FwdEl_tobwords
Definition jFEXFPGA.h:112
LVL1::jFEXFPGA::m_jFEXSmallRJetAlgoTool
ToolHandle< IjFEXSmallRJetAlgo > m_jFEXSmallRJetAlgoTool
Definition jFEXFPGA.h:134
LVL1::jFEXFPGA::m_map_Etvalues_FPGA
std::unordered_map< int, std::vector< int > > m_map_Etvalues_FPGA
Definition jFEXFPGA.h:118
LVL1::jFEXFPGA::m_jfex_string
std::string m_jfex_string[6]
Definition jFEXFPGA.h:145
LVL1::jFEXFPGA::m_map_EM_Etvalues_FPGA
std::unordered_map< int, std::vector< int > > m_map_EM_Etvalues_FPGA
Definition jFEXFPGA.h:120
LVL1::jFEXFPGA::m_jFEXPileupAndNoiseTool
ToolHandle< IjFEXPileupAndNoise > m_jFEXPileupAndNoiseTool
Definition jFEXFPGA.h:141
LVL1::jFEXFPGA::m_jFEXForwardJetsAlgoTool
ToolHandle< IjFEXForwardJetsAlgo > m_jFEXForwardJetsAlgoTool
Definition jFEXFPGA.h:139
LVL1::jFEXFPGA::m_jFEXmetAlgoTool
ToolHandle< IjFEXmetAlgo > m_jFEXmetAlgoTool
Definition jFEXFPGA.h:138
LVL1::jFEXFPGA::m_tau_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_tau_tobwords
Definition jFEXFPGA.h:103
LVL1::jFEXFPGA::m_l1MenuKey
SG::ReadHandleKey< TrigConf::L1Menu > m_l1MenuKey
Definition jFEXFPGA.h:133
LVL1::jFEXFPGA::m_map_HAD_Etvalues_FPGA
std::unordered_map< int, std::vector< int > > m_map_HAD_Etvalues_FPGA
Definition jFEXFPGA.h:119
LVL1::jFEXFPGA::m_jTowersIDs_Thin
int m_jTowersIDs_Thin[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]
Definition jFEXFPGA.h:115
LVL1::jFEXFPGA::m_IjFEXFormTOBsTool
ToolHandle< IjFEXFormTOBs > m_IjFEXFormTOBsTool
Definition jFEXFPGA.h:142
LVL1::jFEXFPGA::m_sumET_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_sumET_tobwords
Definition jFEXFPGA.h:106
LVL1::jFEXFPGA::m_SRJet_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_SRJet_tobwords
Definition jFEXFPGA.h:104
LVL1::jFEXFPGA::m_jFEXsumETAlgoTool
ToolHandle< IjFEXsumETAlgo > m_jFEXsumETAlgoTool
Definition jFEXFPGA.h:137
LVL1::jFEXFPGA::m_jFEXtauAlgoTool
ToolHandle< IjFEXtauAlgo > m_jFEXtauAlgoTool
Definition jFEXFPGA.h:136
LVL1::jFEXFPGA::m_FCALJets
std::unordered_map< int, jFEXForwardJetsInfo > m_FCALJets
Definition jFEXFPGA.h:123
LVL1::jFEXFPGA::m_Met_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_Met_tobwords
Definition jFEXFPGA.h:107
LVL1::jFEXFPGA::m_LRJet_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_LRJet_tobwords
Definition jFEXFPGA.h:105
LVL1::jFEXFPGA::m_ForwardElecs
std::unordered_map< uint, jFEXForwardElecInfo > m_ForwardElecs
Definition jFEXFPGA.h:124
LVL1::jFEXFPGA::m_jTowerContainerKey
SG::ReadHandleKey< LVL1::jTowerContainer > m_jTowerContainerKey
Definition jFEXFPGA.h:132
LVL1::jFEXFPGA::m_jFEXLargeRJetAlgoTool
ToolHandle< IjFEXLargeRJetAlgo > m_jFEXLargeRJetAlgoTool
Definition jFEXFPGA.h:135
LVL1::jFEXFPGA::m_jTowersIDs_Wide
int m_jTowersIDs_Wide[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]
Definition jFEXFPGA.h:114
LVL1::jFEXFPGA::m_jFEXForwardElecAlgoTool
ToolHandle< IjFEXForwardElecAlgo > m_jFEXForwardElecAlgoTool
Definition jFEXFPGA.h:140
TrigConf::L1ThrExtraInfoBase::resolutionMeV
unsigned int resolutionMeV() const
Definition L1ThresholdBase.h:101
TrigConf::L1ThrExtraInfo_jEM::isolation
const WorkingPoints_jEM & isolation(TrigConf::Selection::WP wp, int eta) const
Definition L1ThrExtraInfo.h:217
TrigConf::L1ThrExtraInfo_jEM::ptMinToTopoMeV
unsigned int ptMinToTopoMeV(const std::string &module) const
Definition L1ThrExtraInfo.h:224
TrigConf::L1ThrExtraInfo_jJ::ptMinToTopoMeV
unsigned int ptMinToTopoMeV(const std::string &module) const
Definition L1ThrExtraInfo.h:400
TrigConf::L1ThrExtraInfo_jJ::seedThresholdMeV
unsigned int seedThresholdMeV(const std::string &module) const
Definition L1ThrExtraInfo.h:416
TrigConf::L1ThrExtraInfo_jLJ::ptMinToTopoMeV
unsigned int ptMinToTopoMeV(const std::string &module) const
Definition L1ThrExtraInfo.h:445
TrigConf::L1ThrExtraInfo_jTAU::ptMinToTopoMeV
unsigned int ptMinToTopoMeV(const std::string &module) const
Definition L1ThrExtraInfo.h:322
TrigConf::L1ThrExtraInfo_jTE::etaBoundary_fw
unsigned int etaBoundary_fw(const std::string &module) const
Definition L1ThrExtraInfo.h:562
xAOD::uint32_t
setEventNumber uint32_t
Definition EventInfo_v1.cxx:127

◆ extraDeps_update_handler()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::extraDeps_update_handler ( Gaudi::Details::PropertyBase & ExtraDeps)
protectedinherited

Add StoreName to extra input/output deps as needed.

use the logic of the VarHandleKey to parse the DataObjID keys supplied via the ExtraInputs and ExtraOuputs Properties to add the StoreName if it's not explicitly given

◆ getFwdElTOBs()

std::vector< std::vector< uint32_t > > LVL1::jFEXFPGA::getFwdElTOBs ( )
overridevirtual

sorted Electron tobs

Implements LVL1::IjFEXFPGA.

Definition at line 561 of file jFEXFPGA.cxx.

562 {
563 auto tobsSort = m_FwdEl_tobwords;
564
565 ATH_MSG_DEBUG("number of Forward Elec tobs: " << tobsSort.size() << " in FPGA: " << m_id<< " before truncation");
566 //sort tobs by their et
567 std::sort (tobsSort.begin(), tobsSort.end(), etFwdElSort);
568
569 return tobsSort;
570 }
LVL1::jFEXFPGA::etFwdElSort
static bool etFwdElSort(const std::vector< uint32_t > &i, const std::vector< uint32_t > &j)
Definition jFEXFPGA.h:101
std::sort
void sort(typename DataModel_detail::iterator< DVL > beg, typename DataModel_detail::iterator< DVL > end)
Specialization of sort for DataVector/List.
Definition DVL_algorithms.h:554

◆ getLargeRJetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getLargeRJetTOBs ( )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 547 of file jFEXFPGA.cxx.

548{
549 std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
550
551 // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
552 for(auto &j : m_LRJet_tobwords) {
553 tobsSort.push_back(std::move(j));
554 }
555 std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jLJ_etBit, 0x1fff));
556
557 return tobsSort;
558}
LVL1::FEXAlgoSpaceDefs::jLJ_etBit
static constexpr int jLJ_etBit
Definition FEXAlgoSpaceDefs.h:129
LVL1::jFEXFPGA::TOBetSort
static bool TOBetSort(const TOBObjectClass &i, const TOBObjectClass &j, uint bits, uint mask)
Internal data.
Definition jFEXFPGA.h:97

◆ getMetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getMetTOBs ( )
overridevirtual

Form a tob word out of the potential candidate MET tob.

Implements LVL1::IjFEXFPGA.

Definition at line 600 of file jFEXFPGA.cxx.

600 {
601
602 std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
603
604 // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
605 for(auto &j : m_Met_tobwords) {
606 tobsSort.push_back(std::move(j));
607 }
608
609 return tobsSort;
610}

◆ getSmallRJetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getSmallRJetTOBs ( )
overridevirtual

Form a tob word out of the potential candidate SmallRJet tob.

Implements LVL1::IjFEXFPGA.

Definition at line 534 of file jFEXFPGA.cxx.

535{
536 std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
537
538 // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
539 for(auto &j : m_SRJet_tobwords) {
540 tobsSort.push_back(std::move(j));
541 }
542 std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jJ_etBit, 0x7ff));
543
544 return tobsSort;
545}
LVL1::FEXAlgoSpaceDefs::jJ_etBit
static constexpr int jJ_etBit
Definition FEXAlgoSpaceDefs.h:121

◆ getSumEtTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getSumEtTOBs ( )
overridevirtual

Form a tob word out of the potential candidate SumET tob.

Implements LVL1::IjFEXFPGA.

Definition at line 586 of file jFEXFPGA.cxx.

586 {
587
588 std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
589
590 // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
591 for(auto &j : m_sumET_tobwords) {
592 tobsSort.push_back(std::move(j));
593 }
594
595 return tobsSort;
596}

◆ getTauTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getTauTOBs ( )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 573 of file jFEXFPGA.cxx.

573 {
574
575 std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
576
577 // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
578 for(auto &j : m_tau_tobwords) {
579 tobsSort.push_back(std::move(j));
580 }
581 std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jTau_etBit, 0x7ff));
582
583 return tobsSort;
584}
LVL1::FEXAlgoSpaceDefs::jTau_etBit
static constexpr int jTau_etBit
Definition FEXAlgoSpaceDefs.h:102

◆ getTTowerET()

int LVL1::jFEXFPGA::getTTowerET ( unsigned int TTID)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 638 of file jFEXFPGA.cxx.

638 {
639
640 return getTTowerET_EM(TTID)+getTTowerET_HAD(TTID);
641}
LVL1::jFEXFPGA::getTTowerET_EM
int getTTowerET_EM(unsigned int TTID) override
Definition jFEXFPGA.cxx:614
LVL1::jFEXFPGA::getTTowerET_HAD
int getTTowerET_HAD(unsigned int TTID) override
Definition jFEXFPGA.cxx:626

◆ getTTowerET_EM()

int LVL1::jFEXFPGA::getTTowerET_EM ( unsigned int TTID)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 614 of file jFEXFPGA.cxx.

614 {
615
616 if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
617 return m_map_EM_Etvalues_FPGA[TTID][0];
618 }
619
620 ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_EM, TTower ID not found in map: " << TTID );
621 return -99999;
622}

◆ getTTowerET_forMET()

int LVL1::jFEXFPGA::getTTowerET_forMET ( unsigned int TTID)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 645 of file jFEXFPGA.cxx.

645 {
646
647 int tmp_EM = 0;
648 if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
649 tmp_EM = m_map_EM_Etvalues_FPGA[TTID][1];
650 }
651 else{
652 ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (EM energy), TTower ID not found in map: " << TTID );
653 tmp_EM = -99999;
654 }
655
656
657 int tmp_HAD = 0;
658 if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
659 tmp_HAD = m_map_HAD_Etvalues_FPGA[TTID][1];
660 }
661 else{
662 ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (HAD energy), TTower ID not found in map: " << TTID );
663 tmp_HAD = -99999;
664 }
665
666
667 return tmp_EM + tmp_HAD;
668}

◆ getTTowerET_HAD()

int LVL1::jFEXFPGA::getTTowerET_HAD ( unsigned int TTID)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 626 of file jFEXFPGA.cxx.

626 {
627
628 if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
629 return m_map_HAD_Etvalues_FPGA[TTID][0];
630 }
631
632 ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_HAD, TTower ID not found in map: " << TTID );
633 return -99999;
634}

◆ getTTowerET_SG()

int LVL1::jFEXFPGA::getTTowerET_SG ( unsigned int TTID)
private

Definition at line 672 of file jFEXFPGA.cxx.

672 {
673
674 if(TTID == 0){
675 return -999;
676 }
677 SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey);
678 const LVL1::jTower * tmpTower = jTowerContainer->findTower(TTID);
679 return tmpTower->getTotalET();
680}
LVL1::jTower::getTotalET
int getTotalET() const
Get ET sum of all cells in the jTower in MeV.
Definition jTower.cxx:198

◆ ID()

virtual int LVL1::jFEXFPGA::ID ( )
inlineoverridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 68 of file jFEXFPGA.h.

68{return m_id;}

◆ init()

StatusCode LVL1::jFEXFPGA::init ( int id,
int efexid )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 55 of file jFEXFPGA.cxx.

55 {
56 m_id = id;
57 m_jfexid = jfexid;
58
59 return StatusCode::SUCCESS;
60
61}
Base_Fragment.id
id
Definition Sherpa_i/share/common/Base_Fragment.py:59

◆ initialize()

StatusCode LVL1::jFEXFPGA::initialize ( )
overridevirtual

standard Athena-Algorithm method

Definition at line 47 of file jFEXFPGA.cxx.

47 {
48
49 ATH_CHECK(m_jTowerContainerKey.initialize());
50 ATH_CHECK(m_l1MenuKey.initialize());
51 ATH_CHECK(m_jFEXtauAlgoTool.retrieve());
52 return StatusCode::SUCCESS;
53}

◆ inputHandles()

virtual std::vector< Gaudi::DataHandle * > AthCommonDataStore< AthCommonMsg< AlgTool > >::inputHandles ( ) const
overridevirtualinherited

Return this algorithm's input handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ interfaceID()

const InterfaceID & LVL1::IjFEXFPGA::interfaceID ( )
inlinestaticinherited

Definition at line 70 of file IjFEXFPGA.h.

71 {
72 return IID_IjFEXFPGA;
73 }
LVL1::IID_IjFEXFPGA
static const InterfaceID IID_IjFEXFPGA("LVL1::IjFEXFPGA", 1, 0)

◆ msg()

MsgStream & AthCommonMsg< AlgTool >::msg ( ) const
inlineinherited

Definition at line 24 of file AthCommonMsg.h.

24 {
25 return this->msgStream();
26 }

◆ msgLvl()

bool AthCommonMsg< AlgTool >::msgLvl ( const MSG::Level lvl) const
inlineinherited

Definition at line 30 of file AthCommonMsg.h.

30 {
31 return this->msgLevel(lvl);
32 }

◆ outputHandles()

virtual std::vector< Gaudi::DataHandle * > AthCommonDataStore< AthCommonMsg< AlgTool > >::outputHandles ( ) const
overridevirtualinherited

Return this algorithm's output handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ renounce()

std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > AthCommonDataStore< AthCommonMsg< AlgTool > >::renounce ( T & h)
inlineprotectedinherited

Definition at line 380 of file AthCommonDataStore.h.

381 {
382 h.renounce();
383 PBASE::renounce (h);
384 }
AthCommonDataStore::renounce
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > renounce(T &h)
Definition AthCommonDataStore.h:380

◆ renounceArray()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::renounceArray ( SG::VarHandleKeyArray & handlesArray)
inlineprotectedinherited

remove all handles from I/O resolution

Definition at line 364 of file AthCommonDataStore.h.

364 {
365 handlesArray.renounce();
366 }

◆ reset()

void LVL1::jFEXFPGA::reset ( )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 63 of file jFEXFPGA.cxx.

63 {
64
65 m_id = -1;
66 m_jfexid = -1;
67 m_tau_tobwords.clear();
68 m_SRJet_tobwords.clear();
69 m_LRJet_tobwords.clear();
70 m_sumET_tobwords.clear();
71 m_Met_tobwords.clear();
72 m_map_Etvalues_FPGA.clear();
73 m_map_EM_Etvalues_FPGA.clear();
74 m_map_HAD_Etvalues_FPGA.clear();
75 m_FwdEl_tobwords.clear();
76}

◆ SetTowersAndCells_SG() [1/2]

void LVL1::jFEXFPGA::SetTowersAndCells_SG ( int tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 511 of file jFEXFPGA.cxx.

511 {
512
513 const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
514 const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
515
516 std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Thin[0][0]);
517
518 //this prints out the jTower IDs that each FPGA is responsible for
519 ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
520
521 for (int thisRow=rows-1; thisRow>=0; thisRow--) {
522 for (int thisCol=0; thisCol<cols; thisCol++) {
523 if(thisCol != cols-1) {
524 ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " ");
525 }
526 else {
527 ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " |");
528 }
529 }
530 }
531
532}

◆ SetTowersAndCells_SG() [2/2]

void LVL1::jFEXFPGA::SetTowersAndCells_SG ( int tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 493 of file jFEXFPGA.cxx.

493 {
494
495 const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
496 const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
497
498 std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Wide[0][0]);
499
500 ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
501
502 for (int thisRow=rows-1; thisRow>=0; thisRow--){
503 for (int thisCol=0; thisCol<cols; thisCol++){
504 if(thisCol != cols-1){ ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " "); }
505 else { ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " |"); }
506 }
507 }
508
509}

◆ sysInitialize()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysInitialize ( )
overridevirtualinherited

Perform system initialization for an algorithm.

We override this to declare all the elements of handle key arrays at the end of initialization. See comments on updateVHKA.

Reimplemented in asg::AsgMetadataTool, AthCheckedComponent< AthAlgTool >, AthCheckedComponent<::AthAlgTool >, and DerivationFramework::CfAthAlgTool.

◆ sysStart()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysStart ( )
overridevirtualinherited

Handle START transition.

We override this in order to make sure that conditions handle keys can cache a pointer to the conditions container.

◆ TOBetSort()

template<class TOBObjectClass>
bool LVL1::jFEXFPGA::TOBetSort ( const TOBObjectClass & i,
const TOBObjectClass & j,
uint bits,
uint mask )
inlinestaticprivate

Internal data.

Definition at line 97 of file jFEXFPGA.h.

97 {
98 return (((i->getWord() >> bits ) & mask)>((j->getWord() >> bits ) & mask));
99 }

◆ updateVHKA()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::updateVHKA ( Gaudi::Details::PropertyBase & )
inlineinherited

Definition at line 308 of file AthCommonDataStore.h.

308 {
309 // debug() << "updateVHKA for property " << p.name() << " " << p.toString()
310 // << " size: " << m_vhka.size() << endmsg;
311 for (auto &a : m_vhka) {
312 std::vector<SG::VarHandleKey*> keys = a->keys();
313 for (auto k : keys) {
314 k->setOwner(this);
315 }
316 }
317 }
AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
std::vector< SG::VarHandleKeyArray * > m_vhka
Definition AthCommonDataStore.h:398

Member Data Documentation

◆ m_detStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_detStore
privateinherited

Pointer to StoreGate (detector store by default)

Definition at line 393 of file AthCommonDataStore.h.

◆ m_evtStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_evtStore
privateinherited

Pointer to StoreGate (event store by default)

Definition at line 390 of file AthCommonDataStore.h.

◆ m_FCALJets

std::unordered_map<int, jFEXForwardJetsInfo> LVL1::jFEXFPGA::m_FCALJets
private

Definition at line 123 of file jFEXFPGA.h.

◆ m_ForwardElecs

std::unordered_map<uint, jFEXForwardElecInfo> LVL1::jFEXFPGA::m_ForwardElecs
private

Definition at line 124 of file jFEXFPGA.h.

◆ m_FwdEl_tobwords

std::vector<std::vector<uint32_t> > LVL1::jFEXFPGA::m_FwdEl_tobwords
private

Definition at line 112 of file jFEXFPGA.h.

◆ m_id

int LVL1::jFEXFPGA::m_id {}
private

Definition at line 109 of file jFEXFPGA.h.

109{};

◆ m_IjFEXFormTOBsTool

ToolHandle<IjFEXFormTOBs> LVL1::jFEXFPGA::m_IjFEXFormTOBsTool {this, "IjFEXFormTOBsTool", "LVL1::jFEXFormTOBs", "Tool that forms TOB words"}
private

Definition at line 142 of file jFEXFPGA.h.

142{this, "IjFEXFormTOBsTool", "LVL1::jFEXFormTOBs", "Tool that forms TOB words"};

◆ m_jfex_string

std::string LVL1::jFEXFPGA::m_jfex_string[6] = {"1C","2C","3C","3A","2A","1A"}
private

Definition at line 145 of file jFEXFPGA.h.

145{"1C","2C","3C","3A","2A","1A"};

◆ m_jFEXForwardElecAlgoTool

ToolHandle<IjFEXForwardElecAlgo> LVL1::jFEXFPGA::m_jFEXForwardElecAlgoTool {this, "jFEXForwardElecAlgoTool" , "LVL1::jFEXForwardElecAlgo" , "Tool that runs the jFEX FCAL Electrons algorithm"}
private

Definition at line 140 of file jFEXFPGA.h.

140{this, "jFEXForwardElecAlgoTool" , "LVL1::jFEXForwardElecAlgo" , "Tool that runs the jFEX FCAL Electrons algorithm"};

◆ m_jFEXForwardJetsAlgoTool

ToolHandle<IjFEXForwardJetsAlgo> LVL1::jFEXFPGA::m_jFEXForwardJetsAlgoTool {this, "jFEXForwardJetsAlgoTool" , "LVL1::jFEXForwardJetsAlgo" , "Tool that runs the jFEX FCAL Jets algorithm"}
private

Definition at line 139 of file jFEXFPGA.h.

139{this, "jFEXForwardJetsAlgoTool" , "LVL1::jFEXForwardJetsAlgo" , "Tool that runs the jFEX FCAL Jets algorithm"};

◆ m_jfexid

int LVL1::jFEXFPGA::m_jfexid {}
private

Definition at line 110 of file jFEXFPGA.h.

110{};

◆ m_jFEXLargeRJetAlgoTool

ToolHandle<IjFEXLargeRJetAlgo> LVL1::jFEXFPGA::m_jFEXLargeRJetAlgoTool {this, "jFEXLargeRJetAlgoTool", "LVL1::jFEXLargeRJetAlgo", "Tool that runs the jFEX Large R Jet algorithm"}
private

Definition at line 135 of file jFEXFPGA.h.

135{this, "jFEXLargeRJetAlgoTool", "LVL1::jFEXLargeRJetAlgo", "Tool that runs the jFEX Large R Jet algorithm"};

◆ m_jFEXmetAlgoTool

ToolHandle<IjFEXmetAlgo> LVL1::jFEXFPGA::m_jFEXmetAlgoTool {this, "jFEXmetAlgoTool" , "LVL1::jFEXmetAlgo" , "Tool that runs the jFEX met algorithm"}
private

Definition at line 138 of file jFEXFPGA.h.

138{this, "jFEXmetAlgoTool" , "LVL1::jFEXmetAlgo" , "Tool that runs the jFEX met algorithm"};

◆ m_jFEXPileupAndNoiseTool

ToolHandle<IjFEXPileupAndNoise> LVL1::jFEXFPGA::m_jFEXPileupAndNoiseTool {this, "jFEXPileupAndNoiseTool", "LVL1::jFEXPileupAndNoise", "Tool that applies Pileup and Noise"}
private

Definition at line 141 of file jFEXFPGA.h.

141{this, "jFEXPileupAndNoiseTool", "LVL1::jFEXPileupAndNoise", "Tool that applies Pileup and Noise"};

◆ m_jFEXSmallRJetAlgoTool

ToolHandle<IjFEXSmallRJetAlgo> LVL1::jFEXFPGA::m_jFEXSmallRJetAlgoTool {this, "jFEXSmallRJetAlgoTool", "LVL1::jFEXSmallRJetAlgo", "Tool that runs the jFEX Small R Jet algorithm"}
private

Definition at line 134 of file jFEXFPGA.h.

134{this, "jFEXSmallRJetAlgoTool", "LVL1::jFEXSmallRJetAlgo", "Tool that runs the jFEX Small R Jet algorithm"};

◆ m_jFEXsumETAlgoTool

ToolHandle<IjFEXsumETAlgo> LVL1::jFEXFPGA::m_jFEXsumETAlgoTool {this, "jFEXsumETAlgoTool" , "LVL1::jFEXsumETAlgo" , "Tool that runs the jFEX sumET algorithm"}
private

Definition at line 137 of file jFEXFPGA.h.

137{this, "jFEXsumETAlgoTool" , "LVL1::jFEXsumETAlgo" , "Tool that runs the jFEX sumET algorithm"};

◆ m_jFEXtauAlgoTool

ToolHandle<IjFEXtauAlgo> LVL1::jFEXFPGA::m_jFEXtauAlgoTool {this, "jFEXtauAlgoTool" , "LVL1::jFEXtauAlgo" , "Tool that runs the jFEX tau algorithm"}
private

Definition at line 136 of file jFEXFPGA.h.

136{this, "jFEXtauAlgoTool" , "LVL1::jFEXtauAlgo" , "Tool that runs the jFEX tau algorithm"};

◆ m_jTowerContainerKey

SG::ReadHandleKey<LVL1::jTowerContainer> LVL1::jFEXFPGA::m_jTowerContainerKey {this, "MyETowers", "jTowerContainer", "Input container for jTowers"}
private

Definition at line 132 of file jFEXFPGA.h.

132{this, "MyETowers", "jTowerContainer", "Input container for jTowers"};

◆ m_jTowersColl

std::unordered_map<int,jTower> LVL1::jFEXFPGA::m_jTowersColl
private

Definition at line 117 of file jFEXFPGA.h.

◆ m_jTowersIDs_Thin

int LVL1::jFEXFPGA::m_jTowersIDs_Thin[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}}
private

Definition at line 115 of file jFEXFPGA.h.

115{{0}};

◆ m_jTowersIDs_Wide

int LVL1::jFEXFPGA::m_jTowersIDs_Wide[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}}
private

Definition at line 114 of file jFEXFPGA.h.

114{{0}};

◆ m_l1MenuKey

SG::ReadHandleKey<TrigConf::L1Menu> LVL1::jFEXFPGA::m_l1MenuKey {this, "L1TriggerMenu", "DetectorStore+L1TriggerMenu","Name of the L1Menu object to read configuration from"}
private

Definition at line 133 of file jFEXFPGA.h.

133{this, "L1TriggerMenu", "DetectorStore+L1TriggerMenu","Name of the L1Menu object to read configuration from"};

◆ m_LRJet_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_LRJet_tobwords
private

Definition at line 105 of file jFEXFPGA.h.

◆ m_LRJetET

int LVL1::jFEXFPGA::m_LRJetET {}
private

Definition at line 127 of file jFEXFPGA.h.

127{};

◆ m_map_EM_Etvalues_FPGA

std::unordered_map<int,std::vector<int> > LVL1::jFEXFPGA::m_map_EM_Etvalues_FPGA
private

Definition at line 120 of file jFEXFPGA.h.

◆ m_map_Etvalues_FPGA

std::unordered_map<int,std::vector<int> > LVL1::jFEXFPGA::m_map_Etvalues_FPGA
private

Definition at line 118 of file jFEXFPGA.h.

◆ m_map_HAD_Etvalues_FPGA

std::unordered_map<int,std::vector<int> > LVL1::jFEXFPGA::m_map_HAD_Etvalues_FPGA
private

Definition at line 119 of file jFEXFPGA.h.

◆ m_Met_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_Met_tobwords
private

Definition at line 107 of file jFEXFPGA.h.

◆ m_SRJet_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_SRJet_tobwords
private

Definition at line 104 of file jFEXFPGA.h.

◆ m_SRJetET

int LVL1::jFEXFPGA::m_SRJetET {}
private

Definition at line 126 of file jFEXFPGA.h.

126{};

◆ m_sumET_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_sumET_tobwords
private

Definition at line 106 of file jFEXFPGA.h.

◆ m_tau_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_tau_tobwords
private

Definition at line 103 of file jFEXFPGA.h.

◆ m_varHandleArraysDeclared

bool AthCommonDataStore< AthCommonMsg< AlgTool > >::m_varHandleArraysDeclared
privateinherited

Definition at line 399 of file AthCommonDataStore.h.

◆ m_vhka

std::vector<SG::VarHandleKeyArray*> AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
privateinherited

Definition at line 398 of file AthCommonDataStore.h.

The documentation for this class was generated from the following files:
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