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LVL1::jFEXFPGA Class Reference

The jFEXFPGA class defines the structure of a single jFEX FPGA Its purpose is: More...

#include <jFEXFPGA.h>

Inheritance diagram for LVL1::jFEXFPGA:
Collaboration diagram for LVL1::jFEXFPGA:

Public Member Functions

 jFEXFPGA (const std::string &type, const std::string &name, const IInterface *parent)
 Constructors. More...
 
virtual StatusCode initialize () override
 standard Athena-Algorithm method More...
 
virtual ~jFEXFPGA ()
 Destructor. More...
 
virtual StatusCode init (int id, int efexid) override
 
virtual StatusCode execute (jFEXOutputCollection *inputOutputCollection, const std::pair< unsigned int, const std::vector< int > & > &jetCalibrationParameters) override
 
virtual void reset () override
 
virtual int ID () override
 
virtual void SetTowersAndCells_SG (int[][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]) override
 
virtual void SetTowersAndCells_SG (int[][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]) override
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getSmallRJetTOBs () override
 Form a tob word out of the potential candidate SmallRJet tob. More...
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getLargeRJetTOBs () override
 
virtual std::vector< std::vector< uint32_t > > getFwdElTOBs () override
 sorted Electron tobs More...
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getTauTOBs () override
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getSumEtTOBs () override
 Form a tob word out of the potential candidate SumET tob. More...
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getMetTOBs () override
 Form a tob word out of the potential candidate MET tob. More...
 
int getTTowerET_EM (unsigned int TTID) override
 
int getTTowerET_HAD (unsigned int TTID) override
 
int getTTowerET (unsigned int TTID) override
 
int getTTowerET_forMET (unsigned int TTID) override
 
ServiceHandle< StoreGateSvc > & evtStore ()
 The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc. More...
 
const ServiceHandle< StoreGateSvc > & evtStore () const
 The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc. More...
 
const ServiceHandle< StoreGateSvc > & detStore () const
 The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc. More...
 
virtual StatusCode sysInitialize () override
 Perform system initialization for an algorithm. More...
 
virtual StatusCode sysStart () override
 Handle START transition. More...
 
virtual std::vector< Gaudi::DataHandle * > inputHandles () const override
 Return this algorithm's input handles. More...
 
virtual std::vector< Gaudi::DataHandle * > outputHandles () const override
 Return this algorithm's output handles. More...
 
Gaudi::Details::PropertyBase & declareProperty (Gaudi::Property< T > &t)
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, SG::VarHandleKey &hndl, const std::string &doc, const SG::VarHandleKeyType &)
 Declare a new Gaudi property. More...
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, SG::VarHandleBase &hndl, const std::string &doc, const SG::VarHandleType &)
 Declare a new Gaudi property. More...
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, SG::VarHandleKeyArray &hndArr, const std::string &doc, const SG::VarHandleKeyArrayType &)
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, T &property, const std::string &doc, const SG::NotHandleType &)
 Declare a new Gaudi property. More...
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, T &property, const std::string &doc="none")
 Declare a new Gaudi property. More...
 
void updateVHKA (Gaudi::Details::PropertyBase &)
 
MsgStream & msg () const
 
MsgStream & msg (const MSG::Level lvl) const
 
bool msgLvl (const MSG::Level lvl) const
 

Static Public Member Functions

static const InterfaceID & interfaceID ()
 

Protected Member Functions

void renounceArray (SG::VarHandleKeyArray &handlesArray)
 remove all handles from I/O resolution More...
 
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > renounce (T &h)
 
void extraDeps_update_handler (Gaudi::Details::PropertyBase &ExtraDeps)
 Add StoreName to extra input/output deps as needed. More...
 

Private Types

typedef ServiceHandle< StoreGateSvc > StoreGateSvc_t
 

Private Member Functions

int getTTowerET_SG (unsigned int TTID)
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T > &hndl, const SG::VarHandleKeyType &)
 specialization for handling Gaudi::Property<SG::VarHandleKey> More...
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T > &hndl, const SG::VarHandleKeyArrayType &)
 specialization for handling Gaudi::Property<SG::VarHandleKeyArray> More...
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T > &hndl, const SG::VarHandleType &)
 specialization for handling Gaudi::Property<SG::VarHandleBase> More...
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T > &t, const SG::NotHandleType &)
 specialization for handling everything that's not a Gaudi::Property<SG::VarHandleKey> or a <SG::VarHandleKeyArray> More...
 

Static Private Member Functions

template<class TOBObjectClass >
static bool TOBetSort (const TOBObjectClass &i, const TOBObjectClass &j, uint bits, uint mask)
 Internal data. More...
 
static bool etFwdElSort (const std::vector< uint32_t > &i, const std::vector< uint32_t > &j)
 

Private Attributes

std::vector< std::unique_ptr< jFEXTOB > > m_tau_tobwords
 
std::vector< std::unique_ptr< jFEXTOB > > m_SRJet_tobwords
 
std::vector< std::unique_ptr< jFEXTOB > > m_LRJet_tobwords
 
std::vector< std::unique_ptr< jFEXTOB > > m_sumET_tobwords
 
std::vector< std::unique_ptr< jFEXTOB > > m_Met_tobwords
 
int m_id
 
int m_jfexid
 
std::vector< std::vector< uint32_t > > m_FwdEl_tobwords
 
int m_jTowersIDs_Wide [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}}
 
int m_jTowersIDs_Thin [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}}
 
std::unordered_map< int, jTower > m_jTowersColl
 
std::unordered_map< int, std::vector< int > > m_map_Etvalues_FPGA
 
std::unordered_map< int, std::vector< int > > m_map_HAD_Etvalues_FPGA
 
std::unordered_map< int, std::vector< int > > m_map_EM_Etvalues_FPGA
 
std::unordered_map< int, jFEXForwardJetsInfo > m_FCALJets
 
std::unordered_map< uint, jFEXForwardElecInfo > m_ForwardElecs
 
int m_SRJetET
 
int m_LRJetET
 
CaloCellContainer m_sCellsCollection
 
SG::ReadHandleKey< LVL1::jTowerContainer > m_jTowerContainerKey {this, "MyETowers", "jTowerContainer", "Input container for jTowers"}
 
SG::ReadHandleKey< TrigConf::L1Menu > m_l1MenuKey {this, "L1TriggerMenu", "DetectorStore+L1TriggerMenu","Name of the L1Menu object to read configuration from"}
 
ToolHandle< IjFEXSmallRJetAlgo > m_jFEXSmallRJetAlgoTool {this, "jFEXSmallRJetAlgoTool", "LVL1::jFEXSmallRJetAlgo", "Tool that runs the jFEX Small R Jet algorithm"}
 
ToolHandle< IjFEXLargeRJetAlgo > m_jFEXLargeRJetAlgoTool {this, "jFEXLargeRJetAlgoTool", "LVL1::jFEXLargeRJetAlgo", "Tool that runs the jFEX Large R Jet algorithm"}
 
ToolHandle< IjFEXtauAlgo > m_jFEXtauAlgoTool {this, "jFEXtauAlgoTool" , "LVL1::jFEXtauAlgo" , "Tool that runs the jFEX tau algorithm"}
 
ToolHandle< IjFEXsumETAlgo > m_jFEXsumETAlgoTool {this, "jFEXsumETAlgoTool" , "LVL1::jFEXsumETAlgo" , "Tool that runs the jFEX sumET algorithm"}
 
ToolHandle< IjFEXmetAlgo > m_jFEXmetAlgoTool {this, "jFEXmetAlgoTool" , "LVL1::jFEXmetAlgo" , "Tool that runs the jFEX met algorithm"}
 
ToolHandle< IjFEXForwardJetsAlgo > m_jFEXForwardJetsAlgoTool {this, "jFEXForwardJetsAlgoTool" , "LVL1::jFEXForwardJetsAlgo" , "Tool that runs the jFEX FCAL Jets algorithm"}
 
ToolHandle< IjFEXForwardElecAlgo > m_jFEXForwardElecAlgoTool {this, "jFEXForwardElecAlgoTool" , "LVL1::jFEXForwardElecAlgo" , "Tool that runs the jFEX FCAL Electrons algorithm"}
 
ToolHandle< IjFEXPileupAndNoise > m_jFEXPileupAndNoiseTool {this, "jFEXPileupAndNoiseTool", "LVL1::jFEXPileupAndNoise", "Tool that applies Pileup and Noise"}
 
ToolHandle< IjFEXFormTOBs > m_IjFEXFormTOBsTool {this, "IjFEXFormTOBsTool", "LVL1::jFEXFormTOBs", "Tool that forms TOB words"}
 
std::string m_jfex_string [6] = {"1C","2C","3C","3A","2A","1A"}
 
StoreGateSvc_t m_evtStore
 Pointer to StoreGate (event store by default) More...
 
StoreGateSvc_t m_detStore
 Pointer to StoreGate (detector store by default) More...
 
std::vector< SG::VarHandleKeyArray * > m_vhka
 
bool m_varHandleArraysDeclared
 

Detailed Description

The jFEXFPGA class defines the structure of a single jFEX FPGA Its purpose is:

Definition at line 57 of file jFEXFPGA.h.

Member Typedef Documentation

◆ StoreGateSvc_t

typedef ServiceHandle<StoreGateSvc> AthCommonDataStore< AthCommonMsg< AlgTool > >::StoreGateSvc_t
privateinherited

Definition at line 388 of file AthCommonDataStore.h.

Constructor & Destructor Documentation

◆ jFEXFPGA()

LVL1::jFEXFPGA::jFEXFPGA ( const std::string &  type,
const std::string &  name,
const IInterface *  parent 
)

Constructors.

Definition at line 49 of file jFEXFPGA.cxx.

49  : AthAlgTool(type,name,parent) {
50  declareInterface<IjFEXFPGA>(this);
51 }

◆ ~jFEXFPGA()

LVL1::jFEXFPGA::~jFEXFPGA ( )
virtual

Destructor.

Definition at line 54 of file jFEXFPGA.cxx.

55 {
56 }

Member Function Documentation

◆ declareGaudiProperty() [1/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T > &  hndl,
const SG::VarHandleKeyArrayType &   
)
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKeyArray>

Definition at line 170 of file AthCommonDataStore.h.

172  {
173  return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
174  hndl.value(),
175  hndl.documentation());
176 
177  }

◆ declareGaudiProperty() [2/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T > &  hndl,
const SG::VarHandleKeyType &   
)
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKey>

Definition at line 156 of file AthCommonDataStore.h.

158  {
159  return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
160  hndl.value(),
161  hndl.documentation());
162 
163  }

◆ declareGaudiProperty() [3/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T > &  hndl,
const SG::VarHandleType &   
)
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleBase>

Definition at line 184 of file AthCommonDataStore.h.

186  {
187  return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
188  hndl.value(),
189  hndl.documentation());
190  }

◆ declareGaudiProperty() [4/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T > &  t,
const SG::NotHandleType &   
)
inlineprivateinherited

specialization for handling everything that's not a Gaudi::Property<SG::VarHandleKey> or a <SG::VarHandleKeyArray>

Definition at line 199 of file AthCommonDataStore.h.

200  {
201  return PBASE::declareProperty(t);
202  }

◆ declareProperty() [1/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
SG::VarHandleBase &  hndl,
const std::string &  doc,
const SG::VarHandleType &   
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
hndlObject holding the property value.
docDocumentation string for the property.

This is the version for types that derive from SG::VarHandleBase. The property value object is put on the input and output lists as appropriate; then we forward to the base class.

Definition at line 245 of file AthCommonDataStore.h.

249  {
250  this->declare(hndl.vhKey());
251  hndl.vhKey().setOwner(this);
252 
253  return PBASE::declareProperty(name,hndl,doc);
254  }

◆ declareProperty() [2/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
SG::VarHandleKey &  hndl,
const std::string &  doc,
const SG::VarHandleKeyType &   
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
hndlObject holding the property value.
docDocumentation string for the property.

This is the version for types that derive from SG::VarHandleKey. The property value object is put on the input and output lists as appropriate; then we forward to the base class.

Definition at line 221 of file AthCommonDataStore.h.

225  {
226  this->declare(hndl);
227  hndl.setOwner(this);
228 
229  return PBASE::declareProperty(name,hndl,doc);
230  }

◆ declareProperty() [3/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
SG::VarHandleKeyArray &  hndArr,
const std::string &  doc,
const SG::VarHandleKeyArrayType &   
)
inlineinherited

Definition at line 259 of file AthCommonDataStore.h.

263  {
264 
265  // std::ostringstream ost;
266  // ost << Algorithm::name() << " VHKA declareProp: " << name
267  // << " size: " << hndArr.keys().size()
268  // << " mode: " << hndArr.mode()
269  // << " vhka size: " << m_vhka.size()
270  // << "\n";
271  // debug() << ost.str() << endmsg;
272 
273  hndArr.setOwner(this);
274  m_vhka.push_back(&hndArr);
275 
276  Gaudi::Details::PropertyBase* p = PBASE::declareProperty(name, hndArr, doc);
277  if (p != 0) {
278  p->declareUpdateHandler(&AthCommonDataStore<PBASE>::updateVHKA, this);
279  } else {
280  ATH_MSG_ERROR("unable to call declareProperty on VarHandleKeyArray "
281  << name);
282  }
283 
284  return p;
285 
286  }

◆ declareProperty() [4/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
T &  property,
const std::string &  doc,
const SG::NotHandleType &   
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
propertyObject holding the property value.
docDocumentation string for the property.

This is the generic version, for types that do not derive from SG::VarHandleKey. It just forwards to the base class version of declareProperty.

Definition at line 333 of file AthCommonDataStore.h.

337  {
338  return PBASE::declareProperty(name, property, doc);
339  }

◆ declareProperty() [5/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
T &  property,
const std::string &  doc = "none" 
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
propertyObject holding the property value.
docDocumentation string for the property.

This dispatches to either the generic declareProperty or the one for VarHandle/Key/KeyArray.

Definition at line 352 of file AthCommonDataStore.h.

355  {
356  typedef typename SG::HandleClassifier<T>::type htype;
357  return declareProperty (name, property, doc, htype());
358  }

◆ declareProperty() [6/6]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( Gaudi::Property< T > &  t)
inlineinherited

Definition at line 145 of file AthCommonDataStore.h.

145  {
146  typedef typename SG::HandleClassifier<T>::type htype;
147  return AthCommonDataStore<PBASE>::declareGaudiProperty(t, htype());
148  }

◆ detStore()

const ServiceHandle<StoreGateSvc>& AthCommonDataStore< AthCommonMsg< AlgTool > >::detStore ( ) const
inlineinherited

The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 95 of file AthCommonDataStore.h.

95 { return m_detStore; }

◆ etFwdElSort()

static bool LVL1::jFEXFPGA::etFwdElSort ( const std::vector< uint32_t > &  i,
const std::vector< uint32_t > &  j 
)
inlinestaticprivate

Definition at line 107 of file jFEXFPGA.h.

109  { return (((i.at(0) >> FEXAlgoSpaceDefs::jEM_etBit ) & 0x7ff )> ((j.at(0) >> FEXAlgoSpaceDefs::jEM_etBit) & 0x7ff ));}

◆ evtStore() [1/2]

ServiceHandle<StoreGateSvc>& AthCommonDataStore< AthCommonMsg< AlgTool > >::evtStore ( )
inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 85 of file AthCommonDataStore.h.

85 { return m_evtStore; }

◆ evtStore() [2/2]

const ServiceHandle<StoreGateSvc>& AthCommonDataStore< AthCommonMsg< AlgTool > >::evtStore ( ) const
inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 90 of file AthCommonDataStore.h.

90 { return m_evtStore; }

◆ execute()

StatusCode LVL1::jFEXFPGA::execute ( jFEXOutputCollection *  inputOutputCollection,
const std::pair< unsigned int, const std::vector< int > & > &  jetCalibrationParameters 
)
overridevirtual

Retrieve the L1 menu configuration

Implements LVL1::IjFEXFPGA.

Definition at line 91 of file jFEXFPGA.cxx.

91  {
92 
93  // Retrieve the L1 menu configuration
94  SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
95 
96  const TrigConf::L1ThrExtraInfo_jTAU & thr_jTAU = l1Menu->thrExtraInfo().jTAU();
97  const TrigConf::L1ThrExtraInfo_jJ & thr_jJ = l1Menu->thrExtraInfo().jJ();
98  const TrigConf::L1ThrExtraInfo_jLJ & thr_jLJ = l1Menu->thrExtraInfo().jLJ();
99  const TrigConf::L1ThrExtraInfo_jTE & thr_jTE = l1Menu->thrExtraInfo().jTE();
100  const TrigConf::L1ThrExtraInfo_jXE & thr_jXE = l1Menu->thrExtraInfo().jXE();
101 
102  SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey/*,ctx*/);
103  if(!jTowerContainer.isValid()) {
104  ATH_MSG_ERROR("Could not retrieve container " << m_jTowerContainerKey.key() );
105  return StatusCode::FAILURE;
106  }
107 
108  ATH_CHECK( m_jFEXPileupAndNoiseTool->safetyTest());
109  ATH_CHECK( m_jFEXPileupAndNoiseTool->reset());
110  if(m_jfexid == 0 || m_jfexid == 5) {
111  m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Wide);
112  }
113  else {
114  m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Thin);
115  }
116 
117  //Calculating and sustracting pileup
118  const std::vector<int> pileup_rho = m_jFEXPileupAndNoiseTool->CalculatePileup();
119 
120  //From the DB
121  ATH_CHECK(m_jFEXPileupAndNoiseTool->ApplyPileup());
122 
123  //Noise should be always applied
124  m_jFEXPileupAndNoiseTool->ApplyNoise2Jets(true);
125  m_jFEXPileupAndNoiseTool->ApplyNoise2Met(true);
126  //Getting the values
127  m_map_HAD_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_HAD_Et_values();
128  m_map_EM_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_EM_Et_values();
129  m_map_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->GetEt_values();
130  std::vector<int> pileup_ID;
131  std::vector<int> pileup_HAD_jet;
132  std::vector<int> pileup_EM_jet;
133  std::vector<int> pileup_Total_jet;
134  std::vector<int> pileup_HAD_met;
135  std::vector<int> pileup_EM_met;
136  std::vector<int> pileup_Total_met;
137  for (auto const& [key, val] : m_map_HAD_Etvalues_FPGA)
138  {
139  pileup_ID.push_back(key);
140  pileup_HAD_jet.push_back(val[0]);
141  pileup_EM_jet.push_back(m_map_EM_Etvalues_FPGA[key][0]);
142  pileup_Total_jet.push_back(m_map_Etvalues_FPGA[key][0]);
143  pileup_HAD_met.push_back(val[1]);
144  pileup_EM_met.push_back(m_map_EM_Etvalues_FPGA[key][1]);
145  pileup_Total_met.push_back(m_map_Etvalues_FPGA[key][1]);
146  }
147 
148  //saving pileup information
149  inputOutputCollection->addValue_pileup("pileup_FPGAid", m_id);
150  inputOutputCollection->addValue_pileup("pileup_jFEXid", m_jfexid);
151  inputOutputCollection->addValue_pileup("pileup_rho_EM", pileup_rho[0]);
152  inputOutputCollection->addValue_pileup("pileup_rho_HAD1", pileup_rho[1]);
153  inputOutputCollection->addValue_pileup("pileup_rho_HAD2", pileup_rho[2]);
154  inputOutputCollection->addValue_pileup("pileup_rho_HAD3", pileup_rho[3]);
155  inputOutputCollection->addValue_pileup("pileup_rho_FCAL", pileup_rho[4]);
156  inputOutputCollection->addValue_pileup("pileup_map_ID" , pileup_ID);
157  inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_jet" , pileup_HAD_jet);
158  inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_jet" , pileup_EM_jet);
159  inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_jet", pileup_Total_jet);
160  inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_met" , pileup_HAD_met);
161  inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_met" , pileup_EM_met);
162  inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_met", pileup_Total_met);
163  inputOutputCollection->fill_pileup();
164 
165  if(m_id==0 || m_id==3) {
166  ATH_CHECK( m_jFEXsumETAlgoTool->safetyTest());
167  ATH_CHECK( m_jFEXsumETAlgoTool->reset());
168  ATH_CHECK( m_jFEXmetAlgoTool->safetyTest());
169  ATH_CHECK( m_jFEXmetAlgoTool->reset());
170 
171  m_jFEXsumETAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
172  m_jFEXmetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
173 
174  unsigned int bin_pos = thr_jTE.etaBoundary_fw(m_jfex_string[m_jfexid]);
175 
176  std::unique_ptr<jFEXTOB> jXE_tob = std::make_unique<jFEXTOB>();
177  uint32_t jXE_tobword = 0;
178 
179  std::unique_ptr<jFEXTOB> jTE_tob = std::make_unique<jFEXTOB>();
180  uint32_t jTE_tobword = 0;
181 
182 
183  int hemisphere = m_id == 0 ? 1 : -1;
184 
185  if(m_jfexid > 0 && m_jfexid < 5) {
186 
187  //-----------------jFEXsumETAlgo-----------------
188  m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Thin);
189  m_jFEXsumETAlgoTool->buildBarrelSumET();
190 
191  //-----------------jFEXmetAlgo-----------------
192  m_jFEXmetAlgoTool->setup(m_jTowersIDs_Thin, hemisphere);
193  m_jFEXmetAlgoTool->buildBarrelmet();
194  }
195  else if(m_jfexid == 0 ) {
196 
197  int flipped_jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}};
198  int max_phi_it = FEXAlgoSpaceDefs::jFEX_algoSpace_height-1;
199  int max_eta_it = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-1;
200  for(int mphi = 0; mphi <= max_phi_it; mphi++) {
201  for(int meta = 0; meta <= max_eta_it; meta++) {
202  flipped_jTowersIDs[mphi][meta]=m_jTowersIDs_Wide[mphi][max_eta_it-meta];
203  }
204  }
205  //-----------------jFEXsumETAlgo-----------------
206  m_jFEXsumETAlgoTool->setup(flipped_jTowersIDs);
207  m_jFEXsumETAlgoTool->buildFWDSumET();
208 
209  //-----------------jFEXmetAlgo-----------------
210  m_jFEXmetAlgoTool->setup(flipped_jTowersIDs, hemisphere);
211  m_jFEXmetAlgoTool->buildFWDmet();
212  }
213  else if(m_jfexid == 5) {
214 
215  //-----------------jFEXsumETAlgo-----------------
216  m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Wide);
217  m_jFEXsumETAlgoTool->buildFWDSumET();
218 
219  //-----------------jFEXmetAlgo-----------------
220  m_jFEXmetAlgoTool->setup(m_jTowersIDs_Wide, hemisphere);
221  m_jFEXmetAlgoTool->buildFWDmet();
222  }
223 
224  jXE_tobword = m_IjFEXFormTOBsTool->formMetTOB(m_jFEXmetAlgoTool->GetMetXComponent(), m_jFEXmetAlgoTool->GetMetYComponent(),m_jFEXmetAlgoTool->getjXESat(),thr_jXE.resolutionMeV());
225  jXE_tob->initialize(m_id,m_jfexid,jXE_tobword,thr_jXE.resolutionMeV(),0);
226  m_Met_tobwords.push_back(std::move(jXE_tob));
227 
228  std::tuple<int,bool> jTElow;
229  std::tuple<int,bool> jTEhigh;
230 
231  // NOTE: Foward FPGA in the C-side is already flipped, however we still need to flip the jFEX module 1 and 2
232  if(m_jfexid == 1 || m_jfexid == 2){
233  jTElow = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
234  jTEhigh = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
235  }
236  else{
237  jTElow = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
238  jTEhigh = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
239  }
240 
241  jTE_tobword = m_IjFEXFormTOBsTool->formSumETTOB(jTElow,jTEhigh,thr_jTE.resolutionMeV());
242  jTE_tob->initialize(m_id,m_jfexid,jTE_tobword,thr_jTE.resolutionMeV(),0);
243  m_sumET_tobwords.push_back(std::move(jTE_tob));
244  }
245 
246  //-----------jFEXSmallRJet & Large R Jet Algo-----------------
247  ATH_MSG_DEBUG("================ Central Algorithms ================");
248 
249  int srJet_seedThresholdMeV = thr_jJ.seedThresholdMeV(m_jfex_string[m_jfexid]); //jFEX internal granularity, i.e., 25 MeV/count
250 
251  //Central region algorithms
252  if(m_jfexid > 0 && m_jfexid < 5) {
253  m_jFEXSmallRJetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
254  m_jFEXLargeRJetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
255  m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
256 
257  for(int mphi = 8; mphi < FEXAlgoSpaceDefs::jFEX_algoSpace_height-8; mphi++) {
258  for(int meta = 8; meta < FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width-8; meta++) {
259 
260  //definition of arrays
261  int TT_seed_ID[3][3]= {{0}};
262  int TT_First_ETring[36]= {0};
263  int First_ETring_it = 0;
264 
265  int Jet_SearchWindow[7][7] = {{0}};
266  int Jet_SearchWindowDisplaced[7][7] = {{0}};
267  int largeRCluster_IDs[15][15]= {{0}};
268 
269  //filling up array to send them to the algorithms
270  for(int i = -7; i< 8; i++ ) {
271  for(int j = -7; j< 8; j++) {
272 
273  if(std::abs(i)<4 && std::abs(j)<4) {
274  Jet_SearchWindow[3 + i][3 + j] = m_jTowersIDs_Thin[mphi + i][meta +j];
275  Jet_SearchWindowDisplaced[3 + i][3 + j] = m_jTowersIDs_Thin[mphi+i+1][meta+j+1];
276  }
277 
278  uint deltaR = std::sqrt(std::pow(i,2)+std::pow(j,2));
279 
280  if(deltaR<2) {
281  TT_seed_ID[i+1][j+1] = m_jTowersIDs_Thin[mphi +i][meta +j]; // Seed 0.3x0.3 in phi-eta plane
282  }
283  else if(deltaR<4) {
284  TT_First_ETring[First_ETring_it]= m_jTowersIDs_Thin[mphi +i][meta +j]; // First energy ring, will be used as tau ISO
285  ++First_ETring_it;
286 
287  }
288  else if(deltaR<8) {
289  largeRCluster_IDs[7 +i][7 +j] = m_jTowersIDs_Thin[mphi + i][meta +j];
290  }
291  }
292  }
293 
294  // ******** jJ and jLJ algorithms ********
295  ATH_CHECK( m_jFEXSmallRJetAlgoTool->safetyTest());
296  ATH_CHECK( m_jFEXLargeRJetAlgoTool->safetyTest());
297  m_jFEXSmallRJetAlgoTool->setup(Jet_SearchWindow, Jet_SearchWindowDisplaced);
298  m_jFEXLargeRJetAlgoTool->setupCluster(largeRCluster_IDs);
299  m_jFEXSmallRJetAlgoTool->buildSeeds();
300 
301  bool is_Jet_LM = m_jFEXSmallRJetAlgoTool->isSeedLocalMaxima(srJet_seedThresholdMeV);
302 
303  if(is_Jet_LM) {
304 
305  //getting the energies
306  int SRj_Et = m_jFEXSmallRJetAlgoTool->getSmallClusterET();
307  int LRj_Et = m_jFEXLargeRJetAlgoTool->getLargeClusterET(SRj_Et,m_jFEXLargeRJetAlgoTool->getRingET());
308 
309  bool SRj_Sat = m_jFEXSmallRJetAlgoTool->getSRjetSat();
310  bool LRj_Sat = SRj_Sat || m_jFEXLargeRJetAlgoTool->getLRjetSat();
311 
312  int meta_LM = meta;
313  int mphi_LM = mphi;
314 
315  //Creating SR TOB
316  uint32_t SRJet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, mphi_LM, meta_LM, SRj_Et, SRj_Sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
317 
318  std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
319  jJ_tob->initialize(m_id,m_jfexid,SRJet_tobword,thr_jJ.resolutionMeV(),m_jTowersIDs_Thin[mphi_LM][meta_LM]);
320  if ( SRJet_tobword != 0 ){
321  m_SRJet_tobwords.push_back(std::move(jJ_tob));
322  }
323 
324  //Creating LR TOB
325  uint32_t LRJet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, mphi_LM, meta_LM, LRj_Et, LRj_Sat, thr_jLJ.resolutionMeV(), thr_jLJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
326 
327  std::unique_ptr<jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
328  jLJ_tob->initialize(m_id,m_jfexid,LRJet_tobword,thr_jLJ.resolutionMeV(),m_jTowersIDs_Thin[mphi_LM][meta_LM]);
329  if ( LRJet_tobword != 0 ) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
330 
331  }
332  // ******** jTau algorithm ********
333 
334  ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
335  m_jFEXtauAlgoTool->setup(TT_seed_ID);
336  bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima();
337 
338  // Save TOB is tau is a local maxima
339  if ( is_tau_LocalMax ) {
340 
341  //calculates the 1st energy ring
342  m_jFEXtauAlgoTool->setFirstEtRing(TT_First_ETring);
343 
344 
345  uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
346 
347  std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
348  jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),m_jTowersIDs_Thin[mphi][meta]);
349 
350  if ( jTau_tobword != 0 ){
351  m_tau_tobwords.push_back(std::move(jTau_tob));
352  }
353  }
354  }
355  }
356  } //end of if statement for checking if in central jfex modules
357 
358  //FCAL region algorithm
359  if(m_jfexid ==0 || m_jfexid ==5) {
360 
361  //**********Forward Jets***********************
362  ATH_CHECK(m_jFEXForwardJetsAlgoTool->safetyTest());
363  ATH_CHECK(m_jFEXForwardJetsAlgoTool->reset());
364  m_jFEXForwardJetsAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
365  m_jFEXForwardJetsAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid);
366 
367  m_FCALJets = m_jFEXForwardJetsAlgoTool->calculateJetETs(srJet_seedThresholdMeV);
368  for(std::unordered_map<int, jFEXForwardJetsInfo>::iterator it = m_FCALJets.begin(); it!=(m_FCALJets.end()); ++it) {
369 
370  uint32_t TTID = it->first;
371  jFEXForwardJetsInfo FCALJets = it->second;
372 
373  int iphi = FCALJets.getCentreLocalTTPhi();
374  int ieta = FCALJets.getCentreLocalTTEta();
375  m_SRJetET = FCALJets.getSeedET() + FCALJets.getFirstEnergyRingET();
376  m_LRJetET = m_SRJetET + FCALJets.getSecondEnergyRingET();
377 
378  bool SRJ_sat = FCALJets.getSRjetSat();
379 
380  uint32_t SRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, iphi, ieta, m_SRJetET, SRJ_sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
381 
382  std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
383  jJ_tob->initialize(m_id,m_jfexid,SRFCAL_Jet_tobword,thr_jJ.resolutionMeV(),TTID);
384 
385  if ( SRFCAL_Jet_tobword != 0 ){
386  m_SRJet_tobwords.push_back(std::move(jJ_tob));
387  }
388 
389  if(std::fabs(FCALJets.getCentreTTEta())<2.51){
390  bool LRJ_sat = FCALJets.getLRjetSat();
391  uint32_t LRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, iphi, ieta, m_LRJetET, LRJ_sat, thr_jLJ.resolutionMeV(),thr_jLJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
392 
393  std::unique_ptr<jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
394  jLJ_tob->initialize(m_id,m_jfexid,LRFCAL_Jet_tobword,thr_jLJ.resolutionMeV(),TTID);
395  if ( LRFCAL_Jet_tobword != 0 ) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
396  }
397 
398  }
399  //********** Forward Electrons ***********************
400  ATH_CHECK(m_jFEXForwardElecAlgoTool->safetyTest());
401  ATH_CHECK(m_jFEXForwardElecAlgoTool->reset());
402  m_jFEXForwardElecAlgoTool->setFPGAEnergy(m_map_EM_Etvalues_FPGA,m_map_HAD_Etvalues_FPGA);
403  m_jFEXForwardElecAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid,m_id);
404  m_ForwardElecs = m_jFEXForwardElecAlgoTool->calculateEDM();
405 
407  SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
408  const TrigConf::L1ThrExtraInfo_jEM & thr_jEM = l1Menu->thrExtraInfo().jEM();
409  const uint jFEXETResolution = thr_jEM.resolutionMeV();//200
410  std::string str_jfexname = m_jfex_string[m_jfexid];
411  uint minEtThreshold = thr_jEM.ptMinToTopoMeV(str_jfexname)/jFEXETResolution;
412  //uint Cval[9] = {1,2,3,20,30,40,20,30,40};//C values for iso, emfr1 and emfr2
413  std::vector<int> Ciso;
414  std::vector<int> Chad1;
415  std::vector<int> Chad2;
416 
417  for(std::unordered_map<uint, jFEXForwardElecInfo>::iterator itel = m_ForwardElecs.begin(); itel!=(m_ForwardElecs.end()); ++itel) {
418  uint32_t TTID = itel->first;
419  jFEXForwardElecInfo elCluster = itel->second;
420  uint meta = elCluster.getCoreIeta();//check whether this is the one used by the Trigger conf
421 
422  //retrieve jet rejection thresholds from trigger configuration
423  auto wp_loose = thr_jEM.isolation(TrigConf::Selection::WP::LOOSE, meta);
424  auto wp_medium = thr_jEM.isolation(TrigConf::Selection::WP::MEDIUM, meta);
425  auto wp_tight = thr_jEM.isolation(TrigConf::Selection::WP::TIGHT, meta);
426  Ciso.clear();
427  Chad1.clear();
428  Chad2.clear();
429  Ciso.push_back(wp_loose.iso_fw());
430  Ciso.push_back(wp_medium.iso_fw());
431  Ciso.push_back(wp_tight.iso_fw());
432  Chad1.push_back(wp_loose.frac_fw());
433  Chad1.push_back(wp_medium.frac_fw());
434  Chad1.push_back(wp_tight.frac_fw());
435  Chad2.push_back(wp_loose.frac2_fw());
436  Chad2.push_back(wp_medium.frac2_fw());
437  Chad2.push_back(wp_tight.frac2_fw());
438  int Cval[9] = {Ciso[0], Ciso[1], Ciso[2], Chad1[0], Chad1[1], Chad1[2], Chad2[0], Chad2[1], Chad2[2]};
439 
440  elCluster.setup(Cval,jFEXETResolution);
441  elCluster.calcFwdElEDM();
442 
443  uint etEM = elCluster.getEt();
444  uint32_t FwdEl_tobword = elCluster.getTobWord();
445 
446 
447  std::vector<uint32_t> FwdEltob_aux{FwdEl_tobword,TTID};
448  if ( FwdEl_tobword != 0 && etEM>minEtThreshold) m_FwdEl_tobwords.push_back(FwdEltob_aux);
449  }
450 
451  //******************************** TAU **********************************************
452  int jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}};
453  int max_meta=17;
454 
455  if(m_jfexid ==0) {
456  for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
457  for(int j=28; j<(FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-6); j++) { //lower values of j (j<28) are the Fcals not entering in the jFEX tau range
458  jTowersIDs[i][j-28+8]=m_jTowersIDs_Wide[i][j]; // second argument in m_jTowersIDs is to center the FPGA core area in te same region as the central FPGAs
459  }
460  }
461 
462  }
463  else if(m_jfexid ==5 ) {
464 
465  // Filling m_jTowersIDs with the m_jTowersIDs_Wide ID values up to 2.5 eta
466  for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
467  for(int j=4; j<17; j++) { //higher values of j (j>16) are the Fcals not entering in the jFEX tau range
468  jTowersIDs[i][j]=m_jTowersIDs_Wide[i][j];
469  }
470  }
471  }
472  ATH_MSG_DEBUG("============================ jFEXtauAlgo ============================");
473  ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
474  m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
475  for(int mphi = 8; mphi < 24; mphi++) {
476  for(int meta = 8; meta < max_meta; meta++) {
477 
478  bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima_fwd(jTowersIDs[mphi][meta]);
479 
480  // Save TOB is tau is a local maxima
481  if ( is_tau_LocalMax ) {
482 
483  uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
484 
485  std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
486  jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),jTowersIDs[mphi][meta]);
487  if ( jTau_tobword != 0 ){
488  m_tau_tobwords.push_back(std::move(jTau_tob));
489  }
490  }
491  }
492  }
493  } //end of if statement for checking if in central jfex modules
494  return StatusCode::SUCCESS;
495 } //end of the execute function

◆ extraDeps_update_handler()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::extraDeps_update_handler ( Gaudi::Details::PropertyBase &  ExtraDeps)
protectedinherited

Add StoreName to extra input/output deps as needed.

use the logic of the VarHandleKey to parse the DataObjID keys supplied via the ExtraInputs and ExtraOuputs Properties to add the StoreName if it's not explicitly given

◆ getFwdElTOBs()

std::vector< std::vector< uint32_t > > LVL1::jFEXFPGA::getFwdElTOBs ( )
overridevirtual

sorted Electron tobs

Implements LVL1::IjFEXFPGA.

Definition at line 571 of file jFEXFPGA.cxx.

572  {
573  auto tobsSort = m_FwdEl_tobwords;
574 
575  ATH_MSG_DEBUG("number of Forward Elec tobs: " << tobsSort.size() << " in FPGA: " << m_id<< " before truncation");
576  //sort tobs by their et
577  std::sort (tobsSort.begin(), tobsSort.end(), etFwdElSort);
578 
579  return tobsSort;
580 
581  }

◆ getLargeRJetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getLargeRJetTOBs ( )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 554 of file jFEXFPGA.cxx.

555 {
556 
557 
558  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
559  tobsSort.clear();
560 
561  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
562  for(auto &j : m_LRJet_tobwords) {
563  tobsSort.push_back(std::move(j));
564  }
565  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jLJ_etBit, 0x1fff));
566 
567  return tobsSort;
568 
569 }

◆ getMetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getMetTOBs ( )
overridevirtual

Form a tob word out of the potential candidate MET tob.

Implements LVL1::IjFEXFPGA.

Definition at line 614 of file jFEXFPGA.cxx.

614  {
615 
616  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
617  tobsSort.clear();
618 
619  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
620  for(auto &j : m_Met_tobwords) {
621  tobsSort.push_back(std::move(j));
622  }
623 
624  return tobsSort;
625 
626 }

◆ getSmallRJetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getSmallRJetTOBs ( )
overridevirtual

Form a tob word out of the potential candidate SmallRJet tob.

Implements LVL1::IjFEXFPGA.

Definition at line 538 of file jFEXFPGA.cxx.

539 {
540 
541  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
542  tobsSort.clear();
543 
544  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
545  for(auto &j : m_SRJet_tobwords) {
546  tobsSort.push_back(std::move(j));
547  }
548  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jJ_etBit, 0x7ff));
549 
550  return tobsSort;
551 
552 }

◆ getSumEtTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getSumEtTOBs ( )
overridevirtual

Form a tob word out of the potential candidate SumET tob.

Implements LVL1::IjFEXFPGA.

Definition at line 598 of file jFEXFPGA.cxx.

598  {
599 
600  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
601  tobsSort.clear();
602 
603  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
604  for(auto &j : m_sumET_tobwords) {
605  tobsSort.push_back(std::move(j));
606  }
607 
608  return tobsSort;
609 
610 }

◆ getTauTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getTauTOBs ( )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 584 of file jFEXFPGA.cxx.

584  {
585 
586  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
587  tobsSort.clear();
588 
589  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
590  for(auto &j : m_tau_tobwords) {
591  tobsSort.push_back(std::move(j));
592  }
593  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jTau_etBit, 0x7ff));
594 
595  return tobsSort;
596 }

◆ getTTowerET()

int LVL1::jFEXFPGA::getTTowerET ( unsigned int  TTID)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 656 of file jFEXFPGA.cxx.

656  {
657 
658  return getTTowerET_EM(TTID)+getTTowerET_HAD(TTID);
659 
660 }

◆ getTTowerET_EM()

int LVL1::jFEXFPGA::getTTowerET_EM ( unsigned int  TTID)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 630 of file jFEXFPGA.cxx.

630  {
631 
632  if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
633  return m_map_EM_Etvalues_FPGA[TTID][0];
634  }
635 
636  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_EM, TTower ID not found in map: " << TTID );
637  return -99999;
638 
639 }

◆ getTTowerET_forMET()

int LVL1::jFEXFPGA::getTTowerET_forMET ( unsigned int  TTID)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 664 of file jFEXFPGA.cxx.

664  {
665 
666  int tmp_EM = 0;
667  if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
668  tmp_EM = m_map_EM_Etvalues_FPGA[TTID][1];
669  }
670  else{
671  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (EM energy), TTower ID not found in map: " << TTID );
672  tmp_EM = -99999;
673  }
674 
675 
676  int tmp_HAD = 0;
677  if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
678  tmp_HAD = m_map_HAD_Etvalues_FPGA[TTID][1];
679  }
680  else{
681  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (HAD energy), TTower ID not found in map: " << TTID );
682  tmp_HAD = -99999;
683  }
684 
685 
686  return tmp_EM + tmp_HAD;
687 
688 }

◆ getTTowerET_HAD()

int LVL1::jFEXFPGA::getTTowerET_HAD ( unsigned int  TTID)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 643 of file jFEXFPGA.cxx.

643  {
644 
645  if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
646  return m_map_HAD_Etvalues_FPGA[TTID][0];
647  }
648 
649  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_HAD, TTower ID not found in map: " << TTID );
650  return -99999;
651 
652 }

◆ getTTowerET_SG()

int LVL1::jFEXFPGA::getTTowerET_SG ( unsigned int  TTID)
private

Definition at line 692 of file jFEXFPGA.cxx.

692  {
693 
694  if(TTID == 0){
695  return -999;
696  }
697  SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey);
698  const LVL1::jTower * tmpTower = jTowerContainer->findTower(TTID);
699  return tmpTower->getTotalET();
700 }

◆ ID()

virtual int LVL1::jFEXFPGA::ID ( )
inlineoverridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 74 of file jFEXFPGA.h.

74 {return m_id;}

◆ init()

StatusCode LVL1::jFEXFPGA::init ( int  id,
int  efexid 
)
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 68 of file jFEXFPGA.cxx.

68  {
69  m_id = id;
70  m_jfexid = jfexid;
71 
72  return StatusCode::SUCCESS;
73 
74 }

◆ initialize()

StatusCode LVL1::jFEXFPGA::initialize ( )
overridevirtual

standard Athena-Algorithm method

Definition at line 60 of file jFEXFPGA.cxx.

60  {
61 
62  ATH_CHECK(m_jTowerContainerKey.initialize());
63  ATH_CHECK(m_l1MenuKey.initialize());
64  ATH_CHECK(m_jFEXtauAlgoTool.retrieve());
65  return StatusCode::SUCCESS;
66 }

◆ inputHandles()

virtual std::vector<Gaudi::DataHandle*> AthCommonDataStore< AthCommonMsg< AlgTool > >::inputHandles ( ) const
overridevirtualinherited

Return this algorithm's input handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ interfaceID()

const InterfaceID & LVL1::IjFEXFPGA::interfaceID ( )
inlinestaticinherited

Definition at line 73 of file IjFEXFPGA.h.

74  {
75  return IID_IjFEXFPGA;
76  }

◆ msg() [1/2]

MsgStream& AthCommonMsg< AlgTool >::msg ( ) const
inlineinherited

Definition at line 24 of file AthCommonMsg.h.

24  {
25  return this->msgStream();
26  }

◆ msg() [2/2]

MsgStream& AthCommonMsg< AlgTool >::msg ( const MSG::Level  lvl) const
inlineinherited

Definition at line 27 of file AthCommonMsg.h.

27  {
28  return this->msgStream(lvl);
29  }

◆ msgLvl()

bool AthCommonMsg< AlgTool >::msgLvl ( const MSG::Level  lvl) const
inlineinherited

Definition at line 30 of file AthCommonMsg.h.

30  {
31  return this->msgLevel(lvl);
32  }

◆ outputHandles()

virtual std::vector<Gaudi::DataHandle*> AthCommonDataStore< AthCommonMsg< AlgTool > >::outputHandles ( ) const
overridevirtualinherited

Return this algorithm's output handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ renounce()

std::enable_if_t<std::is_void_v<std::result_of_t<decltype(&T::renounce)(T)> > && !std::is_base_of_v<SG::VarHandleKeyArray, T> && std::is_base_of_v<Gaudi::DataHandle, T>, void> AthCommonDataStore< AthCommonMsg< AlgTool > >::renounce ( T &  h)
inlineprotectedinherited

Definition at line 380 of file AthCommonDataStore.h.

381  {
382  h.renounce();
383  PBASE::renounce (h);
384  }

◆ renounceArray()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::renounceArray ( SG::VarHandleKeyArray &  handlesArray)
inlineprotectedinherited

remove all handles from I/O resolution

Definition at line 364 of file AthCommonDataStore.h.

364  {
365  handlesArray.renounce();
366  }

◆ reset()

void LVL1::jFEXFPGA::reset ( )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 76 of file jFEXFPGA.cxx.

76  {
77 
78  m_id = -1;
79  m_jfexid = -1;
80  m_tau_tobwords.clear();
81  m_SRJet_tobwords.clear();
82  m_LRJet_tobwords.clear();
83  m_sumET_tobwords.clear();
84  m_Met_tobwords.clear();
85  m_map_Etvalues_FPGA.clear();
86  m_map_EM_Etvalues_FPGA.clear();
87  m_map_HAD_Etvalues_FPGA.clear();
88  m_FwdEl_tobwords.clear();
89 }

◆ SetTowersAndCells_SG() [1/2]

void LVL1::jFEXFPGA::SetTowersAndCells_SG ( int  tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 515 of file jFEXFPGA.cxx.

515  {
516 
517  const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
518  const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
519 
520  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Thin[0][0]);
521 
522  //this prints out the jTower IDs that each FPGA is responsible for
523  ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
524 
525  for (int thisRow=rows-1; thisRow>=0; thisRow--) {
526  for (int thisCol=0; thisCol<cols; thisCol++) {
527  if(thisCol != cols-1) {
528  ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " ");
529  }
530  else {
531  ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " |");
532  }
533  }
534  }
535 
536 }

◆ SetTowersAndCells_SG() [2/2]

void LVL1::jFEXFPGA::SetTowersAndCells_SG ( int  tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 497 of file jFEXFPGA.cxx.

497  {
498 
499  const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
500  const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
501 
502  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Wide[0][0]);
503 
504  ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
505 
506  for (int thisRow=rows-1; thisRow>=0; thisRow--){
507  for (int thisCol=0; thisCol<cols; thisCol++){
508  if(thisCol != cols-1){ ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " "); }
509  else { ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " |"); }
510  }
511  }
512 
513 }

◆ sysInitialize()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysInitialize ( )
overridevirtualinherited

Perform system initialization for an algorithm.

We override this to declare all the elements of handle key arrays at the end of initialization. See comments on updateVHKA.

Reimplemented in DerivationFramework::CfAthAlgTool, AthCheckedComponent< AthAlgTool >, AthCheckedComponent<::AthAlgTool >, and asg::AsgMetadataTool.

◆ sysStart()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysStart ( )
overridevirtualinherited

Handle START transition.

We override this in order to make sure that conditions handle keys can cache a pointer to the conditions container.

◆ TOBetSort()

template<class TOBObjectClass >
static bool LVL1::jFEXFPGA::TOBetSort ( const TOBObjectClass &  i,
const TOBObjectClass &  j,
uint  bits,
uint  mask 
)
inlinestaticprivate

Internal data.

Definition at line 103 of file jFEXFPGA.h.

103  {
104  return (((i->getWord() >> bits ) & mask)>((j->getWord() >> bits ) & mask));
105  }

◆ updateVHKA()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::updateVHKA ( Gaudi::Details::PropertyBase &  )
inlineinherited

Definition at line 308 of file AthCommonDataStore.h.

308  {
309  // debug() << "updateVHKA for property " << p.name() << " " << p.toString()
310  // << " size: " << m_vhka.size() << endmsg;
311  for (auto &a : m_vhka) {
312  std::vector<SG::VarHandleKey*> keys = a->keys();
313  for (auto k : keys) {
314  k->setOwner(this);
315  }
316  }
317  }

Member Data Documentation

◆ m_detStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_detStore
privateinherited

Pointer to StoreGate (detector store by default)

Definition at line 393 of file AthCommonDataStore.h.

◆ m_evtStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_evtStore
privateinherited

Pointer to StoreGate (event store by default)

Definition at line 390 of file AthCommonDataStore.h.

◆ m_FCALJets

std::unordered_map<int, jFEXForwardJetsInfo> LVL1::jFEXFPGA::m_FCALJets
private

Definition at line 131 of file jFEXFPGA.h.

◆ m_ForwardElecs

std::unordered_map<uint, jFEXForwardElecInfo> LVL1::jFEXFPGA::m_ForwardElecs
private

Definition at line 132 of file jFEXFPGA.h.

◆ m_FwdEl_tobwords

std::vector<std::vector<uint32_t> > LVL1::jFEXFPGA::m_FwdEl_tobwords
private

Definition at line 120 of file jFEXFPGA.h.

◆ m_id

int LVL1::jFEXFPGA::m_id
private

Definition at line 117 of file jFEXFPGA.h.

◆ m_IjFEXFormTOBsTool

ToolHandle<IjFEXFormTOBs> LVL1::jFEXFPGA::m_IjFEXFormTOBsTool {this, "IjFEXFormTOBsTool", "LVL1::jFEXFormTOBs", "Tool that forms TOB words"}
private

Definition at line 149 of file jFEXFPGA.h.

◆ m_jfex_string

std::string LVL1::jFEXFPGA::m_jfex_string[6] = {"1C","2C","3C","3A","2A","1A"}
private

Definition at line 152 of file jFEXFPGA.h.

◆ m_jFEXForwardElecAlgoTool

ToolHandle<IjFEXForwardElecAlgo> LVL1::jFEXFPGA::m_jFEXForwardElecAlgoTool {this, "jFEXForwardElecAlgoTool" , "LVL1::jFEXForwardElecAlgo" , "Tool that runs the jFEX FCAL Electrons algorithm"}
private

Definition at line 147 of file jFEXFPGA.h.

◆ m_jFEXForwardJetsAlgoTool

ToolHandle<IjFEXForwardJetsAlgo> LVL1::jFEXFPGA::m_jFEXForwardJetsAlgoTool {this, "jFEXForwardJetsAlgoTool" , "LVL1::jFEXForwardJetsAlgo" , "Tool that runs the jFEX FCAL Jets algorithm"}
private

Definition at line 146 of file jFEXFPGA.h.

◆ m_jfexid

int LVL1::jFEXFPGA::m_jfexid
private

Definition at line 118 of file jFEXFPGA.h.

◆ m_jFEXLargeRJetAlgoTool

ToolHandle<IjFEXLargeRJetAlgo> LVL1::jFEXFPGA::m_jFEXLargeRJetAlgoTool {this, "jFEXLargeRJetAlgoTool", "LVL1::jFEXLargeRJetAlgo", "Tool that runs the jFEX Large R Jet algorithm"}
private

Definition at line 142 of file jFEXFPGA.h.

◆ m_jFEXmetAlgoTool

ToolHandle<IjFEXmetAlgo> LVL1::jFEXFPGA::m_jFEXmetAlgoTool {this, "jFEXmetAlgoTool" , "LVL1::jFEXmetAlgo" , "Tool that runs the jFEX met algorithm"}
private

Definition at line 145 of file jFEXFPGA.h.

◆ m_jFEXPileupAndNoiseTool

ToolHandle<IjFEXPileupAndNoise> LVL1::jFEXFPGA::m_jFEXPileupAndNoiseTool {this, "jFEXPileupAndNoiseTool", "LVL1::jFEXPileupAndNoise", "Tool that applies Pileup and Noise"}
private

Definition at line 148 of file jFEXFPGA.h.

◆ m_jFEXSmallRJetAlgoTool

ToolHandle<IjFEXSmallRJetAlgo> LVL1::jFEXFPGA::m_jFEXSmallRJetAlgoTool {this, "jFEXSmallRJetAlgoTool", "LVL1::jFEXSmallRJetAlgo", "Tool that runs the jFEX Small R Jet algorithm"}
private

Definition at line 141 of file jFEXFPGA.h.

◆ m_jFEXsumETAlgoTool

ToolHandle<IjFEXsumETAlgo> LVL1::jFEXFPGA::m_jFEXsumETAlgoTool {this, "jFEXsumETAlgoTool" , "LVL1::jFEXsumETAlgo" , "Tool that runs the jFEX sumET algorithm"}
private

Definition at line 144 of file jFEXFPGA.h.

◆ m_jFEXtauAlgoTool

ToolHandle<IjFEXtauAlgo> LVL1::jFEXFPGA::m_jFEXtauAlgoTool {this, "jFEXtauAlgoTool" , "LVL1::jFEXtauAlgo" , "Tool that runs the jFEX tau algorithm"}
private

Definition at line 143 of file jFEXFPGA.h.

◆ m_jTowerContainerKey

SG::ReadHandleKey<LVL1::jTowerContainer> LVL1::jFEXFPGA::m_jTowerContainerKey {this, "MyETowers", "jTowerContainer", "Input container for jTowers"}
private

Definition at line 139 of file jFEXFPGA.h.

◆ m_jTowersColl

std::unordered_map<int,jTower> LVL1::jFEXFPGA::m_jTowersColl
private

Definition at line 125 of file jFEXFPGA.h.

◆ m_jTowersIDs_Thin

int LVL1::jFEXFPGA::m_jTowersIDs_Thin[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}}
private

Definition at line 123 of file jFEXFPGA.h.

◆ m_jTowersIDs_Wide

int LVL1::jFEXFPGA::m_jTowersIDs_Wide[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}}
private

Definition at line 122 of file jFEXFPGA.h.

◆ m_l1MenuKey

SG::ReadHandleKey<TrigConf::L1Menu> LVL1::jFEXFPGA::m_l1MenuKey {this, "L1TriggerMenu", "DetectorStore+L1TriggerMenu","Name of the L1Menu object to read configuration from"}
private

Definition at line 140 of file jFEXFPGA.h.

◆ m_LRJet_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_LRJet_tobwords
private

Definition at line 113 of file jFEXFPGA.h.

◆ m_LRJetET

int LVL1::jFEXFPGA::m_LRJetET
private

Definition at line 135 of file jFEXFPGA.h.

◆ m_map_EM_Etvalues_FPGA

std::unordered_map<int,std::vector<int> > LVL1::jFEXFPGA::m_map_EM_Etvalues_FPGA
private

Definition at line 128 of file jFEXFPGA.h.

◆ m_map_Etvalues_FPGA

std::unordered_map<int,std::vector<int> > LVL1::jFEXFPGA::m_map_Etvalues_FPGA
private

Definition at line 126 of file jFEXFPGA.h.

◆ m_map_HAD_Etvalues_FPGA

std::unordered_map<int,std::vector<int> > LVL1::jFEXFPGA::m_map_HAD_Etvalues_FPGA
private

Definition at line 127 of file jFEXFPGA.h.

◆ m_Met_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_Met_tobwords
private

Definition at line 115 of file jFEXFPGA.h.

◆ m_sCellsCollection

CaloCellContainer LVL1::jFEXFPGA::m_sCellsCollection
private

Definition at line 137 of file jFEXFPGA.h.

◆ m_SRJet_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_SRJet_tobwords
private

Definition at line 112 of file jFEXFPGA.h.

◆ m_SRJetET

int LVL1::jFEXFPGA::m_SRJetET
private

Definition at line 134 of file jFEXFPGA.h.

◆ m_sumET_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_sumET_tobwords
private

Definition at line 114 of file jFEXFPGA.h.

◆ m_tau_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_tau_tobwords
private

Definition at line 111 of file jFEXFPGA.h.

◆ m_varHandleArraysDeclared

bool AthCommonDataStore< AthCommonMsg< AlgTool > >::m_varHandleArraysDeclared
privateinherited

Definition at line 399 of file AthCommonDataStore.h.

◆ m_vhka

std::vector<SG::VarHandleKeyArray*> AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
privateinherited

Definition at line 398 of file AthCommonDataStore.h.

The documentation for this class was generated from the following files:
xAOD::iterator
JetConstituentVector::iterator iterator
Definition: JetConstituentVector.cxx:68
jTowerContainer
Container class for jTower.
TrigConf::Selection::WP::LOOSE
@ LOOSE
LVL1::jFEXFPGA::m_FwdEl_tobwords
std::vector< std::vector< uint32_t > > m_FwdEl_tobwords
Definition: jFEXFPGA.h:120
LVL1::FEXAlgoSpaceDefs::jJ_etBit
constexpr static int jJ_etBit
Definition: FEXAlgoSpaceDefs.h:119
LVL1::jFEXFPGA::m_l1MenuKey
SG::ReadHandleKey< TrigConf::L1Menu > m_l1MenuKey
Definition: jFEXFPGA.h:140
TrigConf::L1ThrExtraInfo_jJ::seedThresholdMeV
unsigned int seedThresholdMeV(const std::string &module) const
Definition: L1ThrExtraInfo.h:414
LVL1::jFEXFPGA::m_LRJetET
int m_LRJetET
Definition: jFEXFPGA.h:135
LVL1::FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width
constexpr static int jFEX_thin_algoSpace_width
Definition: FEXAlgoSpaceDefs.h:26
LVL1::jFEXFPGA::m_jTowerContainerKey
SG::ReadHandleKey< LVL1::jTowerContainer > m_jTowerContainerKey
Definition: jFEXFPGA.h:139
TrigConf::L1ThrExtraInfo_jEM::isolation
const WorkingPoints_jEM & isolation(TrigConf::Selection::WP wp, int eta) const
Definition: L1ThrExtraInfo.h:215
LVL1::jFEXFPGA::m_jFEXtauAlgoTool
ToolHandle< IjFEXtauAlgo > m_jFEXtauAlgoTool
Definition: jFEXFPGA.h:143
xAOD::uint32_t
setEventNumber uint32_t
Definition: EventInfo_v1.cxx:127
SG::ReadHandle
Definition: StoreGate/StoreGate/ReadHandle.h:70
AthCommonDataStore::declareProperty
Gaudi::Details::PropertyBase & declareProperty(Gaudi::Property< T > &t)
Definition: AthCommonDataStore.h:145
LVL1::jFEXFPGA::m_jfex_string
std::string m_jfex_string[6]
Definition: jFEXFPGA.h:152
TrigConf::L1ThrExtraInfo_jTE
Definition: L1ThrExtraInfo.h:554
LVL1::jFEXFPGA::m_jFEXSmallRJetAlgoTool
ToolHandle< IjFEXSmallRJetAlgo > m_jFEXSmallRJetAlgoTool
Definition: jFEXFPGA.h:141
conifer::pow
constexpr int pow(int x)
Definition: conifer.h:20
skel.it
it
Definition: skel.GENtoEVGEN.py:396
TrigConf::L1ThrExtraInfo_jJ::ptMinToTopoMeV
unsigned int ptMinToTopoMeV(const std::string &module) const
Definition: L1ThrExtraInfo.h:398
AthCommonDataStore< AthCommonMsg< AlgTool > >::m_evtStore
StoreGateSvc_t m_evtStore
Pointer to StoreGate (event store by default)
Definition: AthCommonDataStore.h:390
AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
std::vector< SG::VarHandleKeyArray * > m_vhka
Definition: AthCommonDataStore.h:398
LVL1::jFEXFPGA::m_Met_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_Met_tobwords
Definition: jFEXFPGA.h:115
LVL1::jFEXFPGA::m_sumET_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_sumET_tobwords
Definition: jFEXFPGA.h:114
LVL1::FEXAlgoSpaceDefs::jFEX_algoSpace_height
constexpr static int jFEX_algoSpace_height
Definition: FEXAlgoSpaceDefs.h:27
read_hist_ntuple.t
t
Definition: read_hist_ntuple.py:5
LVL1::jFEXFPGA::getTTowerET_HAD
int getTTowerET_HAD(unsigned int TTID) override
Definition: jFEXFPGA.cxx:643
SG::VarHandleKey::key
const std::string & key() const
Return the StoreGate ID for the referenced object.
Definition: AthToolSupport/AsgDataHandles/Root/VarHandleKey.cxx:141
python.utils.AtlRunQueryLookup.mask
string mask
Definition: AtlRunQueryLookup.py:460
SG::VarHandleKeyArray::setOwner
virtual void setOwner(IDataHandleHolder *o)=0
LVL1::jFEXFPGA::m_jFEXForwardJetsAlgoTool
ToolHandle< IjFEXForwardJetsAlgo > m_jFEXForwardJetsAlgoTool
Definition: jFEXFPGA.h:146
IDTPMcnv.htype
htype
Definition: IDTPMcnv.py:27
TrigConf::L1ThrExtraInfo_jXE
Definition: L1ThrExtraInfo.h:542
LVL1::jFEXFPGA::m_SRJet_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_SRJet_tobwords
Definition: jFEXFPGA.h:112
LVL1::jFEXFPGA::m_tau_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_tau_tobwords
Definition: jFEXFPGA.h:111
uint
unsigned int uint
Definition: LArOFPhaseFill.cxx:20
TrigConf::L1ThrExtraInfo_jTAU::ptMinToTopoMeV
unsigned int ptMinToTopoMeV(const std::string &module) const
Definition: L1ThrExtraInfo.h:320
beamspotnt.cols
list cols
Definition: bin/beamspotnt.py:1114
LVL1::jFEXFPGA::m_jTowersIDs_Wide
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Definition: jTower.h:40
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