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LVL1::jFEXFPGA Class Reference

The jFEXFPGA class defines the structure of a single jFEX FPGA Its purpose is: More...

#include <jFEXFPGA.h>

Inheritance diagram for LVL1::jFEXFPGA:
Collaboration diagram for LVL1::jFEXFPGA:

Public Member Functions

 jFEXFPGA (const std::string &type, const std::string &name, const IInterface *parent)
 Constructors.
virtual StatusCode initialize () override
 standard Athena-Algorithm method
virtual ~jFEXFPGA ()
 Destructor.
virtual StatusCode init (int id, int efexid) override
virtual StatusCode execute (jFEXOutputCollection *inputOutputCollection, const std::pair< unsigned int, const std::vector< int > & > &jetCalibrationParameters) override
virtual void reset () override
virtual int ID () const override
virtual void SetTowersAndCells_SG (int[][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]) override
virtual void SetTowersAndCells_SG (int[][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]) override
virtual std::vector< std::unique_ptr< jFEXTOB > > getSmallRJetTOBs () override
 Form a tob word out of the potential candidate SmallRJet tob.
virtual std::vector< std::unique_ptr< jFEXTOB > > getLargeRJetTOBs () override
virtual std::vector< std::vector< uint32_t > > getFwdElTOBs () override
 sorted Electron tobs
virtual std::vector< std::unique_ptr< jFEXTOB > > getTauTOBs () override
virtual std::vector< std::unique_ptr< jFEXTOB > > getSumEtTOBs () override
 Form a tob word out of the potential candidate SumET tob.
virtual std::vector< std::unique_ptr< jFEXTOB > > getMetTOBs () override
 Form a tob word out of the potential candidate MET tob.
int getTTowerET_EM (unsigned int TTID) const override
int getTTowerET_HAD (unsigned int TTID) const override
int getTTowerET (unsigned int TTID) const override
int getTTowerET_forMET (unsigned int TTID) const override
ServiceHandle< StoreGateSvc > & evtStore ()
 The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.
const ServiceHandle< StoreGateSvc > & detStore () const
 The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.
virtual StatusCode sysInitialize () override
 Perform system initialization for an algorithm.
virtual StatusCode sysStart () override
 Handle START transition.
virtual std::vector< Gaudi::DataHandle * > inputHandles () const override
 Return this algorithm's input handles.
virtual std::vector< Gaudi::DataHandle * > outputHandles () const override
 Return this algorithm's output handles.
Gaudi::Details::PropertyBase & declareProperty (Gaudi::Property< T, V, H > &t)
void updateVHKA (Gaudi::Details::PropertyBase &)
MsgStream & msg () const
bool msgLvl (const MSG::Level lvl) const

Static Public Member Functions

static const InterfaceID & interfaceID ()

Protected Member Functions

void renounceArray (SG::VarHandleKeyArray &handlesArray)
 remove all handles from I/O resolution
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > renounce (T &h)
void extraDeps_update_handler (Gaudi::Details::PropertyBase &ExtraDeps)
 Add StoreName to extra input/output deps as needed.

Private Types

typedef ServiceHandle< StoreGateSvc > StoreGateSvc_t

Private Member Functions

int getTTowerET_SG (unsigned int TTID)
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyType &)
 specialization for handling Gaudi::Property<SG::VarHandleKey>

Static Private Member Functions

template<class TOBObjectClass>
static bool TOBetSort (const TOBObjectClass &i, const TOBObjectClass &j, uint bits, uint mask)
 Internal data.
static bool etFwdElSort (const std::vector< uint32_t > &i, const std::vector< uint32_t > &j)

Private Attributes

std::vector< std::unique_ptr< jFEXTOB > > m_tau_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_SRJet_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_LRJet_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_sumET_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_Met_tobwords
int m_id {}
int m_jfexid {}
std::vector< std::vector< uint32_t > > m_FwdEl_tobwords
int m_jTowersIDs_Wide [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}}
int m_jTowersIDs_Thin [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}}
std::unordered_map< int, std::vector< int > > m_map_HAD_Etvalues_FPGA
std::unordered_map< int, std::vector< int > > m_map_EM_Etvalues_FPGA
SG::ReadHandleKey< LVL1::jTowerContainer > m_jTowerContainerKey {this, "MyETowers", "jTowerContainer", "Input container for jTowers"}
SG::ReadHandleKey< TrigConf::L1Menu > m_l1MenuKey {this, "L1TriggerMenu", "DetectorStore+L1TriggerMenu","Name of the L1Menu object to read configuration from"}
ToolHandle< IjFEXSmallRJetAlgo > m_jFEXSmallRJetAlgoTool {this, "jFEXSmallRJetAlgoTool", "LVL1::jFEXSmallRJetAlgo", "Tool that runs the jFEX Small R Jet algorithm"}
ToolHandle< IjFEXLargeRJetAlgo > m_jFEXLargeRJetAlgoTool {this, "jFEXLargeRJetAlgoTool", "LVL1::jFEXLargeRJetAlgo", "Tool that runs the jFEX Large R Jet algorithm"}
ToolHandle< IjFEXtauAlgo > m_jFEXtauAlgoTool {this, "jFEXtauAlgoTool" , "LVL1::jFEXtauAlgo" , "Tool that runs the jFEX tau algorithm"}
ToolHandle< IjFEXsumETAlgo > m_jFEXsumETAlgoTool {this, "jFEXsumETAlgoTool" , "LVL1::jFEXsumETAlgo" , "Tool that runs the jFEX sumET algorithm"}
ToolHandle< IjFEXmetAlgo > m_jFEXmetAlgoTool {this, "jFEXmetAlgoTool" , "LVL1::jFEXmetAlgo" , "Tool that runs the jFEX met algorithm"}
ToolHandle< IjFEXForwardJetsAlgo > m_jFEXForwardJetsAlgoTool {this, "jFEXForwardJetsAlgoTool" , "LVL1::jFEXForwardJetsAlgo" , "Tool that runs the jFEX FCAL Jets algorithm"}
ToolHandle< IjFEXForwardElecAlgo > m_jFEXForwardElecAlgoTool {this, "jFEXForwardElecAlgoTool" , "LVL1::jFEXForwardElecAlgo" , "Tool that runs the jFEX FCAL Electrons algorithm"}
ToolHandle< IjFEXPileupAndNoise > m_jFEXPileupAndNoiseTool {this, "jFEXPileupAndNoiseTool", "LVL1::jFEXPileupAndNoise", "Tool that applies Pileup and Noise"}
ToolHandle< IjFEXFormTOBs > m_IjFEXFormTOBsTool {this, "IjFEXFormTOBsTool", "LVL1::jFEXFormTOBs", "Tool that forms TOB words"}
std::string m_jfex_string [6] = {"1C","2C","3C","3A","2A","1A"}
StoreGateSvc_t m_evtStore
 Pointer to StoreGate (event store by default).
StoreGateSvc_t m_detStore
 Pointer to StoreGate (detector store by default).
std::vector< SG::VarHandleKeyArray * > m_vhka
bool m_varHandleArraysDeclared

Detailed Description

The jFEXFPGA class defines the structure of a single jFEX FPGA Its purpose is:

  • to emulate the steps taken in processing data for a single jFEX FPGA in hardware and firmware
  • It will need to interact with jTowers and produce the jTOBs. It will be created and handed data by jFEXSim

Definition at line 50 of file jFEXFPGA.h.

Member Typedef Documentation

◆ StoreGateSvc_t

typedef ServiceHandle<StoreGateSvc> AthCommonDataStore< AthCommonMsg< AlgTool > >::StoreGateSvc_t
privateinherited

Definition at line 388 of file AthCommonDataStore.h.

Constructor & Destructor Documentation

◆ jFEXFPGA()

LVL1::jFEXFPGA::jFEXFPGA ( const std::string & type,
const std::string & name,
const IInterface * parent )

Constructors.

Definition at line 36 of file jFEXFPGA.cxx.

36 : AthAlgTool(type,name,parent) {
37 declareInterface<IjFEXFPGA>(this);
38}
AthAlgTool::AthAlgTool
AthAlgTool()
Default constructor:

◆ ~jFEXFPGA()

LVL1::jFEXFPGA::~jFEXFPGA ( )
virtual

Destructor.

Definition at line 41 of file jFEXFPGA.cxx.

42{
43}

Member Function Documentation

◆ declareGaudiProperty()

Gaudi::Details::PropertyBase & AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T, V, H > & hndl,
const SG::VarHandleKeyType &  )
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKey>

Definition at line 156 of file AthCommonDataStore.h.

158 {
159 return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
160 hndl.value(),
161 hndl.documentation());
162
163 }
AthCommonDataStore::declareProperty
Gaudi::Details::PropertyBase & declareProperty(Gaudi::Property< T, V, H > &t)
Definition AthCommonDataStore.h:145

◆ declareProperty()

Gaudi::Details::PropertyBase & AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( Gaudi::Property< T, V, H > & t)
inlineinherited

Definition at line 145 of file AthCommonDataStore.h.

145 {
146 typedef typename SG::HandleClassifier<T>::type htype;
147 return AthCommonDataStore<PBASE>::declareGaudiProperty(t, htype());
148 }
AthCommonDataStore::declareGaudiProperty
Gaudi::Details::PropertyBase & declareGaudiProperty(Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyType &)
specialization for handling Gaudi::Property<SG::VarHandleKey>
Definition AthCommonDataStore.h:156

◆ detStore()

const ServiceHandle< StoreGateSvc > & AthCommonDataStore< AthCommonMsg< AlgTool > >::detStore ( ) const
inlineinherited

The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 95 of file AthCommonDataStore.h.

95{ return m_detStore; }

◆ etFwdElSort()

bool LVL1::jFEXFPGA::etFwdElSort ( const std::vector< uint32_t > & i,
const std::vector< uint32_t > & j )
inlinestaticprivate

Definition at line 100 of file jFEXFPGA.h.

100{ return (((i.at(0) >> FEXAlgoSpaceDefs::jEM_etBit ) & 0x7ff )> ((j.at(0) >> FEXAlgoSpaceDefs::jEM_etBit) & 0x7ff ));}
LVL1::FEXAlgoSpaceDefs::jEM_etBit
static constexpr int jEM_etBit
Definition FEXAlgoSpaceDefs.h:113
TauHitVars::j
float j(const xAOD::IParticle &, const xAOD::TrackMeasurementValidation &hit, const Eigen::Matrix3d &jab_inv)
Definition ConstituentLoaderTauHit.cxx:102

◆ evtStore()

ServiceHandle< StoreGateSvc > & AthCommonDataStore< AthCommonMsg< AlgTool > >::evtStore ( )
inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 85 of file AthCommonDataStore.h.

85{ return m_evtStore; }

◆ execute()

StatusCode LVL1::jFEXFPGA::execute ( jFEXOutputCollection * inputOutputCollection,
const std::pair< unsigned int, const std::vector< int > & > & jetCalibrationParameters )
overridevirtual

Retrieve the L1 menu configuration

Implements LVL1::IjFEXFPGA.

Definition at line 77 of file jFEXFPGA.cxx.

77 {
78
79 // Retrieve the L1 menu configuration
80 SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
81
82 const TrigConf::L1ThrExtraInfo_jTAU & thr_jTAU = l1Menu->thrExtraInfo().jTAU();
83 const TrigConf::L1ThrExtraInfo_jJ & thr_jJ = l1Menu->thrExtraInfo().jJ();
84 const TrigConf::L1ThrExtraInfo_jLJ & thr_jLJ = l1Menu->thrExtraInfo().jLJ();
85 const TrigConf::L1ThrExtraInfo_jTE & thr_jTE = l1Menu->thrExtraInfo().jTE();
86 const TrigConf::L1ThrExtraInfo_jXE & thr_jXE = l1Menu->thrExtraInfo().jXE();
87
88 SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey/*,ctx*/);
89 if(!jTowerContainer.isValid()) {
90 ATH_MSG_ERROR("Could not retrieve container " << m_jTowerContainerKey.key() );
91 return StatusCode::FAILURE;
92 }
93
94 ATH_CHECK( m_jFEXPileupAndNoiseTool->safetyTest());
95 ATH_CHECK( m_jFEXPileupAndNoiseTool->reset());
96 if(m_jfexid == 0 || m_jfexid == 5) {
97 m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Wide);
98 }
99 else {
100 m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Thin);
101 }
102
103 //Calculating and sustracting pileup
104 const std::vector<int> pileup_rho = m_jFEXPileupAndNoiseTool->CalculatePileup();
105
106 //From the DB
107 ATH_CHECK(m_jFEXPileupAndNoiseTool->ApplyPileup());
108
109 //Noise should be always applied
110 m_jFEXPileupAndNoiseTool->ApplyNoise2Jets(true);
111 m_jFEXPileupAndNoiseTool->ApplyNoise2Met(true);
112 //Getting the values
113 m_map_HAD_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_HAD_Et_values();
114 m_map_EM_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_EM_Et_values();
115 std::unordered_map<int,std::vector<int> > map_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->GetEt_values();
116 std::vector<int> pileup_ID;
117 std::vector<int> pileup_HAD_jet;
118 std::vector<int> pileup_EM_jet;
119 std::vector<int> pileup_Total_jet;
120 std::vector<int> pileup_HAD_met;
121 std::vector<int> pileup_EM_met;
122 std::vector<int> pileup_Total_met;
123 for (auto const& [key, val] : m_map_HAD_Etvalues_FPGA)
124 {
125 pileup_ID.push_back(key);
126 pileup_HAD_jet.push_back(val[0]);
127 pileup_EM_jet.push_back(m_map_EM_Etvalues_FPGA[key][0]);
128 pileup_Total_jet.push_back(map_Etvalues_FPGA[key][0]);
129 pileup_HAD_met.push_back(val[1]);
130 pileup_EM_met.push_back(m_map_EM_Etvalues_FPGA[key][1]);
131 pileup_Total_met.push_back(map_Etvalues_FPGA[key][1]);
132 }
133
134 //saving pileup information
135 inputOutputCollection->addValue_pileup("pileup_FPGAid", m_id);
136 inputOutputCollection->addValue_pileup("pileup_jFEXid", m_jfexid);
137 inputOutputCollection->addValue_pileup("pileup_rho_EM", pileup_rho[0]);
138 inputOutputCollection->addValue_pileup("pileup_rho_HAD1", pileup_rho[1]);
139 inputOutputCollection->addValue_pileup("pileup_rho_HAD2", pileup_rho[2]);
140 inputOutputCollection->addValue_pileup("pileup_rho_HAD3", pileup_rho[3]);
141 inputOutputCollection->addValue_pileup("pileup_rho_FCAL", pileup_rho[4]);
142 inputOutputCollection->addValue_pileup("pileup_map_ID" , std::move(pileup_ID));
143 inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_jet" , std::move(pileup_HAD_jet));
144 inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_jet" , std::move(pileup_EM_jet));
145 inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_jet", std::move(pileup_Total_jet));
146 inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_met" , std::move(pileup_HAD_met));
147 inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_met" , std::move(pileup_EM_met));
148 inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_met", std::move(pileup_Total_met));
149 inputOutputCollection->fill_pileup();
150
151 if(m_id==0 || m_id==3) {
152 ATH_CHECK( m_jFEXsumETAlgoTool->safetyTest());
153 ATH_CHECK( m_jFEXsumETAlgoTool->reset());
154 ATH_CHECK( m_jFEXmetAlgoTool->safetyTest());
155 ATH_CHECK( m_jFEXmetAlgoTool->reset());
156
157 m_jFEXsumETAlgoTool->setFPGAEnergy(map_Etvalues_FPGA);
158 m_jFEXmetAlgoTool->setFPGAEnergy(map_Etvalues_FPGA);
159
160 unsigned int bin_pos = thr_jTE.etaBoundary_fw(m_jfex_string[m_jfexid]);
161
162 std::unique_ptr<jFEXTOB> jXE_tob = std::make_unique<jFEXTOB>();
163 uint32_t jXE_tobword = 0;
164
165 std::unique_ptr<jFEXTOB> jTE_tob = std::make_unique<jFEXTOB>();
166 uint32_t jTE_tobword = 0;
167
168
169 int hemisphere = m_id == 0 ? 1 : -1;
170
171 if(m_jfexid > 0 && m_jfexid < 5) {
172
173 //-----------------jFEXsumETAlgo-----------------
174 m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Thin);
175 m_jFEXsumETAlgoTool->buildBarrelSumET();
176
177 //-----------------jFEXmetAlgo-----------------
178 m_jFEXmetAlgoTool->setup(m_jTowersIDs_Thin, hemisphere);
179 m_jFEXmetAlgoTool->buildBarrelmet();
180 }
181 else if(m_jfexid == 0 ) {
182
183 int flipped_jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}};
184 int max_phi_it = FEXAlgoSpaceDefs::jFEX_algoSpace_height-1;
185 int max_eta_it = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-1;
186 for(int mphi = 0; mphi <= max_phi_it; mphi++) {
187 for(int meta = 0; meta <= max_eta_it; meta++) {
188 flipped_jTowersIDs[mphi][meta]=m_jTowersIDs_Wide[mphi][max_eta_it-meta];
189 }
190 }
191 //-----------------jFEXsumETAlgo-----------------
192 m_jFEXsumETAlgoTool->setup(flipped_jTowersIDs);
193 m_jFEXsumETAlgoTool->buildFWDSumET();
194
195 //-----------------jFEXmetAlgo-----------------
196 m_jFEXmetAlgoTool->setup(flipped_jTowersIDs, hemisphere);
197 m_jFEXmetAlgoTool->buildFWDmet();
198 }
199 else if(m_jfexid == 5) {
200
201 //-----------------jFEXsumETAlgo-----------------
202 m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Wide);
203 m_jFEXsumETAlgoTool->buildFWDSumET();
204
205 //-----------------jFEXmetAlgo-----------------
206 m_jFEXmetAlgoTool->setup(m_jTowersIDs_Wide, hemisphere);
207 m_jFEXmetAlgoTool->buildFWDmet();
208 }
209
210 jXE_tobword = m_IjFEXFormTOBsTool->formMetTOB(m_jFEXmetAlgoTool->GetMetXComponent(), m_jFEXmetAlgoTool->GetMetYComponent(),m_jFEXmetAlgoTool->getjXESat(),thr_jXE.resolutionMeV());
211 jXE_tob->initialize(m_id,m_jfexid,jXE_tobword,thr_jXE.resolutionMeV(),0);
212 m_Met_tobwords.push_back(std::move(jXE_tob));
213
214 std::tuple<int,bool> jTElow;
215 std::tuple<int,bool> jTEhigh;
216
217 // NOTE: Foward FPGA in the C-side is already flipped, however we still need to flip the jFEX module 1 and 2
218 if(m_jfexid == 1 || m_jfexid == 2){
219 jTElow = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
220 jTEhigh = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
221 }
222 else{
223 jTElow = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
224 jTEhigh = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
225 }
226
227 jTE_tobword = m_IjFEXFormTOBsTool->formSumETTOB(jTElow,jTEhigh,thr_jTE.resolutionMeV());
228 jTE_tob->initialize(m_id,m_jfexid,jTE_tobword,thr_jTE.resolutionMeV(),0);
229 m_sumET_tobwords.push_back(std::move(jTE_tob));
230 }
231
232 //-----------jFEXSmallRJet & Large R Jet Algo-----------------
233 ATH_MSG_DEBUG("================ Central Algorithms ================");
234
235 int srJet_seedThresholdMeV = thr_jJ.seedThresholdMeV(m_jfex_string[m_jfexid]); //jFEX internal granularity, i.e., 25 MeV/count
236
237
238 //Central region algorithms
239 if(m_jfexid > 0 && m_jfexid < 5) {
240 m_jFEXSmallRJetAlgoTool->setFPGAEnergy(map_Etvalues_FPGA);
241 if(!m_jFEXLargeRJetAlgoTool.empty()) m_jFEXLargeRJetAlgoTool->setFPGAEnergy(map_Etvalues_FPGA);
242 m_jFEXtauAlgoTool->setFPGAEnergy(map_Etvalues_FPGA);
243
244 for(int mphi = 8; mphi < FEXAlgoSpaceDefs::jFEX_algoSpace_height-8; mphi++) {
245 for(int meta = 8; meta < FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width-8; meta++) {
246
247 //definition of arrays
248 int TT_seed_ID[3][3]= {{0}};
249 int TT_First_ETring[36]= {0};
250 int First_ETring_it = 0;
251
252 int Jet_SearchWindow[7][7] = {{0}};
253 int Jet_SearchWindowDisplaced[7][7] = {{0}};
254 int largeRCluster_IDs[15][15]= {{0}};
255
256 //filling up array to send them to the algorithms
257 for(int i = -7; i< 8; i++ ) {
258 for(int j = -7; j< 8; j++) {
259
260 if(std::abs(i)<4 && std::abs(j)<4) {
261 Jet_SearchWindow[3 + i][3 + j] = m_jTowersIDs_Thin[mphi + i][meta +j];
262 Jet_SearchWindowDisplaced[3 + i][3 + j] = m_jTowersIDs_Thin[mphi+i+1][meta+j+1];
263 }
264
265 uint deltaR = std::sqrt(std::pow(i,2)+std::pow(j,2));
266
267 if(deltaR<2) {
268 TT_seed_ID[i+1][j+1] = m_jTowersIDs_Thin[mphi +i][meta +j]; // Seed 0.3x0.3 in phi-eta plane
269 }
270 else if(deltaR<4) {
271 TT_First_ETring[First_ETring_it]= m_jTowersIDs_Thin[mphi +i][meta +j]; // First energy ring, will be used as tau ISO
272 ++First_ETring_it;
273
274 }
275 else if(deltaR<8) {
276 largeRCluster_IDs[7 +i][7 +j] = m_jTowersIDs_Thin[mphi + i][meta +j];
277 }
278 }
279 }
280
281 // ******** jJ and jLJ algorithms ********
282 ATH_CHECK( m_jFEXSmallRJetAlgoTool->safetyTest());
283 if(!m_jFEXLargeRJetAlgoTool.empty()) ATH_CHECK( m_jFEXLargeRJetAlgoTool->safetyTest());
284 m_jFEXSmallRJetAlgoTool->setup(Jet_SearchWindow, Jet_SearchWindowDisplaced);
285 if(!m_jFEXLargeRJetAlgoTool.empty()) m_jFEXLargeRJetAlgoTool->setupCluster(largeRCluster_IDs);
286 m_jFEXSmallRJetAlgoTool->buildSeeds();
287
288 bool is_Jet_LM = m_jFEXSmallRJetAlgoTool->isSeedLocalMaxima(srJet_seedThresholdMeV);
289
290 if(is_Jet_LM) {
291
292 //getting the energies
293 int SRj_Et = m_jFEXSmallRJetAlgoTool->getSmallClusterET();
294 int LRj_Et = (m_jFEXLargeRJetAlgoTool.empty()) ? 0 : m_jFEXLargeRJetAlgoTool->getLargeClusterET(SRj_Et,m_jFEXLargeRJetAlgoTool->getRingET());
295 int seed_Et = m_jFEXSmallRJetAlgoTool->getSeedET();
296
297 bool SRj_Sat = m_jFEXSmallRJetAlgoTool->getSRjetSat();
298 bool LRj_Sat = (m_jFEXLargeRJetAlgoTool.empty()) ? false : (SRj_Sat || m_jFEXLargeRJetAlgoTool->getLRjetSat());
299
300 int meta_LM = meta;
301 int mphi_LM = mphi;
302
303
304 //Creating SR TOB
305 uint32_t SRJet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, mphi_LM, meta_LM, SRj_Et, SRj_Sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
306
307 std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
308 jJ_tob->initialize(m_id,m_jfexid,SRJet_tobword,thr_jJ.resolutionMeV(),m_jTowersIDs_Thin[mphi_LM][meta_LM],seed_Et);
309 if ( SRJet_tobword != 0 ){
310 m_SRJet_tobwords.push_back(std::move(jJ_tob));
311 }
312
313 //Creating LR TOB
314 if(!m_jFEXLargeRJetAlgoTool.empty()) {
315 uint32_t LRJet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, mphi_LM, meta_LM, LRj_Et,
316 LRj_Sat, thr_jLJ.resolutionMeV(),
317 thr_jLJ.ptMinToTopoMeV(
318 m_jfex_string[m_jfexid]));
319
320 std::unique_ptr <jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
321 jLJ_tob->initialize(m_id, m_jfexid, LRJet_tobword, thr_jLJ.resolutionMeV(),
322 m_jTowersIDs_Thin[mphi_LM][meta_LM], seed_Et);
323 if (LRJet_tobword != 0) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
324 }
325 }
326 // ******** jTau algorithm ********
327
328 ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
329 m_jFEXtauAlgoTool->setup(TT_seed_ID);
330 bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima();
331
332 // Save TOB is tau is a local maxima
333 if ( is_tau_LocalMax ) {
334
335 //calculates the 1st energy ring
336 m_jFEXtauAlgoTool->setFirstEtRing(TT_First_ETring);
337
338
339 uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
340
341 std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
342 jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),m_jTowersIDs_Thin[mphi][meta]);
343
344 if ( jTau_tobword != 0 ){
345 m_tau_tobwords.push_back(std::move(jTau_tob));
346 }
347 }
348 }
349 }
350 } //end of if statement for checking if in central jfex modules
351
352 //FCAL region algorithm
353 if(m_jfexid ==0 || m_jfexid ==5) {
354
355 //**********Forward Jets***********************
356 ATH_CHECK(m_jFEXForwardJetsAlgoTool->safetyTest());
357 ATH_CHECK(m_jFEXForwardJetsAlgoTool->reset());
358 m_jFEXForwardJetsAlgoTool->setFPGAEnergy(map_Etvalues_FPGA);
359 m_jFEXForwardJetsAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid);
360
361 std::unordered_map<int, jFEXForwardJetsInfo> FCALJets = m_jFEXForwardJetsAlgoTool->calculateJetETs(srJet_seedThresholdMeV);
362 for(std::unordered_map<int, jFEXForwardJetsInfo>::iterator it = FCALJets.begin(); it!=FCALJets.end(); ++it) {
363
364 uint32_t TTID = it->first;
365 jFEXForwardJetsInfo FCALJets = it->second;
366
367 int iphi = FCALJets.getCentreLocalTTPhi();
368 int ieta = FCALJets.getCentreLocalTTEta();
369 int SRJetET = FCALJets.getSeedET() + FCALJets.getFirstEnergyRingET();
370 int LRJetET = SRJetET + FCALJets.getSecondEnergyRingET();
371 int seedET = FCALJets.getSeedET();
372
373 bool SRJ_sat = FCALJets.getSRjetSat();
374
375 uint32_t SRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, iphi, ieta, SRJetET, SRJ_sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
376
377 std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
378 jJ_tob->initialize(m_id,m_jfexid,SRFCAL_Jet_tobword,thr_jJ.resolutionMeV(),TTID,seedET);
379
380 if ( SRFCAL_Jet_tobword != 0 ){
381 m_SRJet_tobwords.push_back(std::move(jJ_tob));
382 }
383
384 if(std::fabs(FCALJets.getCentreTTEta())<2.51 && !m_jFEXLargeRJetAlgoTool.empty()){
385 bool LRJ_sat = FCALJets.getLRjetSat();
386 uint32_t LRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, iphi, ieta, LRJetET, LRJ_sat, thr_jLJ.resolutionMeV(),thr_jLJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
387
388 std::unique_ptr<jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
389 jLJ_tob->initialize(m_id,m_jfexid,LRFCAL_Jet_tobword,thr_jLJ.resolutionMeV(),TTID);
390 if ( LRFCAL_Jet_tobword != 0 ) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
391 }
392
393 }
394 //********** Forward Electrons ***********************
395 ATH_CHECK(m_jFEXForwardElecAlgoTool->safetyTest());
396 ATH_CHECK(m_jFEXForwardElecAlgoTool->reset());
397 m_jFEXForwardElecAlgoTool->setFPGAEnergy(m_map_EM_Etvalues_FPGA,m_map_HAD_Etvalues_FPGA);
398 m_jFEXForwardElecAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid,m_id);
399 std::unordered_map<uint, jFEXForwardElecInfo> ForwardElecs = m_jFEXForwardElecAlgoTool->calculateEDM();
400
402 SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
403 const TrigConf::L1ThrExtraInfo_jEM & thr_jEM = l1Menu->thrExtraInfo().jEM();
404 const uint jFEXETResolution = thr_jEM.resolutionMeV();//200
405 std::string str_jfexname = m_jfex_string[m_jfexid];
406 uint minEtThreshold = thr_jEM.ptMinToTopoMeV(str_jfexname)/jFEXETResolution;
407 //uint Cval[9] = {1,2,3,20,30,40,20,30,40};//C values for iso, emfr1 and emfr2
408 std::vector<int> Ciso;
409 std::vector<int> Chad1;
410 std::vector<int> Chad2;
411
412 for(std::unordered_map<uint, jFEXForwardElecInfo>::iterator itel = ForwardElecs.begin(); itel!=ForwardElecs.end(); ++itel) {
413 uint32_t TTID = itel->first;
414 jFEXForwardElecInfo elCluster = itel->second;
415 uint meta = elCluster.getCoreIeta();//check whether this is the one used by the Trigger conf
416
417 //retrieve jet rejection thresholds from trigger configuration
418 const auto & wp_loose = thr_jEM.isolation(TrigConf::Selection::WP::LOOSE, meta);
419 const auto & wp_medium = thr_jEM.isolation(TrigConf::Selection::WP::MEDIUM, meta);
420 const auto & wp_tight = thr_jEM.isolation(TrigConf::Selection::WP::TIGHT, meta);
421 Ciso.clear();
422 Chad1.clear();
423 Chad2.clear();
424 Ciso.push_back(wp_loose.iso_fw());
425 Ciso.push_back(wp_medium.iso_fw());
426 Ciso.push_back(wp_tight.iso_fw());
427 Chad1.push_back(wp_loose.frac_fw());
428 Chad1.push_back(wp_medium.frac_fw());
429 Chad1.push_back(wp_tight.frac_fw());
430 Chad2.push_back(wp_loose.frac2_fw());
431 Chad2.push_back(wp_medium.frac2_fw());
432 Chad2.push_back(wp_tight.frac2_fw());
433 int Cval[9] = {Ciso[0], Ciso[1], Ciso[2], Chad1[0], Chad1[1], Chad1[2], Chad2[0], Chad2[1], Chad2[2]};
434
435 elCluster.setup(Cval,jFEXETResolution);
436 elCluster.calcFwdElEDM();
437
438 uint etEM = elCluster.getEt();
439 uint32_t FwdEl_tobword = elCluster.getTobWord();
440
441
442 std::vector<uint32_t> FwdEltob_aux{FwdEl_tobword,TTID};
443 if ( FwdEl_tobword != 0 && etEM>minEtThreshold) m_FwdEl_tobwords.push_back(std::move(FwdEltob_aux));
444 }
445
446 //******************************** TAU **********************************************
447 int jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}};
448 int max_meta=17;
449
450 if(m_jfexid ==0) {
451 for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
452 for(int j=28; j<(FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-6); j++) { //lower values of j (j<28) are the Fcals not entering in the jFEX tau range
453 jTowersIDs[i][j-28+8]=m_jTowersIDs_Wide[i][j]; // second argument in m_jTowersIDs is to center the FPGA core area in te same region as the central FPGAs
454 }
455 }
456
457 }
458 else if(m_jfexid ==5 ) {
459
460 // Filling m_jTowersIDs with the m_jTowersIDs_Wide ID values up to 2.5 eta
461 for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
462 for(int j=4; j<17; j++) { //higher values of j (j>16) are the Fcals not entering in the jFEX tau range
463 jTowersIDs[i][j]=m_jTowersIDs_Wide[i][j];
464 }
465 }
466 }
467 ATH_MSG_DEBUG("============================ jFEXtauAlgo ============================");
468 ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
469 m_jFEXtauAlgoTool->setFPGAEnergy(map_Etvalues_FPGA);
470 for(int mphi = 8; mphi < 24; mphi++) {
471 for(int meta = 8; meta < max_meta; meta++) {
472
473 bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima_fwd(jTowersIDs[mphi][meta]);
474
475 // Save TOB is tau is a local maxima
476 if ( is_tau_LocalMax ) {
477
478 uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
479
480 std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
481 jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),jTowersIDs[mphi][meta]);
482 if ( jTau_tobword != 0 ){
483 m_tau_tobwords.push_back(std::move(jTau_tob));
484 }
485 }
486 }
487 }
488 } //end of if statement for checking if in central jfex modules
489 return StatusCode::SUCCESS;
490} //end of the execute function
deltaR
Scalar deltaR(const MatrixBase< Derived > &vec) const
Definition AmgMatrixBasePlugin.h:105
ATH_CHECK
#define ATH_CHECK
Evaluate an expression and check for errors.
Definition AthCheckMacros.h:40
ATH_MSG_ERROR
#define ATH_MSG_ERROR(x)
Definition AthMsgStreamMacros.h:33
ATH_MSG_DEBUG
#define ATH_MSG_DEBUG(x)
Definition AthMsgStreamMacros.h:29
uint
unsigned int uint
Definition LArOFPhaseFill.cxx:19
LVL1::FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width
static constexpr int jFEX_wide_algoSpace_width
Definition FEXAlgoSpaceDefs.h:27
LVL1::FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width
static constexpr int jFEX_thin_algoSpace_width
Definition FEXAlgoSpaceDefs.h:28
LVL1::FEXAlgoSpaceDefs::jFEX_algoSpace_height
static constexpr int jFEX_algoSpace_height
Definition FEXAlgoSpaceDefs.h:29
LVL1::jFEXFPGA::m_FwdEl_tobwords
std::vector< std::vector< uint32_t > > m_FwdEl_tobwords
Definition jFEXFPGA.h:111
LVL1::jFEXFPGA::m_jFEXSmallRJetAlgoTool
ToolHandle< IjFEXSmallRJetAlgo > m_jFEXSmallRJetAlgoTool
Definition jFEXFPGA.h:121
LVL1::jFEXFPGA::m_jfex_string
std::string m_jfex_string[6]
Definition jFEXFPGA.h:132
LVL1::jFEXFPGA::m_map_EM_Etvalues_FPGA
std::unordered_map< int, std::vector< int > > m_map_EM_Etvalues_FPGA
Definition jFEXFPGA.h:117
LVL1::jFEXFPGA::m_jFEXPileupAndNoiseTool
ToolHandle< IjFEXPileupAndNoise > m_jFEXPileupAndNoiseTool
Definition jFEXFPGA.h:128
LVL1::jFEXFPGA::m_jFEXForwardJetsAlgoTool
ToolHandle< IjFEXForwardJetsAlgo > m_jFEXForwardJetsAlgoTool
Definition jFEXFPGA.h:126
LVL1::jFEXFPGA::m_jFEXmetAlgoTool
ToolHandle< IjFEXmetAlgo > m_jFEXmetAlgoTool
Definition jFEXFPGA.h:125
LVL1::jFEXFPGA::m_tau_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_tau_tobwords
Definition jFEXFPGA.h:102
LVL1::jFEXFPGA::m_l1MenuKey
SG::ReadHandleKey< TrigConf::L1Menu > m_l1MenuKey
Definition jFEXFPGA.h:120
LVL1::jFEXFPGA::m_map_HAD_Etvalues_FPGA
std::unordered_map< int, std::vector< int > > m_map_HAD_Etvalues_FPGA
Definition jFEXFPGA.h:116
LVL1::jFEXFPGA::m_jTowersIDs_Thin
int m_jTowersIDs_Thin[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]
Definition jFEXFPGA.h:114
LVL1::jFEXFPGA::m_IjFEXFormTOBsTool
ToolHandle< IjFEXFormTOBs > m_IjFEXFormTOBsTool
Definition jFEXFPGA.h:129
LVL1::jFEXFPGA::m_sumET_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_sumET_tobwords
Definition jFEXFPGA.h:105
LVL1::jFEXFPGA::m_SRJet_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_SRJet_tobwords
Definition jFEXFPGA.h:103
LVL1::jFEXFPGA::m_jFEXsumETAlgoTool
ToolHandle< IjFEXsumETAlgo > m_jFEXsumETAlgoTool
Definition jFEXFPGA.h:124
LVL1::jFEXFPGA::m_jFEXtauAlgoTool
ToolHandle< IjFEXtauAlgo > m_jFEXtauAlgoTool
Definition jFEXFPGA.h:123
LVL1::jFEXFPGA::m_Met_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_Met_tobwords
Definition jFEXFPGA.h:106
LVL1::jFEXFPGA::m_LRJet_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_LRJet_tobwords
Definition jFEXFPGA.h:104
LVL1::jFEXFPGA::m_jTowerContainerKey
SG::ReadHandleKey< LVL1::jTowerContainer > m_jTowerContainerKey
Definition jFEXFPGA.h:119
LVL1::jFEXFPGA::m_jFEXLargeRJetAlgoTool
ToolHandle< IjFEXLargeRJetAlgo > m_jFEXLargeRJetAlgoTool
Definition jFEXFPGA.h:122
LVL1::jFEXFPGA::m_jTowersIDs_Wide
int m_jTowersIDs_Wide[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]
Definition jFEXFPGA.h:113
LVL1::jFEXFPGA::m_jFEXForwardElecAlgoTool
ToolHandle< IjFEXForwardElecAlgo > m_jFEXForwardElecAlgoTool
Definition jFEXFPGA.h:127
TrigConf::L1ThrExtraInfoBase::resolutionMeV
unsigned int resolutionMeV() const
Definition L1ThresholdBase.h:101
TrigConf::L1ThrExtraInfo_jEM::isolation
const WorkingPoints_jEM & isolation(TrigConf::Selection::WP wp, int eta) const
Definition L1ThrExtraInfo.h:221
TrigConf::L1ThrExtraInfo_jEM::ptMinToTopoMeV
unsigned int ptMinToTopoMeV(const std::string &module) const
Definition L1ThrExtraInfo.h:228
TrigConf::L1ThrExtraInfo_jJ::ptMinToTopoMeV
unsigned int ptMinToTopoMeV(const std::string &module) const
Definition L1ThrExtraInfo.h:404
TrigConf::L1ThrExtraInfo_jJ::seedThresholdMeV
unsigned int seedThresholdMeV(const std::string &module) const
Definition L1ThrExtraInfo.h:420
TrigConf::L1ThrExtraInfo_jLJ::ptMinToTopoMeV
unsigned int ptMinToTopoMeV(const std::string &module) const
Definition L1ThrExtraInfo.h:449
TrigConf::L1ThrExtraInfo_jTAU::ptMinToTopoMeV
unsigned int ptMinToTopoMeV(const std::string &module) const
Definition L1ThrExtraInfo.h:326
TrigConf::L1ThrExtraInfo_jTE::etaBoundary_fw
unsigned int etaBoundary_fw(const std::string &module) const
Definition L1ThrExtraInfo.h:566
xAOD::uint32_t
setEventNumber uint32_t
Definition EventInfo_v1.cxx:127

◆ extraDeps_update_handler()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::extraDeps_update_handler ( Gaudi::Details::PropertyBase & ExtraDeps)
protectedinherited

Add StoreName to extra input/output deps as needed.

use the logic of the VarHandleKey to parse the DataObjID keys supplied via the ExtraInputs and ExtraOuputs Properties to add the StoreName if it's not explicitly given

◆ getFwdElTOBs()

std::vector< std::vector< uint32_t > > LVL1::jFEXFPGA::getFwdElTOBs ( )
overridevirtual

sorted Electron tobs

Implements LVL1::IjFEXFPGA.

Definition at line 564 of file jFEXFPGA.cxx.

565 {
566 auto tobsSort = m_FwdEl_tobwords;
567
568 ATH_MSG_DEBUG("number of Forward Elec tobs: " << tobsSort.size() << " in FPGA: " << m_id<< " before truncation");
569 //sort tobs by their et
570 std::sort (tobsSort.begin(), tobsSort.end(), etFwdElSort);
571
572 return tobsSort;
573 }
LVL1::jFEXFPGA::etFwdElSort
static bool etFwdElSort(const std::vector< uint32_t > &i, const std::vector< uint32_t > &j)
Definition jFEXFPGA.h:100
std::sort
void sort(typename DataModel_detail::iterator< DVL > beg, typename DataModel_detail::iterator< DVL > end)
Specialization of sort for DataVector/List.
Definition DVL_algorithms.h:554

◆ getLargeRJetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getLargeRJetTOBs ( )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 550 of file jFEXFPGA.cxx.

551{
552 std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
553
554 // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
555 for(auto &j : m_LRJet_tobwords) {
556 tobsSort.push_back(std::move(j));
557 }
558 std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jLJ_etBit, 0x1fff));
559
560 return tobsSort;
561}
LVL1::FEXAlgoSpaceDefs::jLJ_etBit
static constexpr int jLJ_etBit
Definition FEXAlgoSpaceDefs.h:129
LVL1::jFEXFPGA::TOBetSort
static bool TOBetSort(const TOBObjectClass &i, const TOBObjectClass &j, uint bits, uint mask)
Internal data.
Definition jFEXFPGA.h:96

◆ getMetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getMetTOBs ( )
overridevirtual

Form a tob word out of the potential candidate MET tob.

Implements LVL1::IjFEXFPGA.

Definition at line 603 of file jFEXFPGA.cxx.

603 {
604
605 std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
606
607 // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
608 for(auto &j : m_Met_tobwords) {
609 tobsSort.push_back(std::move(j));
610 }
611
612 return tobsSort;
613}

◆ getSmallRJetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getSmallRJetTOBs ( )
overridevirtual

Form a tob word out of the potential candidate SmallRJet tob.

Implements LVL1::IjFEXFPGA.

Definition at line 537 of file jFEXFPGA.cxx.

538{
539 std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
540
541 // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
542 for(auto &j : m_SRJet_tobwords) {
543 tobsSort.push_back(std::move(j));
544 }
545 std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jJ_etBit, 0x7ff));
546
547 return tobsSort;
548}
LVL1::FEXAlgoSpaceDefs::jJ_etBit
static constexpr int jJ_etBit
Definition FEXAlgoSpaceDefs.h:121

◆ getSumEtTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getSumEtTOBs ( )
overridevirtual

Form a tob word out of the potential candidate SumET tob.

Implements LVL1::IjFEXFPGA.

Definition at line 589 of file jFEXFPGA.cxx.

589 {
590
591 std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
592
593 // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
594 for(auto &j : m_sumET_tobwords) {
595 tobsSort.push_back(std::move(j));
596 }
597
598 return tobsSort;
599}

◆ getTauTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXFPGA::getTauTOBs ( )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 576 of file jFEXFPGA.cxx.

576 {
577
578 std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
579
580 // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
581 for(auto &j : m_tau_tobwords) {
582 tobsSort.push_back(std::move(j));
583 }
584 std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jTau_etBit, 0x7ff));
585
586 return tobsSort;
587}
LVL1::FEXAlgoSpaceDefs::jTau_etBit
static constexpr int jTau_etBit
Definition FEXAlgoSpaceDefs.h:102

◆ getTTowerET()

int LVL1::jFEXFPGA::getTTowerET ( unsigned int TTID) const
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 641 of file jFEXFPGA.cxx.

641 {
642
643 return getTTowerET_EM(TTID)+getTTowerET_HAD(TTID);
644}
LVL1::jFEXFPGA::getTTowerET_HAD
int getTTowerET_HAD(unsigned int TTID) const override
Definition jFEXFPGA.cxx:629
LVL1::jFEXFPGA::getTTowerET_EM
int getTTowerET_EM(unsigned int TTID) const override
Definition jFEXFPGA.cxx:617

◆ getTTowerET_EM()

int LVL1::jFEXFPGA::getTTowerET_EM ( unsigned int TTID) const
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 617 of file jFEXFPGA.cxx.

617 {
618
619 if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
620 return m_map_EM_Etvalues_FPGA.at(TTID)[0];
621 }
622
623 ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_EM, TTower ID not found in map: " << TTID );
624 return -99999;
625}

◆ getTTowerET_forMET()

int LVL1::jFEXFPGA::getTTowerET_forMET ( unsigned int TTID) const
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 648 of file jFEXFPGA.cxx.

648 {
649
650 int tmp_EM = 0;
651 if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
652 tmp_EM = m_map_EM_Etvalues_FPGA.at(TTID)[1];
653 }
654 else{
655 ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (EM energy), TTower ID not found in map: " << TTID );
656 tmp_EM = -99999;
657 }
658
659
660 int tmp_HAD = 0;
661 if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
662 tmp_HAD = m_map_HAD_Etvalues_FPGA.at(TTID)[1];
663 }
664 else{
665 ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (HAD energy), TTower ID not found in map: " << TTID );
666 tmp_HAD = -99999;
667 }
668
669
670 return tmp_EM + tmp_HAD;
671}

◆ getTTowerET_HAD()

int LVL1::jFEXFPGA::getTTowerET_HAD ( unsigned int TTID) const
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 629 of file jFEXFPGA.cxx.

629 {
630
631 if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
632 return m_map_HAD_Etvalues_FPGA.at(TTID)[0];
633 }
634
635 ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_HAD, TTower ID not found in map: " << TTID );
636 return -99999;
637}

◆ getTTowerET_SG()

int LVL1::jFEXFPGA::getTTowerET_SG ( unsigned int TTID)
private

Definition at line 675 of file jFEXFPGA.cxx.

675 {
676
677 if(TTID == 0){
678 return -999;
679 }
680 SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey);
681 const LVL1::jTower * tmpTower = jTowerContainer->findTower(TTID);
682 return tmpTower->getTotalET();
683}
LVL1::jTower::getTotalET
int getTotalET() const
Get ET sum of all cells in the jTower in MeV.
Definition jTower.cxx:199

◆ ID()

virtual int LVL1::jFEXFPGA::ID ( ) const
inlineoverridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 67 of file jFEXFPGA.h.

67{return m_id;}

◆ init()

StatusCode LVL1::jFEXFPGA::init ( int id,
int efexid )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 55 of file jFEXFPGA.cxx.

55 {
56 m_id = id;
57 m_jfexid = jfexid;
58
59 return StatusCode::SUCCESS;
60
61}
Base_Fragment.id
id
Definition Sherpa_i/share/common/Base_Fragment.py:59

◆ initialize()

StatusCode LVL1::jFEXFPGA::initialize ( )
overridevirtual

standard Athena-Algorithm method

Definition at line 47 of file jFEXFPGA.cxx.

47 {
48
49 ATH_CHECK(m_jTowerContainerKey.initialize());
50 ATH_CHECK(m_l1MenuKey.initialize());
51 ATH_CHECK(m_jFEXtauAlgoTool.retrieve());
52 return StatusCode::SUCCESS;
53}

◆ inputHandles()

virtual std::vector< Gaudi::DataHandle * > AthCommonDataStore< AthCommonMsg< AlgTool > >::inputHandles ( ) const
overridevirtualinherited

Return this algorithm's input handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ interfaceID()

const InterfaceID & LVL1::IjFEXFPGA::interfaceID ( )
inlinestaticinherited

Definition at line 70 of file IjFEXFPGA.h.

71 {
72 return IID_IjFEXFPGA;
73 }
LVL1::IID_IjFEXFPGA
static const InterfaceID IID_IjFEXFPGA("LVL1::IjFEXFPGA", 1, 0)

◆ msg()

MsgStream & AthCommonMsg< AlgTool >::msg ( ) const
inlineinherited

Definition at line 24 of file AthCommonMsg.h.

24 {
25 return this->msgStream();
26 }

◆ msgLvl()

bool AthCommonMsg< AlgTool >::msgLvl ( const MSG::Level lvl) const
inlineinherited

Definition at line 30 of file AthCommonMsg.h.

30 {
31 return this->msgLevel(lvl);
32 }

◆ outputHandles()

virtual std::vector< Gaudi::DataHandle * > AthCommonDataStore< AthCommonMsg< AlgTool > >::outputHandles ( ) const
overridevirtualinherited

Return this algorithm's output handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ renounce()

std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > AthCommonDataStore< AthCommonMsg< AlgTool > >::renounce ( T & h)
inlineprotectedinherited

Definition at line 380 of file AthCommonDataStore.h.

381 {
382 h.renounce();
383 PBASE::renounce (h);
384 }
AthCommonDataStore::renounce
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > renounce(T &h)
Definition AthCommonDataStore.h:380

◆ renounceArray()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::renounceArray ( SG::VarHandleKeyArray & handlesArray)
inlineprotectedinherited

remove all handles from I/O resolution

Definition at line 364 of file AthCommonDataStore.h.

364 {
365 handlesArray.renounce();
366 }

◆ reset()

void LVL1::jFEXFPGA::reset ( )
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 63 of file jFEXFPGA.cxx.

63 {
64
65 m_id = -1;
66 m_jfexid = -1;
67 m_tau_tobwords.clear();
68 m_SRJet_tobwords.clear();
69 m_LRJet_tobwords.clear();
70 m_sumET_tobwords.clear();
71 m_Met_tobwords.clear();
72 m_map_EM_Etvalues_FPGA.clear();
73 m_map_HAD_Etvalues_FPGA.clear();
74 m_FwdEl_tobwords.clear();
75}

◆ SetTowersAndCells_SG() [1/2]

void LVL1::jFEXFPGA::SetTowersAndCells_SG ( int tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 512 of file jFEXFPGA.cxx.

512 {
513
514 const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
515 const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
516
517 std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Thin[0][0]);
518
519 if (msgLvl(MSG::DEBUG)) {
520 //this prints out the jTower IDs that each FPGA is responsible for
521 ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
522
523 for (int thisRow=rows-1; thisRow>=0; thisRow--) {
524 for (int thisCol=0; thisCol<cols; thisCol++) {
525 if(thisCol != cols-1) {
526 ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " ");
527 }
528 else {
529 ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " |");
530 }
531 }
532 }
533 }
534
535}
AthCommonMsg< AlgTool >::msgLvl
bool msgLvl(const MSG::Level lvl) const
Definition AthCommonMsg.h:30

◆ SetTowersAndCells_SG() [2/2]

void LVL1::jFEXFPGA::SetTowersAndCells_SG ( int tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXFPGA.

Definition at line 492 of file jFEXFPGA.cxx.

492 {
493
494 const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
495 const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
496
497 std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Wide[0][0]);
498
499 if (msgLvl(MSG::DEBUG)) {
500 ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
501
502 for (int thisRow=rows-1; thisRow>=0; thisRow--){
503 for (int thisCol=0; thisCol<cols; thisCol++){
504 if(thisCol != cols-1){ ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " "); }
505 else { ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " |"); }
506 }
507 }
508 }
509
510}

◆ sysInitialize()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysInitialize ( )
overridevirtualinherited

Perform system initialization for an algorithm.

We override this to declare all the elements of handle key arrays at the end of initialization. See comments on updateVHKA.

Reimplemented in asg::AsgMetadataTool, AthCheckedComponent< AthAlgTool >, and AthCheckedComponent<::AthAlgTool >.

◆ sysStart()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysStart ( )
overridevirtualinherited

Handle START transition.

We override this in order to make sure that conditions handle keys can cache a pointer to the conditions container.

◆ TOBetSort()

template<class TOBObjectClass>
bool LVL1::jFEXFPGA::TOBetSort ( const TOBObjectClass & i,
const TOBObjectClass & j,
uint bits,
uint mask )
inlinestaticprivate

Internal data.

Definition at line 96 of file jFEXFPGA.h.

96 {
97 return (((i->getWord() >> bits ) & mask)>((j->getWord() >> bits ) & mask));
98 }

◆ updateVHKA()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::updateVHKA ( Gaudi::Details::PropertyBase & )
inlineinherited

Definition at line 308 of file AthCommonDataStore.h.

308 {
309 // debug() << "updateVHKA for property " << p.name() << " " << p.toString()
310 // << " size: " << m_vhka.size() << endmsg;
311 for (auto &a : m_vhka) {
312 std::vector<SG::VarHandleKey*> keys = a->keys();
313 for (auto k : keys) {
314 k->setOwner(this);
315 }
316 }
317 }
AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
std::vector< SG::VarHandleKeyArray * > m_vhka
Definition AthCommonDataStore.h:398

Member Data Documentation

◆ m_detStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_detStore
privateinherited

Pointer to StoreGate (detector store by default).

Definition at line 393 of file AthCommonDataStore.h.

◆ m_evtStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_evtStore
privateinherited

Pointer to StoreGate (event store by default).

Definition at line 390 of file AthCommonDataStore.h.

◆ m_FwdEl_tobwords

std::vector<std::vector<uint32_t> > LVL1::jFEXFPGA::m_FwdEl_tobwords
private

Definition at line 111 of file jFEXFPGA.h.

◆ m_id

int LVL1::jFEXFPGA::m_id {}
private

Definition at line 108 of file jFEXFPGA.h.

108{};

◆ m_IjFEXFormTOBsTool

ToolHandle<IjFEXFormTOBs> LVL1::jFEXFPGA::m_IjFEXFormTOBsTool {this, "IjFEXFormTOBsTool", "LVL1::jFEXFormTOBs", "Tool that forms TOB words"}
private

Definition at line 129 of file jFEXFPGA.h.

129{this, "IjFEXFormTOBsTool", "LVL1::jFEXFormTOBs", "Tool that forms TOB words"};

◆ m_jfex_string

std::string LVL1::jFEXFPGA::m_jfex_string[6] = {"1C","2C","3C","3A","2A","1A"}
private

Definition at line 132 of file jFEXFPGA.h.

132{"1C","2C","3C","3A","2A","1A"};

◆ m_jFEXForwardElecAlgoTool

ToolHandle<IjFEXForwardElecAlgo> LVL1::jFEXFPGA::m_jFEXForwardElecAlgoTool {this, "jFEXForwardElecAlgoTool" , "LVL1::jFEXForwardElecAlgo" , "Tool that runs the jFEX FCAL Electrons algorithm"}
private

Definition at line 127 of file jFEXFPGA.h.

127{this, "jFEXForwardElecAlgoTool" , "LVL1::jFEXForwardElecAlgo" , "Tool that runs the jFEX FCAL Electrons algorithm"};

◆ m_jFEXForwardJetsAlgoTool

ToolHandle<IjFEXForwardJetsAlgo> LVL1::jFEXFPGA::m_jFEXForwardJetsAlgoTool {this, "jFEXForwardJetsAlgoTool" , "LVL1::jFEXForwardJetsAlgo" , "Tool that runs the jFEX FCAL Jets algorithm"}
private

Definition at line 126 of file jFEXFPGA.h.

126{this, "jFEXForwardJetsAlgoTool" , "LVL1::jFEXForwardJetsAlgo" , "Tool that runs the jFEX FCAL Jets algorithm"};

◆ m_jfexid

int LVL1::jFEXFPGA::m_jfexid {}
private

Definition at line 109 of file jFEXFPGA.h.

109{};

◆ m_jFEXLargeRJetAlgoTool

ToolHandle<IjFEXLargeRJetAlgo> LVL1::jFEXFPGA::m_jFEXLargeRJetAlgoTool {this, "jFEXLargeRJetAlgoTool", "LVL1::jFEXLargeRJetAlgo", "Tool that runs the jFEX Large R Jet algorithm"}
private

Definition at line 122 of file jFEXFPGA.h.

122{this, "jFEXLargeRJetAlgoTool", "LVL1::jFEXLargeRJetAlgo", "Tool that runs the jFEX Large R Jet algorithm"};

◆ m_jFEXmetAlgoTool

ToolHandle<IjFEXmetAlgo> LVL1::jFEXFPGA::m_jFEXmetAlgoTool {this, "jFEXmetAlgoTool" , "LVL1::jFEXmetAlgo" , "Tool that runs the jFEX met algorithm"}
private

Definition at line 125 of file jFEXFPGA.h.

125{this, "jFEXmetAlgoTool" , "LVL1::jFEXmetAlgo" , "Tool that runs the jFEX met algorithm"};

◆ m_jFEXPileupAndNoiseTool

ToolHandle<IjFEXPileupAndNoise> LVL1::jFEXFPGA::m_jFEXPileupAndNoiseTool {this, "jFEXPileupAndNoiseTool", "LVL1::jFEXPileupAndNoise", "Tool that applies Pileup and Noise"}
private

Definition at line 128 of file jFEXFPGA.h.

128{this, "jFEXPileupAndNoiseTool", "LVL1::jFEXPileupAndNoise", "Tool that applies Pileup and Noise"};

◆ m_jFEXSmallRJetAlgoTool

ToolHandle<IjFEXSmallRJetAlgo> LVL1::jFEXFPGA::m_jFEXSmallRJetAlgoTool {this, "jFEXSmallRJetAlgoTool", "LVL1::jFEXSmallRJetAlgo", "Tool that runs the jFEX Small R Jet algorithm"}
private

Definition at line 121 of file jFEXFPGA.h.

121{this, "jFEXSmallRJetAlgoTool", "LVL1::jFEXSmallRJetAlgo", "Tool that runs the jFEX Small R Jet algorithm"};

◆ m_jFEXsumETAlgoTool

ToolHandle<IjFEXsumETAlgo> LVL1::jFEXFPGA::m_jFEXsumETAlgoTool {this, "jFEXsumETAlgoTool" , "LVL1::jFEXsumETAlgo" , "Tool that runs the jFEX sumET algorithm"}
private

Definition at line 124 of file jFEXFPGA.h.

124{this, "jFEXsumETAlgoTool" , "LVL1::jFEXsumETAlgo" , "Tool that runs the jFEX sumET algorithm"};

◆ m_jFEXtauAlgoTool

ToolHandle<IjFEXtauAlgo> LVL1::jFEXFPGA::m_jFEXtauAlgoTool {this, "jFEXtauAlgoTool" , "LVL1::jFEXtauAlgo" , "Tool that runs the jFEX tau algorithm"}
private

Definition at line 123 of file jFEXFPGA.h.

123{this, "jFEXtauAlgoTool" , "LVL1::jFEXtauAlgo" , "Tool that runs the jFEX tau algorithm"};

◆ m_jTowerContainerKey

SG::ReadHandleKey<LVL1::jTowerContainer> LVL1::jFEXFPGA::m_jTowerContainerKey {this, "MyETowers", "jTowerContainer", "Input container for jTowers"}
private

Definition at line 119 of file jFEXFPGA.h.

119{this, "MyETowers", "jTowerContainer", "Input container for jTowers"};

◆ m_jTowersIDs_Thin

int LVL1::jFEXFPGA::m_jTowersIDs_Thin[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}}
private

Definition at line 114 of file jFEXFPGA.h.

114{{0}};

◆ m_jTowersIDs_Wide

int LVL1::jFEXFPGA::m_jTowersIDs_Wide[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}}
private

Definition at line 113 of file jFEXFPGA.h.

113{{0}};

◆ m_l1MenuKey

SG::ReadHandleKey<TrigConf::L1Menu> LVL1::jFEXFPGA::m_l1MenuKey {this, "L1TriggerMenu", "DetectorStore+L1TriggerMenu","Name of the L1Menu object to read configuration from"}
private

Definition at line 120 of file jFEXFPGA.h.

120{this, "L1TriggerMenu", "DetectorStore+L1TriggerMenu","Name of the L1Menu object to read configuration from"};

◆ m_LRJet_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_LRJet_tobwords
private

Definition at line 104 of file jFEXFPGA.h.

◆ m_map_EM_Etvalues_FPGA

std::unordered_map<int,std::vector<int> > LVL1::jFEXFPGA::m_map_EM_Etvalues_FPGA
private

Definition at line 117 of file jFEXFPGA.h.

◆ m_map_HAD_Etvalues_FPGA

std::unordered_map<int,std::vector<int> > LVL1::jFEXFPGA::m_map_HAD_Etvalues_FPGA
private

Definition at line 116 of file jFEXFPGA.h.

◆ m_Met_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_Met_tobwords
private

Definition at line 106 of file jFEXFPGA.h.

◆ m_SRJet_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_SRJet_tobwords
private

Definition at line 103 of file jFEXFPGA.h.

◆ m_sumET_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_sumET_tobwords
private

Definition at line 105 of file jFEXFPGA.h.

◆ m_tau_tobwords

std::vector<std::unique_ptr<jFEXTOB> > LVL1::jFEXFPGA::m_tau_tobwords
private

Definition at line 102 of file jFEXFPGA.h.

◆ m_varHandleArraysDeclared

bool AthCommonDataStore< AthCommonMsg< AlgTool > >::m_varHandleArraysDeclared
privateinherited

Definition at line 399 of file AthCommonDataStore.h.

◆ m_vhka

std::vector<SG::VarHandleKeyArray*> AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
privateinherited

Definition at line 398 of file AthCommonDataStore.h.

The documentation for this class was generated from the following files:
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