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LVL1::jFEXSim Class Reference

The jFEXSim class defines the structure of a single jFEX Its purpose is: More...

#include <jFEXSim.h>

Inheritance diagram for LVL1::jFEXSim:
Collaboration diagram for LVL1::jFEXSim:

Public Member Functions

 jFEXSim (const std::string &type, const std::string &name, const IInterface *parent)
 Constructors. More...
 
virtual ~jFEXSim ()
 Destructor. More...
 
virtual StatusCode initialize () override
 standard Athena-Algorithm method More...
 
virtual StatusCode finalize () override
 standard Athena-Algorithm method More...
 
virtual void init (int id) override
 
virtual void reset () override
 
virtual int ID () override
 
virtual void SetTowersAndCells_SG (int tmp[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]) override
 
virtual void SetTowersAndCells_SG (int tmp[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]) override
 
virtual StatusCode ExecuteForwardASide (int tmp[2 *FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width], jFEXOutputCollection *inputOutputCollection, const std::pair< unsigned int, const std::vector< int > & > &jetCalibrationParameters) override
 
virtual StatusCode ExecuteForwardCSide (int tmp[2 *FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width], jFEXOutputCollection *inputOutputCollection, const std::pair< unsigned int, const std::vector< int > & > &jetCalibrationParameters) override
 
virtual StatusCode ExecuteBarrel (int tmp[2 *FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width], jFEXOutputCollection *inputOutputCollection, const std::pair< unsigned int, const std::vector< int > & > &jetCalibrationParameters) override
 
virtual std::vector< std::vector< std::vector< uint32_t > > > getFwdElTOBs () override
 
virtual std::vector< std::vector< std::unique_ptr< jFEXTOB > > > getTauTOBs () override
 
virtual std::vector< std::vector< std::unique_ptr< jFEXTOB > > > getSmallRJetTOBs () override
 
virtual std::vector< std::vector< std::unique_ptr< jFEXTOB > > > getLargeRJetTOBs () override
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getSumEtTOBs () override
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getMetTOBs () override
 
ServiceHandle< StoreGateSvc > & evtStore ()
 The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc. More...
 
const ServiceHandle< StoreGateSvc > & evtStore () const
 The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc. More...
 
const ServiceHandle< StoreGateSvc > & detStore () const
 The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc. More...
 
virtual StatusCode sysInitialize () override
 Perform system initialization for an algorithm. More...
 
virtual StatusCode sysStart () override
 Handle START transition. More...
 
virtual std::vector< Gaudi::DataHandle * > inputHandles () const override
 Return this algorithm's input handles. More...
 
virtual std::vector< Gaudi::DataHandle * > outputHandles () const override
 Return this algorithm's output handles. More...
 
Gaudi::Details::PropertyBase & declareProperty (Gaudi::Property< T, V, H > &t)
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, SG::VarHandleKey &hndl, const std::string &doc, const SG::VarHandleKeyType &)
 Declare a new Gaudi property. More...
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, SG::VarHandleBase &hndl, const std::string &doc, const SG::VarHandleType &)
 Declare a new Gaudi property. More...
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, SG::VarHandleKeyArray &hndArr, const std::string &doc, const SG::VarHandleKeyArrayType &)
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, T &property, const std::string &doc, const SG::NotHandleType &)
 Declare a new Gaudi property. More...
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, T &property, const std::string &doc="none")
 Declare a new Gaudi property. More...
 
void updateVHKA (Gaudi::Details::PropertyBase &)
 
MsgStream & msg () const
 
MsgStream & msg (const MSG::Level lvl) const
 
bool msgLvl (const MSG::Level lvl) const
 

Static Public Member Functions

static const InterfaceID & interfaceID ()
 

Protected Member Functions

void renounceArray (SG::VarHandleKeyArray &handlesArray)
 remove all handles from I/O resolution More...
 
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > renounce (T &h)
 
void extraDeps_update_handler (Gaudi::Details::PropertyBase &ExtraDeps)
 Add StoreName to extra input/output deps as needed. More...
 

Private Types

typedef ServiceHandle< StoreGateSvc > StoreGateSvc_t
 

Private Member Functions

Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyType &)
 specialization for handling Gaudi::Property<SG::VarHandleKey> More...
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyArrayType &)
 specialization for handling Gaudi::Property<SG::VarHandleKeyArray> More...
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T, V, H > &hndl, const SG::VarHandleType &)
 specialization for handling Gaudi::Property<SG::VarHandleBase> More...
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T, V, H > &t, const SG::NotHandleType &)
 specialization for handling everything that's not a Gaudi::Property<SG::VarHandleKey> or a <SG::VarHandleKeyArray> More...
 

Private Attributes

int m_id {}
 Internal data. More...
 
int m_jTowersIDs_Wide [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] {}
 
int m_jTowersIDs_Thin [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] {}
 
std::unordered_map< int, jTower > m_jTowersColl
 
std::vector< jFEXFPGA * > m_jFEXFPGACollection
 
std::vector< std::vector< std::vector< uint32_t > > > m_fwdEl_tobWords
 
ToolHandle< IjFEXFPGA > m_jFEXFPGATool {this, "jFEXFPGATool", "LVL1::jFEXFPGA", "Tool that simulates the FPGA hardware"}
 
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_tau_tobWords
 
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_smallRJet_tobWords
 
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_largeRJet_tobWords
 
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_sumET_tobWords
 
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_Met_tobWords
 
StoreGateSvc_t m_evtStore
 Pointer to StoreGate (event store by default) More...
 
StoreGateSvc_t m_detStore
 Pointer to StoreGate (detector store by default) More...
 
std::vector< SG::VarHandleKeyArray * > m_vhka
 
bool m_varHandleArraysDeclared
 

Detailed Description

The jFEXSim class defines the structure of a single jFEX Its purpose is:

Definition at line 32 of file jFEXSim.h.

Member Typedef Documentation

◆ StoreGateSvc_t

typedef ServiceHandle<StoreGateSvc> AthCommonDataStore< AthCommonMsg< AlgTool > >::StoreGateSvc_t
privateinherited

Definition at line 388 of file AthCommonDataStore.h.

Constructor & Destructor Documentation

◆ jFEXSim()

LVL1::jFEXSim::jFEXSim ( const std::string &  type,
const std::string &  name,
const IInterface *  parent 
)

Constructors.

Definition at line 17 of file jFEXSim.cxx.

17  :
18  AthAlgTool(type,name,parent)
19  {
20  declareInterface<IjFEXSim>(this);
21  }

◆ ~jFEXSim()

LVL1::jFEXSim::~jFEXSim ( )
virtual

Destructor.

Definition at line 77 of file jFEXSim.cxx.

78  {
79  }

Member Function Documentation

◆ declareGaudiProperty() [1/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T, V, H > &  hndl,
const SG::VarHandleKeyArrayType &   
)
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKeyArray>

Definition at line 170 of file AthCommonDataStore.h.

172  {
173  return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
174  hndl.value(),
175  hndl.documentation());
176 
177  }

◆ declareGaudiProperty() [2/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T, V, H > &  hndl,
const SG::VarHandleKeyType &   
)
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKey>

Definition at line 156 of file AthCommonDataStore.h.

158  {
159  return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
160  hndl.value(),
161  hndl.documentation());
162 
163  }

◆ declareGaudiProperty() [3/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T, V, H > &  hndl,
const SG::VarHandleType &   
)
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleBase>

Definition at line 184 of file AthCommonDataStore.h.

186  {
187  return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
188  hndl.value(),
189  hndl.documentation());
190  }

◆ declareGaudiProperty() [4/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T, V, H > &  t,
const SG::NotHandleType &   
)
inlineprivateinherited

specialization for handling everything that's not a Gaudi::Property<SG::VarHandleKey> or a <SG::VarHandleKeyArray>

Definition at line 199 of file AthCommonDataStore.h.

200  {
201  return PBASE::declareProperty(t);
202  }

◆ declareProperty() [1/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
SG::VarHandleBase &  hndl,
const std::string &  doc,
const SG::VarHandleType &   
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
hndlObject holding the property value.
docDocumentation string for the property.

This is the version for types that derive from SG::VarHandleBase. The property value object is put on the input and output lists as appropriate; then we forward to the base class.

Definition at line 245 of file AthCommonDataStore.h.

249  {
250  this->declare(hndl.vhKey());
251  hndl.vhKey().setOwner(this);
252 
253  return PBASE::declareProperty(name,hndl,doc);
254  }

◆ declareProperty() [2/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
SG::VarHandleKey &  hndl,
const std::string &  doc,
const SG::VarHandleKeyType &   
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
hndlObject holding the property value.
docDocumentation string for the property.

This is the version for types that derive from SG::VarHandleKey. The property value object is put on the input and output lists as appropriate; then we forward to the base class.

Definition at line 221 of file AthCommonDataStore.h.

225  {
226  this->declare(hndl);
227  hndl.setOwner(this);
228 
229  return PBASE::declareProperty(name,hndl,doc);
230  }

◆ declareProperty() [3/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
SG::VarHandleKeyArray &  hndArr,
const std::string &  doc,
const SG::VarHandleKeyArrayType &   
)
inlineinherited

Definition at line 259 of file AthCommonDataStore.h.

263  {
264 
265  // std::ostringstream ost;
266  // ost << Algorithm::name() << " VHKA declareProp: " << name
267  // << " size: " << hndArr.keys().size()
268  // << " mode: " << hndArr.mode()
269  // << " vhka size: " << m_vhka.size()
270  // << "\n";
271  // debug() << ost.str() << endmsg;
272 
273  hndArr.setOwner(this);
274  m_vhka.push_back(&hndArr);
275 
276  Gaudi::Details::PropertyBase* p = PBASE::declareProperty(name, hndArr, doc);
277  if (p != 0) {
278  p->declareUpdateHandler(&AthCommonDataStore<PBASE>::updateVHKA, this);
279  } else {
280  ATH_MSG_ERROR("unable to call declareProperty on VarHandleKeyArray "
281  << name);
282  }
283 
284  return p;
285 
286  }

◆ declareProperty() [4/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
T &  property,
const std::string &  doc,
const SG::NotHandleType &   
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
propertyObject holding the property value.
docDocumentation string for the property.

This is the generic version, for types that do not derive from SG::VarHandleKey. It just forwards to the base class version of declareProperty.

Definition at line 333 of file AthCommonDataStore.h.

337  {
338  return PBASE::declareProperty(name, property, doc);
339  }

◆ declareProperty() [5/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
T &  property,
const std::string &  doc = "none" 
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
propertyObject holding the property value.
docDocumentation string for the property.

This dispatches to either the generic declareProperty or the one for VarHandle/Key/KeyArray.

Definition at line 352 of file AthCommonDataStore.h.

355  {
356  typedef typename SG::HandleClassifier<T>::type htype;
357  return declareProperty (name, property, doc, htype());
358  }

◆ declareProperty() [6/6]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( Gaudi::Property< T, V, H > &  t)
inlineinherited

Definition at line 145 of file AthCommonDataStore.h.

145  {
146  typedef typename SG::HandleClassifier<T>::type htype;
147  return AthCommonDataStore<PBASE>::declareGaudiProperty(t, htype());
148  }

◆ detStore()

const ServiceHandle<StoreGateSvc>& AthCommonDataStore< AthCommonMsg< AlgTool > >::detStore ( ) const
inlineinherited

The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 95 of file AthCommonDataStore.h.

95 { return m_detStore; }

◆ evtStore() [1/2]

ServiceHandle<StoreGateSvc>& AthCommonDataStore< AthCommonMsg< AlgTool > >::evtStore ( )
inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 85 of file AthCommonDataStore.h.

85 { return m_evtStore; }

◆ evtStore() [2/2]

const ServiceHandle<StoreGateSvc>& AthCommonDataStore< AthCommonMsg< AlgTool > >::evtStore ( ) const
inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 90 of file AthCommonDataStore.h.

90 { return m_evtStore; }

◆ ExecuteBarrel()

StatusCode LVL1::jFEXSim::ExecuteBarrel ( int  tmp[2 *FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width],
jFEXOutputCollection *  inputOutputCollection,
const std::pair< unsigned int, const std::vector< int > & > &  jetCalibrationParameters 
)
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 579 of file jFEXSim.cxx.

579  {
580 
581 
582  const int nrows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
583  const int ncols = FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width;
584 
585  // FPGA boundaries in phi: 0.0, 1.6, 3.2, 4.8, 6.4
586  // Written explicitly:
587  // 5.6 -> 2.4 [core is 0.0 to 1.6]
588  // 0.8 -> 4.0 [core is 1.6 to 3.2]
589  // 2.4 -> 5.6 [core is 3.2 to 4.8]
590  // 4.0 -> 0.8 [core is 4.8 to 6.4]
591 
592  int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
593 
594 
595  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
596  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
597  // 5.6 -> 2.4 [core is 0.0 to 1.6]
598  for (int myrow = 0; myrow<8; myrow++){
599  for (int mycol = 0; mycol<ncols; mycol++){
600  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[56+myrow][mycol]; // fills target rows 0-7 with source rows 56-63
601  }
602  }
603  for (int myrow = 8; myrow<32; myrow++){
604  for (int mycol = 0; mycol<ncols; mycol++){
605  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-8][mycol]; // fills target rows 8-31 with source rows 0-23
606  }
607  }
608  ATH_CHECK(m_jFEXFPGATool->init(0, m_id));
609  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
610  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
611  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
612  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
613  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
614  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
615  m_sumET_tobWords.push_back(m_jFEXFPGATool->getSumEtTOBs());
616  m_Met_tobWords.push_back(m_jFEXFPGATool->getMetTOBs());
617  m_jFEXFPGATool->reset();
618  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
619 
620  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
621  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
622  // 0.8 -> 4.0 [core is 1.6 to 3.2]
623  for (int myrow = 0; myrow<32; myrow++){
624  for (int mycol = 0; mycol<ncols; mycol++){
625  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[8+myrow][mycol]; // fills target rows 0-31 with source rows 8-39
626  }
627  }
628  ATH_CHECK(m_jFEXFPGATool->init(1, m_id));
629  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
630  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
631  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
632  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
633  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
634  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
635  m_jFEXFPGATool->reset();
636  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
637 
638 
639  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
640  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
641  // 2.4 -> 5.6 [core is 3.2 to 4.8]
642  for (int myrow = 0; myrow<32; myrow++){
643  for (int mycol = 0; mycol<ncols; mycol++){
644  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[24+myrow][mycol]; // fills target rows 0-31 with source rows 24-55
645  }
646  }
647  //FPGA 2 correcponds to U4, index 3
648  ATH_CHECK(m_jFEXFPGATool->init(3, m_id));
649  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
650  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
651  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
652  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
653  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
654  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
655  m_sumET_tobWords.push_back(m_jFEXFPGATool->getSumEtTOBs());
656  m_Met_tobWords.push_back(m_jFEXFPGATool->getMetTOBs());
657  m_jFEXFPGATool->reset();
658  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
659 
660  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
661  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
662  // 4.0 -> 0.8 [core is 4.8 to 6.4]
663  for (int myrow = 0; myrow<24; myrow++){
664  for (int mycol = 0; mycol<ncols; mycol++){
665  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[40+myrow][mycol]; // fills target rows 0-23 with source rows 40-63
666  }
667  }
668  for (int myrow = 24; myrow<32; myrow++){
669  for (int mycol = 0; mycol<ncols; mycol++){
670  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-24][mycol]; // fills target rows 24-31 with source rows 0-8
671  }
672  }
673  //FPGA 3 correcponds to U3, index 2
674  ATH_CHECK(m_jFEXFPGATool->init(2, m_id));
675  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
676  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
677  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
678  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
679  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
680  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
681  m_jFEXFPGATool->reset();
682  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
683 
684  return StatusCode::SUCCESS;
685 
686 }

◆ ExecuteForwardASide()

StatusCode LVL1::jFEXSim::ExecuteForwardASide ( int  tmp[2 *FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width],
jFEXOutputCollection *  inputOutputCollection,
const std::pair< unsigned int, const std::vector< int > & > &  jetCalibrationParameters 
)
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 84 of file jFEXSim.cxx.

84  {
85 
86  const int nrows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
87  const int ncols = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width;
88 
89  // So the way this works now is a little awkward due to the forward regions, which have less cells in phi and also overlap a lot.
90  // Interesting that I put nrows = 16*2 here, the documentation (l1caloreqs) looks like it should infact be just 16 (based on Fig 27)
91  // But actually the overlap is I suppose much greater, probably covering a much larger region, in this case 16/2
92  // Yes, this is answered by the few lines just below which specify the exact ranges
93  // Back to the forward regions, which have less cells in phi. We have 2 decisions, we can either fill half the cells in phi, or fill every other cell in phi
94  // For now I will fill every other cell in phi, but realistically the algorithm in the forward region needs to be written in a very different way
95  // and the re-writing on that algorithm will likely impact on how it is written in the central regions too
96  // The new writing of the algorithm will need to use the information from the central point of each tower in the array to check if it falls within a certain radius
97  // it cannot rely on the structure of the array itself at all. As such this algorithm is likely to end up being much less efficient that the eFEX equivalent.
98 
99  int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
100 
101  // FPGA boundaries in phi: 0.0, 1.6, 3.2, 4.8, 6.4
102  // Written explicitly:
103  // 5.6 -> 2.4 [core is 0.0 to 1.6] // FPGA 0
104  // 0.8 -> 4.0 [core is 1.6 to 3.2] // FPGA 1
105  // 2.4 -> 5.6 [core is 3.2 to 4.8] // FPGA 2
106  // 4.0 -> 0.8 [core is 4.8 to 6.4] // FPGA 3
107 
108  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
109  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
110  // 5.6 -> 2.4 [core is 0.0 to 1.6]
111  for (int myrow = 0; myrow<2; myrow++){
112  for (int mycol = 0; mycol<24; mycol++){
113  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[14+myrow][mycol]; // For columns 0-23: Fills target rows 0-1 with source rows 14-15
114  }
115  }
116  for (int myrow = 2; myrow<6; myrow++){
117  for (int mycol = 0; mycol<24; mycol++){
118  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol]; // For columns 0-23: Fills target rows 2-5 with source rows 0-3
119  }
120  }
121  for (int myrow = 6; myrow<8; myrow++){
122  for (int mycol = 0; mycol<24; mycol++){
123  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol]; // For columns 0-23: Fills target rows 6-8 with source rows 4-5
124  }
125  }
126  for (int myrow = 0; myrow<4; myrow++){
127  for (int mycol = 24; mycol<28; mycol++){
128  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[28+myrow][mycol]; // For columns 24-27: Fills target rows 0-3 with source rows 28-31
129  }
130  }
131  for (int myrow = 4; myrow<12; myrow++){
132  for (int mycol = 24; mycol<28; mycol++){
133  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol]; // For columns 24-27: Fills target rows 4-11 with source rows 0-7
134  }
135  }
136  for (int myrow = 12; myrow<16; myrow++){
137  for (int mycol = 24; mycol<28; mycol++){
138  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol]; // For columns 24-27: Fills target rows 12-15 with source rows 8-11
139  }
140  }
141  for (int myrow = 0; myrow<8; myrow++){
142  for (int mycol = 28; mycol<ncols; mycol++){
143  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[56+myrow][mycol]; // For columns 0-7: Fills target rows 0-7 with source rows 56-63
144  }
145  }
146  for (int myrow = 8; myrow<32; myrow++){
147  for (int mycol = 28; mycol<ncols; mycol++){
148  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-8][mycol]; // For columns 8-END: Fills target rows 8-31 with source rows 0-23
149  }
150  }
151  ATH_CHECK(m_jFEXFPGATool->init(0, m_id));
152  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
153  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
154  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
155  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
156  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
157  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
158  m_sumET_tobWords.push_back(m_jFEXFPGATool->getSumEtTOBs());
159  m_Met_tobWords.push_back(m_jFEXFPGATool->getMetTOBs());
160  m_jFEXFPGATool->reset();
161  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
162 
163  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
164  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
165  // 0.8 -> 4.0 [core is 1.6 to 3.2]
166  for (int myrow = 0; myrow<2; myrow++){
167  for (int mycol = 0; mycol<24; mycol++){
168  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[2+myrow][mycol]; // For columns 0-23: Fills target rows 0-1 with source rows 2-3
169  }
170  }
171  for (int myrow = 2; myrow<6; myrow++){
172  for (int mycol = 0; mycol<24; mycol++){
173  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol]; // For columns 0-23: Fills target rows 2-5 with source rows 4-7
174  }
175  }
176  for (int myrow = 6; myrow<8; myrow++){
177  for (int mycol = 0; mycol<24; mycol++){
178  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol]; // For columns 0-23: Fills target rows 6-8 with source rows 8-9
179  }
180  }
181  for (int myrow = 0; myrow<4; myrow++){
182  for (int mycol = 24; mycol<28; mycol++){
183  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[4+myrow][mycol]; // For columns 24-27: Fills target rows 0-3 with source rows 4-7
184  }
185  }
186  for (int myrow = 4; myrow<12; myrow++){
187  for (int mycol = 24; mycol<28; mycol++){
188  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol]; // For columns 24-27: Fills target rows 4-11 with source rows 8-15
189  }
190  }
191  for (int myrow = 12; myrow<16; myrow++){
192  for (int mycol = 24; mycol<28; mycol++){
193  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol]; // For columns 24-27: Fills target rows 12-15 with source rows 16-19
194  }
195  }
196  for (int myrow = 0; myrow<8; myrow++){
197  for (int mycol = 28; mycol<ncols; mycol++){
198  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[8+myrow][mycol]; // For columns 0-7: Fills target rows 0-7 with source rows 8-15
199  }
200  }
201  for (int myrow = 8; myrow<32; myrow++){
202  for (int mycol = 28; mycol<ncols; mycol++){
203  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+8][mycol]; // For columns 8-END: Fills target rows 8-31 with source rows 16-39
204  }
205  }
206  ATH_CHECK(m_jFEXFPGATool->init(1, m_id));
207  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
208  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
209  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
210  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
211  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
212  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
213  m_jFEXFPGATool->reset();
214  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
215 
216 
217  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
218  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
219  // 2.4 -> 5.6 [core is 3.2 to 4.8]
220  for (int myrow = 0; myrow<2; myrow++){
221  for (int mycol = 0; mycol<24; mycol++){
222  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[6+myrow][mycol]; // For columns 0-23: Fills target rows 0-1 with source rows 6-7
223  }
224  }
225  for (int myrow = 2; myrow<6; myrow++){
226  for (int mycol = 0; mycol<24; mycol++){
227  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol]; // For columns 0-23: Fills target rows 2-5 with source rows 8-11
228  }
229  }
230  for (int myrow = 6; myrow<8; myrow++){
231  for (int mycol = 0; mycol<24; mycol++){
232  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol]; // For columns 0-23: Fills target rows 6-8 with source rows 12-13
233  }
234  }
235  for (int myrow = 0; myrow<4; myrow++){
236  for (int mycol = 24; mycol<28; mycol++){
237  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[12+myrow][mycol]; // For columns 24-27: Fills target rows 0-3 with source rows 12-15
238  }
239  }
240  for (int myrow = 4; myrow<12; myrow++){
241  for (int mycol = 24; mycol<28; mycol++){
242  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol]; // For columns 24-27: Fills target rows 4-11 with source rows 16-23
243  }
244  }
245  for (int myrow = 12; myrow<16; myrow++){
246  for (int mycol = 24; mycol<28; mycol++){
247  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol]; // For columns 24-27: Fills target rows 12-15 with source rows 24-27
248  }
249  }
250  for (int myrow = 0; myrow<8; myrow++){
251  for (int mycol = 28; mycol<ncols; mycol++){
252  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[24+myrow][mycol]; // For columns 0-7: Fills target rows 0-7 with source rows 24-31
253  }
254  }
255  for (int myrow = 8; myrow<32; myrow++){
256  for (int mycol = 28; mycol<ncols; mycol++){
257  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+24][mycol]; // For columns 8-END: Fills target rows 8-31 with source rows 32-55
258  }
259  }
260 
261  //FPGA 2 correcponds to U4, index 3
262  ATH_CHECK(m_jFEXFPGATool->init(3, m_id));
263  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
264  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
265  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
266  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
267  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
268  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
269  m_sumET_tobWords.push_back(m_jFEXFPGATool->getSumEtTOBs());
270  m_Met_tobWords.push_back(m_jFEXFPGATool->getMetTOBs());
271  m_jFEXFPGATool->reset();
272  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
273 
274  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
275  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
276  // 4.0 -> 0.8 [core is 4.8 to 6.4]
277  for (int myrow = 0; myrow<2; myrow++){
278  for (int mycol = 0; mycol<24; mycol++){
279  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[10+myrow][mycol]; // For columns 0-23: Fills target rows 0-1 with source rows 10-11
280  }
281  }
282  for (int myrow = 2; myrow<6; myrow++){
283  for (int mycol = 0; mycol<24; mycol++){
284  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+10][mycol]; // For columns 0-23: Fills target rows 2-5 with source rows 12-15
285  }
286  }
287  for (int myrow = 6; myrow<8; myrow++){
288  for (int mycol = 0; mycol<24; mycol++){
289  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-6][mycol]; // For columns 0-23: Fills target rows 6-8 with source rows 0-1
290  }
291  }
292  for (int myrow = 0; myrow<4; myrow++){
293  for (int mycol = 24; mycol<28; mycol++){
294  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[20+myrow][mycol]; // For columns 24-27: Fills target rows 0-3 with source rows 20-23
295  }
296  }
297  for (int myrow = 4; myrow<12; myrow++){
298  for (int mycol = 24; mycol<28; mycol++){
299  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+20][mycol]; // For columns 24-27: Fills target rows 4-11 with source rows 24-31
300  }
301  }
302  for (int myrow = 12; myrow<16; myrow++){
303  for (int mycol = 24; mycol<28; mycol++){
304  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-12][mycol]; // For columns 24-27: Fills target rows 12-15 with source rows 0-3
305  }
306  }
307  for (int myrow = 0; myrow<24; myrow++){
308  for (int mycol = 28; mycol<ncols; mycol++){
309  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[40+myrow][mycol]; // For columns 0-23: Fills target rows 0-23 with source rows 40-63
310  }
311  }
312  for (int myrow = 24; myrow<32; myrow++){
313  for (int mycol = 28; mycol<ncols; mycol++){
314  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-24][mycol]; // For columns 24-END: Fills target rows 24-31 with source rows 0-8
315  }
316  }
317  //FPGA 3 correcponds to U3, index 2
318  ATH_CHECK(m_jFEXFPGATool->init(2, m_id));
319  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
320  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
321  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
322  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
323  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
324  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
325  m_jFEXFPGATool->reset();
326  //FPGA 3---------------------------------------------------------------------------------------------------------------------------------------------
327 
328  return StatusCode::SUCCESS;
329 
330 }

◆ ExecuteForwardCSide()

StatusCode LVL1::jFEXSim::ExecuteForwardCSide ( int  tmp[2 *FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width],
jFEXOutputCollection *  inputOutputCollection,
const std::pair< unsigned int, const std::vector< int > & > &  jetCalibrationParameters 
)
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 332 of file jFEXSim.cxx.

332  {
333 
334  const int nrows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
335  const int ncols = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width;
336 
337  // So the way this works now is a little awkward due to the forward regions, which have less cells in phi and also overlap a lot.
338  // Interesting that I put nrows = 16*2 here, the documentation (l1caloreqs) looks like it should infact be just 16 (based on Fig 27)
339  // But actually the overlap is I suppose much greater, probably covering a much larger region, in this case 16/2
340  // Yes, this is answered by the few lines just below which specify the exact ranges
341  // Back to the forward regions, which have less cells in phi. We have 2 decisions, we can either fill half the cells in phi, or fill every other cell in phi
342  // For now I will fill every other cell in phi, but realistically the algorithm in the forward region needs to be written in a very different way
343  // and the re-writing on that algorithm will likely impact on how it is written in the central regions too
344  // The new writing of the algorithm will need to use the information from the central point of each tower in the array to check if it falls within a certain radius
345  // it cannot rely on the structure of the array itself at all. As such this algorithm is likely to end up being much less efficient that the eFEX equivalent.
346 
347  int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
348 
349  // FPGA boundaries in phi: 0.0, 1.6, 3.2, 4.8, 6.4
350  // Written explicitly:
351  // 5.6 -> 2.4 [core is 0.0 to 1.6] // FPGA 0
352  // 0.8 -> 4.0 [core is 1.6 to 3.2] // FPGA 1
353  // 2.4 -> 5.6 [core is 3.2 to 4.8] // FPGA 2
354  // 4.0 -> 0.8 [core is 4.8 to 6.4] // FPGA 3
355 
356  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
357  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
358  // 5.6 -> 2.4 [core is 0.0 to 1.6]
359  for (int myrow = 0; myrow<2; myrow++){
360  for (int mycol = ncols-24; mycol<ncols; mycol++){
361  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[14+myrow][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 0-1 with source rows 14-15
362  }
363  }
364  for (int myrow = 2; myrow<6; myrow++){
365  for (int mycol = ncols-24; mycol<ncols; mycol++){
366  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 2-5 with source rows 0-3
367  }
368  }
369  for (int myrow = 6; myrow<8; myrow++){
370  for (int mycol = ncols-24; mycol<ncols; mycol++){
371  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 6-8 with source rows 4-5
372  }
373  }
374  for (int myrow = 0; myrow<4; myrow++){
375  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
376  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[28+myrow][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 0-3 with source rows 28-31
377  }
378  }
379  for (int myrow = 4; myrow<12; myrow++){
380  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
381  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 4-11 with source rows 0-7
382  }
383  }
384  for (int myrow = 12; myrow<16; myrow++){
385  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
386  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 12-15 with source rows 8-11
387  }
388  }
389  for (int myrow = 0; myrow<8; myrow++){
390  for (int mycol = 0; mycol<ncols-28; mycol++){
391  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[56+myrow][mycol]; // For columns 0-7 (mirrored for CSide however): Fills target rows 0-7 with source rows 56-63
392  }
393  }
394  for (int myrow = 8; myrow<32; myrow++){
395  for (int mycol = 0; mycol<ncols-28; mycol++){
396  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-8][mycol]; // For columns 8-END (mirrored for CSide however): Fills target rows 8-31 with source rows 0-23
397  }
398  }
399  ATH_CHECK(m_jFEXFPGATool->init(0, m_id));
400  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
401  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
402  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
403  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
404  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
405  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
406  m_sumET_tobWords.push_back(m_jFEXFPGATool->getSumEtTOBs());
407  m_Met_tobWords.push_back(m_jFEXFPGATool->getMetTOBs());
408  m_jFEXFPGATool->reset();
409  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
410 
411  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
412  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
413  // 0.8 -> 4.0 [core is 1.6 to 3.2]
414  for (int myrow = 0; myrow<2; myrow++){
415  for (int mycol = ncols-24; mycol<ncols; mycol++){
416  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[2+myrow][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 0-1 with source rows 2-3
417  }
418  }
419  for (int myrow = 2; myrow<6; myrow++){
420  for (int mycol = ncols-24; mycol<ncols; mycol++){
421  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 2-5 with source rows 4-7
422  }
423  }
424  for (int myrow = 6; myrow<8; myrow++){
425  for (int mycol = ncols-24; mycol<ncols; mycol++){
426  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 6-8 with source rows 8-9
427  }
428  }
429  for (int myrow = 0; myrow<4; myrow++){
430  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
431  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[4+myrow][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 0-3 with source rows 4-7
432  }
433  }
434  for (int myrow = 4; myrow<12; myrow++){
435  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
436  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 4-11 with source rows 8-15
437  }
438  }
439  for (int myrow = 12; myrow<16; myrow++){
440  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
441  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 12-15 with source rows 16-19
442  }
443  }
444  for (int myrow = 0; myrow<8; myrow++){
445  for (int mycol = 0; mycol<ncols-28; mycol++){
446  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[8+myrow][mycol]; // For columns 0-7 (mirrored for CSide however): Fills target rows 0-7 with source rows 8-15
447  }
448  }
449  for (int myrow = 8; myrow<32; myrow++){
450  for (int mycol = 0; mycol<ncols-28; mycol++){
451  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+8][mycol]; // For columns 8-END (mirrored for CSide however): Fills target rows 8-31 with source rows 16-39
452  }
453  }
454  ATH_CHECK(m_jFEXFPGATool->init(1, m_id));
455  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
456  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
457  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
458  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
459  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
460  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
461  m_jFEXFPGATool->reset();
462  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
463 
464  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
465  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
466  // 2.4 -> 5.6 [core is 3.2 to 4.8]
467  for (int myrow = 0; myrow<2; myrow++){
468  for (int mycol = ncols-24; mycol<ncols; mycol++){
469  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[6+myrow][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 0-1 with source rows 6-7
470  }
471  }
472  for (int myrow = 2; myrow<6; myrow++){
473  for (int mycol = ncols-24; mycol<ncols; mycol++){
474  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 2-5 with source rows 8-11
475  }
476  }
477  for (int myrow = 6; myrow<8; myrow++){
478  for (int mycol = ncols-24; mycol<ncols; mycol++){
479  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 6-8 with source rows 12-13
480  }
481  }
482  for (int myrow = 0; myrow<4; myrow++){
483  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
484  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[12+myrow][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 0-3 with source rows 12-15
485  }
486  }
487  for (int myrow = 4; myrow<12; myrow++){
488  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
489  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 4-11 with source rows 16-23
490  }
491  }
492  for (int myrow = 12; myrow<16; myrow++){
493  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
494  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 12-15 with source rows 24-27
495  }
496  }
497  for (int myrow = 0; myrow<8; myrow++){
498  for (int mycol = 0; mycol<ncols-28; mycol++){
499  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[24+myrow][mycol]; // For columns 0-7 (mirrored for CSide however): Fills target rows 0-7 with source rows 24-31
500  }
501  }
502  for (int myrow = 8; myrow<32; myrow++){
503  for (int mycol = 0; mycol<ncols-28; mycol++){
504  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+24][mycol]; // For columns 8-END (mirrored for CSide however): Fills target rows 8-31 with source rows 32-55
505  }
506  }
507  //FPGA 2 correcponds to U4, index 3
508  ATH_CHECK(m_jFEXFPGATool->init(3, m_id));
509  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
510  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
511  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
512  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
513  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
514  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
515  m_sumET_tobWords.push_back(m_jFEXFPGATool->getSumEtTOBs());
516  m_Met_tobWords.push_back(m_jFEXFPGATool->getMetTOBs());
517  m_jFEXFPGATool->reset();
518  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
519 
520  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
521  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
522  // 4.0 -> 0.8 [core is 4.8 to 6.4]
523  for (int myrow = 0; myrow<2; myrow++){
524  for (int mycol = ncols-24; mycol<ncols; mycol++){
525  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[10+myrow][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 0-1 with source rows 10-11
526  }
527  }
528  for (int myrow = 2; myrow<6; myrow++){
529  for (int mycol = ncols-24; mycol<ncols; mycol++){
530  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+10][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 2-5 with source rows 12-15
531  }
532  }
533  for (int myrow = 6; myrow<8; myrow++){
534  for (int mycol = ncols-24; mycol<ncols; mycol++){
535  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-6][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 6-8 with source rows 0-1
536  }
537  }
538  for (int myrow = 0; myrow<4; myrow++){
539  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
540  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[20+myrow][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 0-3 with source rows 20-23
541  }
542  }
543  for (int myrow = 4; myrow<12; myrow++){
544  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
545  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+20][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 4-11 with source rows 24-31
546  }
547  }
548  for (int myrow = 12; myrow<16; myrow++){
549  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
550  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-12][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 12-15 with source rows 0-3
551  }
552  }
553  for (int myrow = 0; myrow<24; myrow++){
554  for (int mycol = 0; mycol<ncols-28; mycol++){
555  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[40+myrow][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 0-23 with source rows 40-63
556  }
557  }
558  for (int myrow = 24; myrow<32; myrow++){
559  for (int mycol = 0; mycol<ncols-28; mycol++){
560  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-24][mycol]; // For columns 24-END (mirrored for CSide however): Fills target rows 24-31 with source rows 0-8
561  }
562  }
563  //FPGA 3 correcponds to U3, index 2
564  ATH_CHECK(m_jFEXFPGATool->init(2, m_id));
565  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
566  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
567  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
568  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
569  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
570  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
571  m_jFEXFPGATool->reset();
572  //FPGA 3---------------------------------------------------------------------------------------------------------------------------------------------
573 
574  return StatusCode::SUCCESS;
575 
576  }

◆ extraDeps_update_handler()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::extraDeps_update_handler ( Gaudi::Details::PropertyBase &  ExtraDeps)
protectedinherited

Add StoreName to extra input/output deps as needed.

use the logic of the VarHandleKey to parse the DataObjID keys supplied via the ExtraInputs and ExtraOuputs Properties to add the StoreName if it's not explicitly given

◆ finalize()

StatusCode LVL1::jFEXSim::finalize ( )
overridevirtual

standard Athena-Algorithm method

Definition at line 34 of file jFEXSim.cxx.

35  {
36  return StatusCode::SUCCESS;
37  }

◆ getFwdElTOBs()

std::vector< std::vector< std::vector< uint32_t > > > LVL1::jFEXSim::getFwdElTOBs ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 786 of file jFEXSim.cxx.

786  {
787 
788  return m_fwdEl_tobWords;
789 }

◆ getLargeRJetTOBs()

std::vector< std::vector< std::unique_ptr< jFEXTOB > > > LVL1::jFEXSim::getLargeRJetTOBs ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 757 of file jFEXSim.cxx.

758 {
759  std::vector< std::vector<std::unique_ptr<jFEXTOB>> > ljTOBs;
760  ljTOBs.resize(m_largeRJet_tobWords.size());
761 
762  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
763  for (unsigned int i = 0; i < m_largeRJet_tobWords.size(); ++i){
764  for(unsigned int j = 0; j < m_largeRJet_tobWords[i].size(); ++j){
765  ljTOBs.at(i).push_back(std::move(m_largeRJet_tobWords[i][j]));
766  }
767  }
768  return ljTOBs;
769 }

◆ getMetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXSim::getMetTOBs ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 805 of file jFEXSim.cxx.

805  {
806 
807  std::vector<std::unique_ptr<jFEXTOB>> metTOBs;
808 
809  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
810  for (unsigned int i = 0; i < m_Met_tobWords.size(); ++i){
811  for(unsigned int j = 0; j < m_Met_tobWords[i].size(); ++j){
812  metTOBs.push_back(std::move(m_Met_tobWords[i][j]));
813  }
814  }
815 
816  return metTOBs;
817 }

◆ getSmallRJetTOBs()

std::vector< std::vector< std::unique_ptr< jFEXTOB > > > LVL1::jFEXSim::getSmallRJetTOBs ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 741 of file jFEXSim.cxx.

742 {
743  std::vector< std::vector<std::unique_ptr<jFEXTOB>>> sjTOBs;
744  sjTOBs.clear();
745  sjTOBs.resize(m_smallRJet_tobWords.size());
746 
747  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
748  for (unsigned int i = 0; i < m_smallRJet_tobWords.size(); ++i){
749  for(unsigned int j = 0; j < m_smallRJet_tobWords[i].size(); ++j){
750  sjTOBs.at(i).push_back(std::move(m_smallRJet_tobWords[i][j]));
751  }
752  }
753  return sjTOBs;
754 
755 }

◆ getSumEtTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXSim::getSumEtTOBs ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 791 of file jFEXSim.cxx.

791  {
792 
793  std::vector<std::unique_ptr<jFEXTOB>> sumetTOBs;
794 
795  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
796  for (unsigned int i = 0; i < m_sumET_tobWords.size(); ++i){
797  for(unsigned int j = 0; j < m_sumET_tobWords[i].size(); ++j){
798  sumetTOBs.push_back(std::move(m_sumET_tobWords[i][j]));
799  }
800  }
801 
802  return sumetTOBs;
803 }

◆ getTauTOBs()

std::vector< std::vector< std::unique_ptr< jFEXTOB > > > LVL1::jFEXSim::getTauTOBs ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 771 of file jFEXSim.cxx.

772 {
773  std::vector< std::vector<std::unique_ptr<jFEXTOB>> > tauTOBs;
774  tauTOBs.resize(m_tau_tobWords.size());
775 
776  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
777  for (unsigned int i = 0; i < m_tau_tobWords.size(); ++i){
778  for(unsigned int j = 0; j < m_tau_tobWords[i].size(); ++j){
779  tauTOBs.at(i).push_back(std::move(m_tau_tobWords[i][j]));
780  }
781  }
782 
783  return tauTOBs;
784 }

◆ ID()

virtual int LVL1::jFEXSim::ID ( )
inlineoverridevirtual

Implements LVL1::IjFEXSim.

Definition at line 51 of file jFEXSim.h.

51 {return m_id;}

◆ init()

void LVL1::jFEXSim::init ( int  id)
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 71 of file jFEXSim.cxx.

72  {
73  m_id = id;
74  }

◆ initialize()

StatusCode LVL1::jFEXSim::initialize ( )
overridevirtual

standard Athena-Algorithm method

Definition at line 26 of file jFEXSim.cxx.

27  {
28  ATH_CHECK( m_jFEXFPGATool.retrieve() );
29  return StatusCode::SUCCESS;
30  }

◆ inputHandles()

virtual std::vector<Gaudi::DataHandle*> AthCommonDataStore< AthCommonMsg< AlgTool > >::inputHandles ( ) const
overridevirtualinherited

Return this algorithm's input handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ interfaceID()

const InterfaceID & LVL1::IjFEXSim::interfaceID ( )
inlinestaticinherited

Definition at line 62 of file IjFEXSim.h.

63  {
64  return IID_IjFEXSim;
65  }

◆ msg() [1/2]

MsgStream& AthCommonMsg< AlgTool >::msg ( ) const
inlineinherited

Definition at line 24 of file AthCommonMsg.h.

24  {
25  return this->msgStream();
26  }

◆ msg() [2/2]

MsgStream& AthCommonMsg< AlgTool >::msg ( const MSG::Level  lvl) const
inlineinherited

Definition at line 27 of file AthCommonMsg.h.

27  {
28  return this->msgStream(lvl);
29  }

◆ msgLvl()

bool AthCommonMsg< AlgTool >::msgLvl ( const MSG::Level  lvl) const
inlineinherited

Definition at line 30 of file AthCommonMsg.h.

30  {
31  return this->msgLevel(lvl);
32  }

◆ outputHandles()

virtual std::vector<Gaudi::DataHandle*> AthCommonDataStore< AthCommonMsg< AlgTool > >::outputHandles ( ) const
overridevirtualinherited

Return this algorithm's output handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ renounce()

std::enable_if_t<std::is_void_v<std::result_of_t<decltype(&T::renounce)(T)> > && !std::is_base_of_v<SG::VarHandleKeyArray, T> && std::is_base_of_v<Gaudi::DataHandle, T>, void> AthCommonDataStore< AthCommonMsg< AlgTool > >::renounce ( T &  h)
inlineprotectedinherited

Definition at line 380 of file AthCommonDataStore.h.

381  {
382  h.renounce();
383  PBASE::renounce (h);
384  }

◆ renounceArray()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::renounceArray ( SG::VarHandleKeyArray &  handlesArray)
inlineprotectedinherited

remove all handles from I/O resolution

Definition at line 364 of file AthCommonDataStore.h.

364  {
365  handlesArray.renounce();
366  }

◆ reset()

void LVL1::jFEXSim::reset ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 40 of file jFEXSim.cxx.

41  {
42 
43  m_id = -1;
44  m_jFEXFPGACollection.clear();
45 
46  int rows = sizeof m_jTowersIDs_Thin / sizeof m_jTowersIDs_Thin[0];
47  int cols = sizeof m_jTowersIDs_Thin[0] / sizeof m_jTowersIDs_Thin[0][0];
48  for (int i=0; i<rows; i++){
49  for (int j=0; j<cols; j++){
50  m_jTowersIDs_Thin[i][j] = 0;
51  }
52  }
53 
54 
55  rows = sizeof m_jTowersIDs_Wide / sizeof m_jTowersIDs_Wide[0];
56  cols = sizeof m_jTowersIDs_Wide[0] / sizeof m_jTowersIDs_Wide[0][0];
57  for (int i=0; i<rows; i++){
58  for (int j=0; j<cols; j++){
59  m_jTowersIDs_Wide[i][j] = 0;
60  }
61  }
62 
63  m_smallRJet_tobWords.clear();
64  m_tau_tobWords.clear();
65  m_fwdEl_tobWords.clear();
66  m_largeRJet_tobWords.clear();
67  m_sumET_tobWords.clear();
68  m_Met_tobWords.clear();
69  }

◆ SetTowersAndCells_SG() [1/2]

void LVL1::jFEXSim::SetTowersAndCells_SG ( int  tmp[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 822 of file jFEXSim.cxx.

822  { // METHOD USING ONLY IDS
823 
824  const int nrows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
825  const int ncols = FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width;
826 
827  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(nrows*ncols),&m_jTowersIDs_Thin[0][0]);
828 
829  int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
830 
831  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
832  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
833  for (int myrow = 0; myrow<nrows; myrow++){
834  for (int mycol = 0; mycol<ncols; mycol++){
835  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
836  }
837  }
838  m_jFEXFPGACollection.at(0)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
839  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
840 
841  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
842  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
843  for (int myrow = nrows; myrow<nrows*2; myrow++){
844  for (int mycol = 0; mycol<ncols; mycol++){
845  tmp_jTowersIDs_subset_FPGA[myrow-nrows][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
846  }
847  }
848  m_jFEXFPGACollection.at(1)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
849  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
850 
851 
852  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
853  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
854  for (int myrow = nrows*2; myrow<nrows*3; myrow++){
855  for (int mycol = 0; mycol<ncols; mycol++){
856  tmp_jTowersIDs_subset_FPGA[myrow-(nrows*2)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
857  }
858  }
859  m_jFEXFPGACollection.at(2)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
860  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
861 
862  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
863  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
864  for (int myrow = nrows*3; myrow<nrows*4; myrow++){
865  for (int mycol = 0; mycol<ncols; mycol++){
866  tmp_jTowersIDs_subset_FPGA[myrow-(nrows*3)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
867  }
868  }
869  m_jFEXFPGACollection.at(3)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
870  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
871 
872  }

◆ SetTowersAndCells_SG() [2/2]

void LVL1::jFEXSim::SetTowersAndCells_SG ( int  tmp[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 688 of file jFEXSim.cxx.

688  { // METHOD USING ONLY IDS
689 
690  const int nrows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
691  const int ncols = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width;
692  // We may need a function along the lines of "SetForwardTowersAndCells_SG"(int tmp_jTowerIDs_subset[16][28]
693 
694  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(nrows*ncols),&m_jTowersIDs_Wide[0][0]);
695 
696  int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
697 
698  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
699  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
700  for (int myrow = 0; myrow<nrows; myrow++){
701  for (int mycol = 0; mycol<ncols; mycol++){
702  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
703  }
704  }
705  m_jFEXFPGACollection.at(0)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
706  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
707 
708  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
709  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
710  for (int myrow = nrows; myrow<nrows*2; myrow++){
711  for (int mycol = 0; mycol<ncols; mycol++){
712  tmp_jTowersIDs_subset_FPGA[myrow-nrows][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
713  }
714  }
715  m_jFEXFPGACollection.at(1)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
716  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
717 
718 
719  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
720  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
721  for (int myrow = nrows*2; myrow<nrows*3; myrow++){
722  for (int mycol = 0; mycol<ncols; mycol++){
723  tmp_jTowersIDs_subset_FPGA[myrow-(nrows*2)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
724  }
725  }
726  m_jFEXFPGACollection.at(2)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
727  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
728 
729  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
730  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
731  for (int myrow = nrows*3; myrow<nrows*4; myrow++){
732  for (int mycol = 0; mycol<ncols; mycol++){
733  tmp_jTowersIDs_subset_FPGA[myrow-(nrows*3)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
734  }
735  }
736  m_jFEXFPGACollection.at(3)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
737  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
738 
739 }

◆ sysInitialize()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysInitialize ( )
overridevirtualinherited

Perform system initialization for an algorithm.

We override this to declare all the elements of handle key arrays at the end of initialization. See comments on updateVHKA.

Reimplemented in DerivationFramework::CfAthAlgTool, AthCheckedComponent< AthAlgTool >, AthCheckedComponent<::AthAlgTool >, and asg::AsgMetadataTool.

◆ sysStart()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysStart ( )
overridevirtualinherited

Handle START transition.

We override this in order to make sure that conditions handle keys can cache a pointer to the conditions container.

◆ updateVHKA()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::updateVHKA ( Gaudi::Details::PropertyBase &  )
inlineinherited

Definition at line 308 of file AthCommonDataStore.h.

308  {
309  // debug() << "updateVHKA for property " << p.name() << " " << p.toString()
310  // << " size: " << m_vhka.size() << endmsg;
311  for (auto &a : m_vhka) {
312  std::vector<SG::VarHandleKey*> keys = a->keys();
313  for (auto k : keys) {
314  k->setOwner(this);
315  }
316  }
317  }

Member Data Documentation

◆ m_detStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_detStore
privateinherited

Pointer to StoreGate (detector store by default)

Definition at line 393 of file AthCommonDataStore.h.

◆ m_evtStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_evtStore
privateinherited

Pointer to StoreGate (event store by default)

Definition at line 390 of file AthCommonDataStore.h.

◆ m_fwdEl_tobWords

std::vector<std::vector<std::vector<uint32_t> > > LVL1::jFEXSim::m_fwdEl_tobWords
private

Definition at line 81 of file jFEXSim.h.

◆ m_id

int LVL1::jFEXSim::m_id {}
private

Internal data.

Definition at line 72 of file jFEXSim.h.

◆ m_jFEXFPGACollection

std::vector<jFEXFPGA*> LVL1::jFEXSim::m_jFEXFPGACollection
private

Definition at line 79 of file jFEXSim.h.

◆ m_jFEXFPGATool

ToolHandle<IjFEXFPGA> LVL1::jFEXSim::m_jFEXFPGATool {this, "jFEXFPGATool", "LVL1::jFEXFPGA", "Tool that simulates the FPGA hardware"}
private

Definition at line 83 of file jFEXSim.h.

◆ m_jTowersColl

std::unordered_map<int,jTower> LVL1::jFEXSim::m_jTowersColl
private

Definition at line 76 of file jFEXSim.h.

◆ m_jTowersIDs_Thin

int LVL1::jFEXSim::m_jTowersIDs_Thin[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] {}
private

Definition at line 74 of file jFEXSim.h.

◆ m_jTowersIDs_Wide

int LVL1::jFEXSim::m_jTowersIDs_Wide[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] {}
private

Definition at line 73 of file jFEXSim.h.

◆ m_largeRJet_tobWords

std::vector< std::vector<std::unique_ptr<jFEXTOB> > > LVL1::jFEXSim::m_largeRJet_tobWords
private

Definition at line 88 of file jFEXSim.h.

◆ m_Met_tobWords

std::vector< std::vector<std::unique_ptr<jFEXTOB> > > LVL1::jFEXSim::m_Met_tobWords
private

Definition at line 90 of file jFEXSim.h.

◆ m_smallRJet_tobWords

std::vector< std::vector<std::unique_ptr<jFEXTOB> > > LVL1::jFEXSim::m_smallRJet_tobWords
private

Definition at line 87 of file jFEXSim.h.

◆ m_sumET_tobWords

std::vector< std::vector<std::unique_ptr<jFEXTOB> > > LVL1::jFEXSim::m_sumET_tobWords
private

Definition at line 89 of file jFEXSim.h.

◆ m_tau_tobWords

std::vector< std::vector<std::unique_ptr<jFEXTOB> > > LVL1::jFEXSim::m_tau_tobWords
private

Definition at line 86 of file jFEXSim.h.

◆ m_varHandleArraysDeclared

bool AthCommonDataStore< AthCommonMsg< AlgTool > >::m_varHandleArraysDeclared
privateinherited

Definition at line 399 of file AthCommonDataStore.h.

◆ m_vhka

std::vector<SG::VarHandleKeyArray*> AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
privateinherited

Definition at line 398 of file AthCommonDataStore.h.

The documentation for this class was generated from the following files:
LVL1::jFEXSim::m_id
int m_id
Internal data.
Definition: jFEXSim.h:72
LVL1::FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width
constexpr static int jFEX_thin_algoSpace_width
Definition: FEXAlgoSpaceDefs.h:28
LVL1::jFEXSim::m_largeRJet_tobWords
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_largeRJet_tobWords
Definition: jFEXSim.h:88
LVL1::jFEXSim::m_jFEXFPGACollection
std::vector< jFEXFPGA * > m_jFEXFPGACollection
Definition: jFEXSim.h:79
AthCommonDataStore< AthCommonMsg< AlgTool > >::m_evtStore
StoreGateSvc_t m_evtStore
Pointer to StoreGate (event store by default)
Definition: AthCommonDataStore.h:390
AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
std::vector< SG::VarHandleKeyArray * > m_vhka
Definition: AthCommonDataStore.h:398
LVL1::FEXAlgoSpaceDefs::jFEX_algoSpace_height
constexpr static int jFEX_algoSpace_height
Definition: FEXAlgoSpaceDefs.h:29
read_hist_ntuple.t
t
Definition: read_hist_ntuple.py:5
python.CaloAddPedShiftConfig.type
type
Definition: CaloAddPedShiftConfig.py:42
SG::VarHandleKeyArray::setOwner
virtual void setOwner(IDataHandleHolder *o)=0
IDTPMcnv.htype
htype
Definition: IDTPMcnv.py:29
AthCommonDataStore::declareGaudiProperty
Gaudi::Details::PropertyBase & declareGaudiProperty(Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyType &)
specialization for handling Gaudi::Property<SG::VarHandleKey>
Definition: AthCommonDataStore.h:156
beamspotnt.cols
list cols
Definition: bin/beamspotnt.py:1113
python.utils.AtlRunQueryDQUtils.p
p
Definition: AtlRunQueryDQUtils.py:209
AthCommonDataStore
Definition: AthCommonDataStore.h:52
ATH_MSG_ERROR
#define ATH_MSG_ERROR(x)
Definition: AthMsgStreamMacros.h:33
lumiFormat.i
int i
Definition: lumiFormat.py:85
AthCommonDataStore::declareProperty
Gaudi::Details::PropertyBase & declareProperty(Gaudi::Property< T, V, H > &t)
Definition: AthCommonDataStore.h:145
LVL1::FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width
constexpr static int jFEX_wide_algoSpace_width
Definition: FEXAlgoSpaceDefs.h:27
test_pyathena.parent
parent
Definition: test_pyathena.py:15
ATH_CHECK
#define ATH_CHECK
Definition: AthCheckMacros.h:40
beamspotnt.rows
list rows
Definition: bin/beamspotnt.py:1111
AthCommonDataStore< AthCommonMsg< AlgTool > >::m_detStore
StoreGateSvc_t m_detStore
Pointer to StoreGate (detector store by default)
Definition: AthCommonDataStore.h:393
LVL1::jFEXSim::m_Met_tobWords
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_Met_tobWords
Definition: jFEXSim.h:90
AthAlgTool::AthAlgTool
AthAlgTool()
Default constructor:
SG::VarHandleKeyArray::renounce
virtual void renounce()=0
SG::HandleClassifier::type
std::conditional< std::is_base_of< SG::VarHandleKeyArray, T >::value, VarHandleKeyArrayType, type2 >::type type
Definition: HandleClassifier.h:54
merge_scale_histograms.doc
string doc
Definition: merge_scale_histograms.py:9
id
SG::auxid_t id
Definition: Control/AthContainers/Root/debug.cxx:239
name
std::string name
Definition: Control/AthContainers/Root/debug.cxx:240
LVL1::jFEXSim::m_jFEXFPGATool
ToolHandle< IjFEXFPGA > m_jFEXFPGATool
Definition: jFEXSim.h:83
a
TList * a
Definition: liststreamerinfos.cxx:10
h
LVL1::jFEXSim::m_sumET_tobWords
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_sumET_tobWords
Definition: jFEXSim.h:89
SG::VarHandleBase::vhKey
SG::VarHandleKey & vhKey()
Return a non-const reference to the HandleKey.
Definition: StoreGate/src/VarHandleBase.cxx:629
python.Bindings.keys
keys
Definition: Control/AthenaPython/python/Bindings.py:801
calibdata.copy
bool copy
Definition: calibdata.py:26
LVL1::jFEXSim::m_jTowersIDs_Wide
int m_jTowersIDs_Wide[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]
Definition: jFEXSim.h:73
LVL1::jFEXSim::m_tau_tobWords
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_tau_tobWords
Definition: jFEXSim.h:86
LVL1::jFEXSim::m_jTowersIDs_Thin
int m_jTowersIDs_Thin[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]
Definition: jFEXSim.h:74
LVL1::jFEXSim::m_smallRJet_tobWords
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_smallRJet_tobWords
Definition: jFEXSim.h:87
LVL1::jFEXSim::m_fwdEl_tobWords
std::vector< std::vector< std::vector< uint32_t > > > m_fwdEl_tobWords
Definition: jFEXSim.h:81
fitman.k
k
Definition: fitman.py:528
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