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LVL1::jFEXSim Class Reference

The jFEXSim class defines the structure of a single jFEX Its purpose is: More...

#include <jFEXSim.h>

Inheritance diagram for LVL1::jFEXSim:
Collaboration diagram for LVL1::jFEXSim:

Public Member Functions

 jFEXSim (const std::string &type, const std::string &name, const IInterface *parent)
 Constructors. More...
 
virtual ~jFEXSim ()
 Destructor. More...
 
virtual StatusCode initialize () override
 standard Athena-Algorithm method More...
 
virtual StatusCode finalize () override
 standard Athena-Algorithm method More...
 
virtual void init (int id) override
 
virtual void reset () override
 
virtual int ID () override
 
virtual void SetTowersAndCells_SG (int tmp[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]) override
 
virtual void SetTowersAndCells_SG (int tmp[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]) override
 
virtual StatusCode ExecuteForwardASide (int tmp[2 *FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width], jFEXOutputCollection *inputOutputCollection, const std::pair< unsigned int, const std::vector< int > & > &jetCalibrationParameters) override
 
virtual StatusCode ExecuteForwardCSide (int tmp[2 *FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width], jFEXOutputCollection *inputOutputCollection, const std::pair< unsigned int, const std::vector< int > & > &jetCalibrationParameters) override
 
virtual StatusCode ExecuteBarrel (int tmp[2 *FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width], jFEXOutputCollection *inputOutputCollection, const std::pair< unsigned int, const std::vector< int > & > &jetCalibrationParameters) override
 
virtual std::vector< std::vector< std::vector< uint32_t > > > getFwdElTOBs () override
 
virtual std::vector< std::vector< std::unique_ptr< jFEXTOB > > > getTauTOBs () override
 
virtual std::vector< std::vector< std::unique_ptr< jFEXTOB > > > getSmallRJetTOBs () override
 
virtual std::vector< std::vector< std::unique_ptr< jFEXTOB > > > getLargeRJetTOBs () override
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getSumEtTOBs () override
 
virtual std::vector< std::unique_ptr< jFEXTOB > > getMetTOBs () override
 
ServiceHandle< StoreGateSvc > & evtStore ()
 The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc. More...
 
const ServiceHandle< StoreGateSvc > & evtStore () const
 The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc. More...
 
const ServiceHandle< StoreGateSvc > & detStore () const
 The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc. More...
 
virtual StatusCode sysInitialize () override
 Perform system initialization for an algorithm. More...
 
virtual StatusCode sysStart () override
 Handle START transition. More...
 
virtual std::vector< Gaudi::DataHandle * > inputHandles () const override
 Return this algorithm's input handles. More...
 
virtual std::vector< Gaudi::DataHandle * > outputHandles () const override
 Return this algorithm's output handles. More...
 
Gaudi::Details::PropertyBase & declareProperty (Gaudi::Property< T > &t)
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, SG::VarHandleKey &hndl, const std::string &doc, const SG::VarHandleKeyType &)
 Declare a new Gaudi property. More...
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, SG::VarHandleBase &hndl, const std::string &doc, const SG::VarHandleType &)
 Declare a new Gaudi property. More...
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, SG::VarHandleKeyArray &hndArr, const std::string &doc, const SG::VarHandleKeyArrayType &)
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, T &property, const std::string &doc, const SG::NotHandleType &)
 Declare a new Gaudi property. More...
 
Gaudi::Details::PropertyBase * declareProperty (const std::string &name, T &property, const std::string &doc="none")
 Declare a new Gaudi property. More...
 
void updateVHKA (Gaudi::Details::PropertyBase &)
 
MsgStream & msg () const
 
MsgStream & msg (const MSG::Level lvl) const
 
bool msgLvl (const MSG::Level lvl) const
 

Static Public Member Functions

static const InterfaceID & interfaceID ()
 

Protected Member Functions

void renounceArray (SG::VarHandleKeyArray &handlesArray)
 remove all handles from I/O resolution More...
 
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > renounce (T &h)
 
void extraDeps_update_handler (Gaudi::Details::PropertyBase &ExtraDeps)
 Add StoreName to extra input/output deps as needed. More...
 

Private Types

typedef ServiceHandle< StoreGateSvc > StoreGateSvc_t
 

Private Member Functions

Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T > &hndl, const SG::VarHandleKeyType &)
 specialization for handling Gaudi::Property<SG::VarHandleKey> More...
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T > &hndl, const SG::VarHandleKeyArrayType &)
 specialization for handling Gaudi::Property<SG::VarHandleKeyArray> More...
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T > &hndl, const SG::VarHandleType &)
 specialization for handling Gaudi::Property<SG::VarHandleBase> More...
 
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T > &t, const SG::NotHandleType &)
 specialization for handling everything that's not a Gaudi::Property<SG::VarHandleKey> or a <SG::VarHandleKeyArray> More...
 

Private Attributes

int m_id
 Internal data. More...
 
int m_jTowersIDs_Wide [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]
 
int m_jTowersIDs_Thin [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]
 
std::unordered_map< int, jTower > m_jTowersColl
 
CaloCellContainer m_sCellsCollection
 
std::vector< jFEXFPGA * > m_jFEXFPGACollection
 
std::vector< std::vector< std::vector< uint32_t > > > m_fwdEl_tobWords
 
ToolHandle< IjFEXFPGA > m_jFEXFPGATool {this, "jFEXFPGATool", "LVL1::jFEXFPGA", "Tool that simulates the FPGA hardware"}
 
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_tau_tobWords
 
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_smallRJet_tobWords
 
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_largeRJet_tobWords
 
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_sumET_tobWords
 
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_Met_tobWords
 
StoreGateSvc_t m_evtStore
 Pointer to StoreGate (event store by default) More...
 
StoreGateSvc_t m_detStore
 Pointer to StoreGate (detector store by default) More...
 
std::vector< SG::VarHandleKeyArray * > m_vhka
 
bool m_varHandleArraysDeclared
 

Detailed Description

The jFEXSim class defines the structure of a single jFEX Its purpose is:

Definition at line 34 of file jFEXSim.h.

Member Typedef Documentation

◆ StoreGateSvc_t

typedef ServiceHandle<StoreGateSvc> AthCommonDataStore< AthCommonMsg< AlgTool > >::StoreGateSvc_t
privateinherited

Definition at line 388 of file AthCommonDataStore.h.

Constructor & Destructor Documentation

◆ jFEXSim()

LVL1::jFEXSim::jFEXSim ( const std::string &  type,
const std::string &  name,
const IInterface *  parent 
)

Constructors.

Definition at line 27 of file jFEXSim.cxx.

27  :
28  AthAlgTool(type,name,parent)
29  {
30  declareInterface<IjFEXSim>(this);
31  }

◆ ~jFEXSim()

LVL1::jFEXSim::~jFEXSim ( )
virtual

Destructor.

Definition at line 87 of file jFEXSim.cxx.

88  {
89  }

Member Function Documentation

◆ declareGaudiProperty() [1/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T > &  hndl,
const SG::VarHandleKeyArrayType &   
)
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKeyArray>

Definition at line 170 of file AthCommonDataStore.h.

172  {
173  return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
174  hndl.value(),
175  hndl.documentation());
176 
177  }

◆ declareGaudiProperty() [2/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T > &  hndl,
const SG::VarHandleKeyType &   
)
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKey>

Definition at line 156 of file AthCommonDataStore.h.

158  {
159  return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
160  hndl.value(),
161  hndl.documentation());
162 
163  }

◆ declareGaudiProperty() [3/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T > &  hndl,
const SG::VarHandleType &   
)
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleBase>

Definition at line 184 of file AthCommonDataStore.h.

186  {
187  return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
188  hndl.value(),
189  hndl.documentation());
190  }

◆ declareGaudiProperty() [4/4]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T > &  t,
const SG::NotHandleType &   
)
inlineprivateinherited

specialization for handling everything that's not a Gaudi::Property<SG::VarHandleKey> or a <SG::VarHandleKeyArray>

Definition at line 199 of file AthCommonDataStore.h.

200  {
201  return PBASE::declareProperty(t);
202  }

◆ declareProperty() [1/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
SG::VarHandleBase &  hndl,
const std::string &  doc,
const SG::VarHandleType &   
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
hndlObject holding the property value.
docDocumentation string for the property.

This is the version for types that derive from SG::VarHandleBase. The property value object is put on the input and output lists as appropriate; then we forward to the base class.

Definition at line 245 of file AthCommonDataStore.h.

249  {
250  this->declare(hndl.vhKey());
251  hndl.vhKey().setOwner(this);
252 
253  return PBASE::declareProperty(name,hndl,doc);
254  }

◆ declareProperty() [2/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
SG::VarHandleKey &  hndl,
const std::string &  doc,
const SG::VarHandleKeyType &   
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
hndlObject holding the property value.
docDocumentation string for the property.

This is the version for types that derive from SG::VarHandleKey. The property value object is put on the input and output lists as appropriate; then we forward to the base class.

Definition at line 221 of file AthCommonDataStore.h.

225  {
226  this->declare(hndl);
227  hndl.setOwner(this);
228 
229  return PBASE::declareProperty(name,hndl,doc);
230  }

◆ declareProperty() [3/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
SG::VarHandleKeyArray &  hndArr,
const std::string &  doc,
const SG::VarHandleKeyArrayType &   
)
inlineinherited

Definition at line 259 of file AthCommonDataStore.h.

263  {
264 
265  // std::ostringstream ost;
266  // ost << Algorithm::name() << " VHKA declareProp: " << name
267  // << " size: " << hndArr.keys().size()
268  // << " mode: " << hndArr.mode()
269  // << " vhka size: " << m_vhka.size()
270  // << "\n";
271  // debug() << ost.str() << endmsg;
272 
273  hndArr.setOwner(this);
274  m_vhka.push_back(&hndArr);
275 
276  Gaudi::Details::PropertyBase* p = PBASE::declareProperty(name, hndArr, doc);
277  if (p != 0) {
278  p->declareUpdateHandler(&AthCommonDataStore<PBASE>::updateVHKA, this);
279  } else {
280  ATH_MSG_ERROR("unable to call declareProperty on VarHandleKeyArray "
281  << name);
282  }
283 
284  return p;
285 
286  }

◆ declareProperty() [4/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
T &  property,
const std::string &  doc,
const SG::NotHandleType &   
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
propertyObject holding the property value.
docDocumentation string for the property.

This is the generic version, for types that do not derive from SG::VarHandleKey. It just forwards to the base class version of declareProperty.

Definition at line 333 of file AthCommonDataStore.h.

337  {
338  return PBASE::declareProperty(name, property, doc);
339  }

◆ declareProperty() [5/6]

Gaudi::Details::PropertyBase* AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( const std::string &  name,
T &  property,
const std::string &  doc = "none" 
)
inlineinherited

Declare a new Gaudi property.

Parameters
nameName of the property.
propertyObject holding the property value.
docDocumentation string for the property.

This dispatches to either the generic declareProperty or the one for VarHandle/Key/KeyArray.

Definition at line 352 of file AthCommonDataStore.h.

355  {
356  typedef typename SG::HandleClassifier<T>::type htype;
357  return declareProperty (name, property, doc, htype());
358  }

◆ declareProperty() [6/6]

Gaudi::Details::PropertyBase& AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( Gaudi::Property< T > &  t)
inlineinherited

Definition at line 145 of file AthCommonDataStore.h.

145  {
146  typedef typename SG::HandleClassifier<T>::type htype;
147  return AthCommonDataStore<PBASE>::declareGaudiProperty(t, htype());
148  }

◆ detStore()

const ServiceHandle<StoreGateSvc>& AthCommonDataStore< AthCommonMsg< AlgTool > >::detStore ( ) const
inlineinherited

The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 95 of file AthCommonDataStore.h.

95 { return m_detStore; }

◆ evtStore() [1/2]

ServiceHandle<StoreGateSvc>& AthCommonDataStore< AthCommonMsg< AlgTool > >::evtStore ( )
inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 85 of file AthCommonDataStore.h.

85 { return m_evtStore; }

◆ evtStore() [2/2]

const ServiceHandle<StoreGateSvc>& AthCommonDataStore< AthCommonMsg< AlgTool > >::evtStore ( ) const
inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 90 of file AthCommonDataStore.h.

90 { return m_evtStore; }

◆ ExecuteBarrel()

StatusCode LVL1::jFEXSim::ExecuteBarrel ( int  tmp[2 *FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width],
jFEXOutputCollection *  inputOutputCollection,
const std::pair< unsigned int, const std::vector< int > & > &  jetCalibrationParameters 
)
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 589 of file jFEXSim.cxx.

589  {
590 
591 
592  const int nrows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
593  const int ncols = FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width;
594 
595  // FPGA boundaries in phi: 0.0, 1.6, 3.2, 4.8, 6.4
596  // Written explicitly:
597  // 5.6 -> 2.4 [core is 0.0 to 1.6]
598  // 0.8 -> 4.0 [core is 1.6 to 3.2]
599  // 2.4 -> 5.6 [core is 3.2 to 4.8]
600  // 4.0 -> 0.8 [core is 4.8 to 6.4]
601 
602  int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
603 
604 
605  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
606  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
607  // 5.6 -> 2.4 [core is 0.0 to 1.6]
608  for (int myrow = 0; myrow<8; myrow++){
609  for (int mycol = 0; mycol<ncols; mycol++){
610  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[56+myrow][mycol]; // fills target rows 0-7 with source rows 56-63
611  }
612  }
613  for (int myrow = 8; myrow<32; myrow++){
614  for (int mycol = 0; mycol<ncols; mycol++){
615  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-8][mycol]; // fills target rows 8-31 with source rows 0-23
616  }
617  }
618  ATH_CHECK(m_jFEXFPGATool->init(0, m_id));
619  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
620  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
621  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
622  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
623  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
624  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
625  m_sumET_tobWords.push_back(m_jFEXFPGATool->getSumEtTOBs());
626  m_Met_tobWords.push_back(m_jFEXFPGATool->getMetTOBs());
627  m_jFEXFPGATool->reset();
628  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
629 
630  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
631  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
632  // 0.8 -> 4.0 [core is 1.6 to 3.2]
633  for (int myrow = 0; myrow<32; myrow++){
634  for (int mycol = 0; mycol<ncols; mycol++){
635  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[8+myrow][mycol]; // fills target rows 0-31 with source rows 8-39
636  }
637  }
638  ATH_CHECK(m_jFEXFPGATool->init(1, m_id));
639  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
640  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
641  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
642  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
643  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
644  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
645  m_jFEXFPGATool->reset();
646  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
647 
648 
649  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
650  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
651  // 2.4 -> 5.6 [core is 3.2 to 4.8]
652  for (int myrow = 0; myrow<32; myrow++){
653  for (int mycol = 0; mycol<ncols; mycol++){
654  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[24+myrow][mycol]; // fills target rows 0-31 with source rows 24-55
655  }
656  }
657  //FPGA 2 correcponds to U4, index 3
658  ATH_CHECK(m_jFEXFPGATool->init(3, m_id));
659  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
660  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
661  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
662  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
663  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
664  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
665  m_sumET_tobWords.push_back(m_jFEXFPGATool->getSumEtTOBs());
666  m_Met_tobWords.push_back(m_jFEXFPGATool->getMetTOBs());
667  m_jFEXFPGATool->reset();
668  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
669 
670  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
671  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
672  // 4.0 -> 0.8 [core is 4.8 to 6.4]
673  for (int myrow = 0; myrow<24; myrow++){
674  for (int mycol = 0; mycol<ncols; mycol++){
675  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[40+myrow][mycol]; // fills target rows 0-23 with source rows 40-63
676  }
677  }
678  for (int myrow = 24; myrow<32; myrow++){
679  for (int mycol = 0; mycol<ncols; mycol++){
680  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-24][mycol]; // fills target rows 24-31 with source rows 0-8
681  }
682  }
683  //FPGA 3 correcponds to U3, index 2
684  ATH_CHECK(m_jFEXFPGATool->init(2, m_id));
685  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
686  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
687  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
688  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
689  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
690  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
691  m_jFEXFPGATool->reset();
692  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
693 
694  return StatusCode::SUCCESS;
695 
696 }

◆ ExecuteForwardASide()

StatusCode LVL1::jFEXSim::ExecuteForwardASide ( int  tmp[2 *FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width],
jFEXOutputCollection *  inputOutputCollection,
const std::pair< unsigned int, const std::vector< int > & > &  jetCalibrationParameters 
)
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 94 of file jFEXSim.cxx.

94  {
95 
96  const int nrows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
97  const int ncols = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width;
98 
99  // So the way this works now is a little awkward due to the forward regions, which have less cells in phi and also overlap a lot.
100  // Interesting that I put nrows = 16*2 here, the documentation (l1caloreqs) looks like it should infact be just 16 (based on Fig 27)
101  // But actually the overlap is I suppose much greater, probably covering a much larger region, in this case 16/2
102  // Yes, this is answered by the few lines just below which specify the exact ranges
103  // Back to the forward regions, which have less cells in phi. We have 2 decisions, we can either fill half the cells in phi, or fill every other cell in phi
104  // For now I will fill every other cell in phi, but realistically the algorithm in the forward region needs to be written in a very different way
105  // and the re-writing on that algorithm will likely impact on how it is written in the central regions too
106  // The new writing of the algorithm will need to use the information from the central point of each tower in the array to check if it falls within a certain radius
107  // it cannot rely on the structure of the array itself at all. As such this algorithm is likely to end up being much less efficient that the eFEX equivalent.
108 
109  int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
110 
111  // FPGA boundaries in phi: 0.0, 1.6, 3.2, 4.8, 6.4
112  // Written explicitly:
113  // 5.6 -> 2.4 [core is 0.0 to 1.6] // FPGA 0
114  // 0.8 -> 4.0 [core is 1.6 to 3.2] // FPGA 1
115  // 2.4 -> 5.6 [core is 3.2 to 4.8] // FPGA 2
116  // 4.0 -> 0.8 [core is 4.8 to 6.4] // FPGA 3
117 
118  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
119  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
120  // 5.6 -> 2.4 [core is 0.0 to 1.6]
121  for (int myrow = 0; myrow<2; myrow++){
122  for (int mycol = 0; mycol<24; mycol++){
123  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[14+myrow][mycol]; // For columns 0-23: Fills target rows 0-1 with source rows 14-15
124  }
125  }
126  for (int myrow = 2; myrow<6; myrow++){
127  for (int mycol = 0; mycol<24; mycol++){
128  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol]; // For columns 0-23: Fills target rows 2-5 with source rows 0-3
129  }
130  }
131  for (int myrow = 6; myrow<8; myrow++){
132  for (int mycol = 0; mycol<24; mycol++){
133  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol]; // For columns 0-23: Fills target rows 6-8 with source rows 4-5
134  }
135  }
136  for (int myrow = 0; myrow<4; myrow++){
137  for (int mycol = 24; mycol<28; mycol++){
138  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[28+myrow][mycol]; // For columns 24-27: Fills target rows 0-3 with source rows 28-31
139  }
140  }
141  for (int myrow = 4; myrow<12; myrow++){
142  for (int mycol = 24; mycol<28; mycol++){
143  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol]; // For columns 24-27: Fills target rows 4-11 with source rows 0-7
144  }
145  }
146  for (int myrow = 12; myrow<16; myrow++){
147  for (int mycol = 24; mycol<28; mycol++){
148  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol]; // For columns 24-27: Fills target rows 12-15 with source rows 8-11
149  }
150  }
151  for (int myrow = 0; myrow<8; myrow++){
152  for (int mycol = 28; mycol<ncols; mycol++){
153  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[56+myrow][mycol]; // For columns 0-7: Fills target rows 0-7 with source rows 56-63
154  }
155  }
156  for (int myrow = 8; myrow<32; myrow++){
157  for (int mycol = 28; mycol<ncols; mycol++){
158  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-8][mycol]; // For columns 8-END: Fills target rows 8-31 with source rows 0-23
159  }
160  }
161  ATH_CHECK(m_jFEXFPGATool->init(0, m_id));
162  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
163  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
164  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
165  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
166  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
167  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
168  m_sumET_tobWords.push_back(m_jFEXFPGATool->getSumEtTOBs());
169  m_Met_tobWords.push_back(m_jFEXFPGATool->getMetTOBs());
170  m_jFEXFPGATool->reset();
171  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
172 
173  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
174  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
175  // 0.8 -> 4.0 [core is 1.6 to 3.2]
176  for (int myrow = 0; myrow<2; myrow++){
177  for (int mycol = 0; mycol<24; mycol++){
178  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[2+myrow][mycol]; // For columns 0-23: Fills target rows 0-1 with source rows 2-3
179  }
180  }
181  for (int myrow = 2; myrow<6; myrow++){
182  for (int mycol = 0; mycol<24; mycol++){
183  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol]; // For columns 0-23: Fills target rows 2-5 with source rows 4-7
184  }
185  }
186  for (int myrow = 6; myrow<8; myrow++){
187  for (int mycol = 0; mycol<24; mycol++){
188  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol]; // For columns 0-23: Fills target rows 6-8 with source rows 8-9
189  }
190  }
191  for (int myrow = 0; myrow<4; myrow++){
192  for (int mycol = 24; mycol<28; mycol++){
193  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[4+myrow][mycol]; // For columns 24-27: Fills target rows 0-3 with source rows 4-7
194  }
195  }
196  for (int myrow = 4; myrow<12; myrow++){
197  for (int mycol = 24; mycol<28; mycol++){
198  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol]; // For columns 24-27: Fills target rows 4-11 with source rows 8-15
199  }
200  }
201  for (int myrow = 12; myrow<16; myrow++){
202  for (int mycol = 24; mycol<28; mycol++){
203  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol]; // For columns 24-27: Fills target rows 12-15 with source rows 16-19
204  }
205  }
206  for (int myrow = 0; myrow<8; myrow++){
207  for (int mycol = 28; mycol<ncols; mycol++){
208  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[8+myrow][mycol]; // For columns 0-7: Fills target rows 0-7 with source rows 8-15
209  }
210  }
211  for (int myrow = 8; myrow<32; myrow++){
212  for (int mycol = 28; mycol<ncols; mycol++){
213  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+8][mycol]; // For columns 8-END: Fills target rows 8-31 with source rows 16-39
214  }
215  }
216  ATH_CHECK(m_jFEXFPGATool->init(1, m_id));
217  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
218  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
219  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
220  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
221  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
222  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
223  m_jFEXFPGATool->reset();
224  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
225 
226 
227  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
228  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
229  // 2.4 -> 5.6 [core is 3.2 to 4.8]
230  for (int myrow = 0; myrow<2; myrow++){
231  for (int mycol = 0; mycol<24; mycol++){
232  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[6+myrow][mycol]; // For columns 0-23: Fills target rows 0-1 with source rows 6-7
233  }
234  }
235  for (int myrow = 2; myrow<6; myrow++){
236  for (int mycol = 0; mycol<24; mycol++){
237  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol]; // For columns 0-23: Fills target rows 2-5 with source rows 8-11
238  }
239  }
240  for (int myrow = 6; myrow<8; myrow++){
241  for (int mycol = 0; mycol<24; mycol++){
242  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol]; // For columns 0-23: Fills target rows 6-8 with source rows 12-13
243  }
244  }
245  for (int myrow = 0; myrow<4; myrow++){
246  for (int mycol = 24; mycol<28; mycol++){
247  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[12+myrow][mycol]; // For columns 24-27: Fills target rows 0-3 with source rows 12-15
248  }
249  }
250  for (int myrow = 4; myrow<12; myrow++){
251  for (int mycol = 24; mycol<28; mycol++){
252  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol]; // For columns 24-27: Fills target rows 4-11 with source rows 16-23
253  }
254  }
255  for (int myrow = 12; myrow<16; myrow++){
256  for (int mycol = 24; mycol<28; mycol++){
257  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol]; // For columns 24-27: Fills target rows 12-15 with source rows 24-27
258  }
259  }
260  for (int myrow = 0; myrow<8; myrow++){
261  for (int mycol = 28; mycol<ncols; mycol++){
262  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[24+myrow][mycol]; // For columns 0-7: Fills target rows 0-7 with source rows 24-31
263  }
264  }
265  for (int myrow = 8; myrow<32; myrow++){
266  for (int mycol = 28; mycol<ncols; mycol++){
267  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+24][mycol]; // For columns 8-END: Fills target rows 8-31 with source rows 32-55
268  }
269  }
270 
271  //FPGA 2 correcponds to U4, index 3
272  ATH_CHECK(m_jFEXFPGATool->init(3, m_id));
273  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
274  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
275  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
276  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
277  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
278  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
279  m_sumET_tobWords.push_back(m_jFEXFPGATool->getSumEtTOBs());
280  m_Met_tobWords.push_back(m_jFEXFPGATool->getMetTOBs());
281  m_jFEXFPGATool->reset();
282  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
283 
284  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
285  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
286  // 4.0 -> 0.8 [core is 4.8 to 6.4]
287  for (int myrow = 0; myrow<2; myrow++){
288  for (int mycol = 0; mycol<24; mycol++){
289  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[10+myrow][mycol]; // For columns 0-23: Fills target rows 0-1 with source rows 10-11
290  }
291  }
292  for (int myrow = 2; myrow<6; myrow++){
293  for (int mycol = 0; mycol<24; mycol++){
294  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+10][mycol]; // For columns 0-23: Fills target rows 2-5 with source rows 12-15
295  }
296  }
297  for (int myrow = 6; myrow<8; myrow++){
298  for (int mycol = 0; mycol<24; mycol++){
299  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-6][mycol]; // For columns 0-23: Fills target rows 6-8 with source rows 0-1
300  }
301  }
302  for (int myrow = 0; myrow<4; myrow++){
303  for (int mycol = 24; mycol<28; mycol++){
304  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[20+myrow][mycol]; // For columns 24-27: Fills target rows 0-3 with source rows 20-23
305  }
306  }
307  for (int myrow = 4; myrow<12; myrow++){
308  for (int mycol = 24; mycol<28; mycol++){
309  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+20][mycol]; // For columns 24-27: Fills target rows 4-11 with source rows 24-31
310  }
311  }
312  for (int myrow = 12; myrow<16; myrow++){
313  for (int mycol = 24; mycol<28; mycol++){
314  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-12][mycol]; // For columns 24-27: Fills target rows 12-15 with source rows 0-3
315  }
316  }
317  for (int myrow = 0; myrow<24; myrow++){
318  for (int mycol = 28; mycol<ncols; mycol++){
319  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[40+myrow][mycol]; // For columns 0-23: Fills target rows 0-23 with source rows 40-63
320  }
321  }
322  for (int myrow = 24; myrow<32; myrow++){
323  for (int mycol = 28; mycol<ncols; mycol++){
324  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-24][mycol]; // For columns 24-END: Fills target rows 24-31 with source rows 0-8
325  }
326  }
327  //FPGA 3 correcponds to U3, index 2
328  ATH_CHECK(m_jFEXFPGATool->init(2, m_id));
329  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
330  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
331  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
332  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
333  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
334  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
335  m_jFEXFPGATool->reset();
336  //FPGA 3---------------------------------------------------------------------------------------------------------------------------------------------
337 
338  return StatusCode::SUCCESS;
339 
340 }

◆ ExecuteForwardCSide()

StatusCode LVL1::jFEXSim::ExecuteForwardCSide ( int  tmp[2 *FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width],
jFEXOutputCollection *  inputOutputCollection,
const std::pair< unsigned int, const std::vector< int > & > &  jetCalibrationParameters 
)
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 342 of file jFEXSim.cxx.

342  {
343 
344  const int nrows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
345  const int ncols = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width;
346 
347  // So the way this works now is a little awkward due to the forward regions, which have less cells in phi and also overlap a lot.
348  // Interesting that I put nrows = 16*2 here, the documentation (l1caloreqs) looks like it should infact be just 16 (based on Fig 27)
349  // But actually the overlap is I suppose much greater, probably covering a much larger region, in this case 16/2
350  // Yes, this is answered by the few lines just below which specify the exact ranges
351  // Back to the forward regions, which have less cells in phi. We have 2 decisions, we can either fill half the cells in phi, or fill every other cell in phi
352  // For now I will fill every other cell in phi, but realistically the algorithm in the forward region needs to be written in a very different way
353  // and the re-writing on that algorithm will likely impact on how it is written in the central regions too
354  // The new writing of the algorithm will need to use the information from the central point of each tower in the array to check if it falls within a certain radius
355  // it cannot rely on the structure of the array itself at all. As such this algorithm is likely to end up being much less efficient that the eFEX equivalent.
356 
357  int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
358 
359  // FPGA boundaries in phi: 0.0, 1.6, 3.2, 4.8, 6.4
360  // Written explicitly:
361  // 5.6 -> 2.4 [core is 0.0 to 1.6] // FPGA 0
362  // 0.8 -> 4.0 [core is 1.6 to 3.2] // FPGA 1
363  // 2.4 -> 5.6 [core is 3.2 to 4.8] // FPGA 2
364  // 4.0 -> 0.8 [core is 4.8 to 6.4] // FPGA 3
365 
366  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
367  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
368  // 5.6 -> 2.4 [core is 0.0 to 1.6]
369  for (int myrow = 0; myrow<2; myrow++){
370  for (int mycol = ncols-24; mycol<ncols; mycol++){
371  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[14+myrow][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 0-1 with source rows 14-15
372  }
373  }
374  for (int myrow = 2; myrow<6; myrow++){
375  for (int mycol = ncols-24; mycol<ncols; mycol++){
376  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 2-5 with source rows 0-3
377  }
378  }
379  for (int myrow = 6; myrow<8; myrow++){
380  for (int mycol = ncols-24; mycol<ncols; mycol++){
381  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 6-8 with source rows 4-5
382  }
383  }
384  for (int myrow = 0; myrow<4; myrow++){
385  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
386  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[28+myrow][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 0-3 with source rows 28-31
387  }
388  }
389  for (int myrow = 4; myrow<12; myrow++){
390  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
391  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 4-11 with source rows 0-7
392  }
393  }
394  for (int myrow = 12; myrow<16; myrow++){
395  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
396  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 12-15 with source rows 8-11
397  }
398  }
399  for (int myrow = 0; myrow<8; myrow++){
400  for (int mycol = 0; mycol<ncols-28; mycol++){
401  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[56+myrow][mycol]; // For columns 0-7 (mirrored for CSide however): Fills target rows 0-7 with source rows 56-63
402  }
403  }
404  for (int myrow = 8; myrow<32; myrow++){
405  for (int mycol = 0; mycol<ncols-28; mycol++){
406  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-8][mycol]; // For columns 8-END (mirrored for CSide however): Fills target rows 8-31 with source rows 0-23
407  }
408  }
409  ATH_CHECK(m_jFEXFPGATool->init(0, m_id));
410  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
411  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
412  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
413  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
414  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
415  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
416  m_sumET_tobWords.push_back(m_jFEXFPGATool->getSumEtTOBs());
417  m_Met_tobWords.push_back(m_jFEXFPGATool->getMetTOBs());
418  m_jFEXFPGATool->reset();
419  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
420 
421  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
422  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
423  // 0.8 -> 4.0 [core is 1.6 to 3.2]
424  for (int myrow = 0; myrow<2; myrow++){
425  for (int mycol = ncols-24; mycol<ncols; mycol++){
426  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[2+myrow][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 0-1 with source rows 2-3
427  }
428  }
429  for (int myrow = 2; myrow<6; myrow++){
430  for (int mycol = ncols-24; mycol<ncols; mycol++){
431  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 2-5 with source rows 4-7
432  }
433  }
434  for (int myrow = 6; myrow<8; myrow++){
435  for (int mycol = ncols-24; mycol<ncols; mycol++){
436  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 6-8 with source rows 8-9
437  }
438  }
439  for (int myrow = 0; myrow<4; myrow++){
440  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
441  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[4+myrow][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 0-3 with source rows 4-7
442  }
443  }
444  for (int myrow = 4; myrow<12; myrow++){
445  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
446  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 4-11 with source rows 8-15
447  }
448  }
449  for (int myrow = 12; myrow<16; myrow++){
450  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
451  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 12-15 with source rows 16-19
452  }
453  }
454  for (int myrow = 0; myrow<8; myrow++){
455  for (int mycol = 0; mycol<ncols-28; mycol++){
456  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[8+myrow][mycol]; // For columns 0-7 (mirrored for CSide however): Fills target rows 0-7 with source rows 8-15
457  }
458  }
459  for (int myrow = 8; myrow<32; myrow++){
460  for (int mycol = 0; mycol<ncols-28; mycol++){
461  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+8][mycol]; // For columns 8-END (mirrored for CSide however): Fills target rows 8-31 with source rows 16-39
462  }
463  }
464  ATH_CHECK(m_jFEXFPGATool->init(1, m_id));
465  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
466  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
467  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
468  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
469  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
470  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
471  m_jFEXFPGATool->reset();
472  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
473 
474  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
475  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
476  // 2.4 -> 5.6 [core is 3.2 to 4.8]
477  for (int myrow = 0; myrow<2; myrow++){
478  for (int mycol = ncols-24; mycol<ncols; mycol++){
479  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[6+myrow][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 0-1 with source rows 6-7
480  }
481  }
482  for (int myrow = 2; myrow<6; myrow++){
483  for (int mycol = ncols-24; mycol<ncols; mycol++){
484  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 2-5 with source rows 8-11
485  }
486  }
487  for (int myrow = 6; myrow<8; myrow++){
488  for (int mycol = ncols-24; mycol<ncols; mycol++){
489  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 6-8 with source rows 12-13
490  }
491  }
492  for (int myrow = 0; myrow<4; myrow++){
493  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
494  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[12+myrow][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 0-3 with source rows 12-15
495  }
496  }
497  for (int myrow = 4; myrow<12; myrow++){
498  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
499  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 4-11 with source rows 16-23
500  }
501  }
502  for (int myrow = 12; myrow<16; myrow++){
503  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
504  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 12-15 with source rows 24-27
505  }
506  }
507  for (int myrow = 0; myrow<8; myrow++){
508  for (int mycol = 0; mycol<ncols-28; mycol++){
509  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[24+myrow][mycol]; // For columns 0-7 (mirrored for CSide however): Fills target rows 0-7 with source rows 24-31
510  }
511  }
512  for (int myrow = 8; myrow<32; myrow++){
513  for (int mycol = 0; mycol<ncols-28; mycol++){
514  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+24][mycol]; // For columns 8-END (mirrored for CSide however): Fills target rows 8-31 with source rows 32-55
515  }
516  }
517  //FPGA 2 correcponds to U4, index 3
518  ATH_CHECK(m_jFEXFPGATool->init(3, m_id));
519  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
520  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
521  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
522  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
523  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
524  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
525  m_sumET_tobWords.push_back(m_jFEXFPGATool->getSumEtTOBs());
526  m_Met_tobWords.push_back(m_jFEXFPGATool->getMetTOBs());
527  m_jFEXFPGATool->reset();
528  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
529 
530  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
531  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
532  // 4.0 -> 0.8 [core is 4.8 to 6.4]
533  for (int myrow = 0; myrow<2; myrow++){
534  for (int mycol = ncols-24; mycol<ncols; mycol++){
535  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[10+myrow][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 0-1 with source rows 10-11
536  }
537  }
538  for (int myrow = 2; myrow<6; myrow++){
539  for (int mycol = ncols-24; mycol<ncols; mycol++){
540  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+10][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 2-5 with source rows 12-15
541  }
542  }
543  for (int myrow = 6; myrow<8; myrow++){
544  for (int mycol = ncols-24; mycol<ncols; mycol++){
545  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-6][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 6-8 with source rows 0-1
546  }
547  }
548  for (int myrow = 0; myrow<4; myrow++){
549  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
550  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[20+myrow][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 0-3 with source rows 20-23
551  }
552  }
553  for (int myrow = 4; myrow<12; myrow++){
554  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
555  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+20][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 4-11 with source rows 24-31
556  }
557  }
558  for (int myrow = 12; myrow<16; myrow++){
559  for (int mycol = ncols-28; mycol<ncols-24; mycol++){
560  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-12][mycol]; // For columns 24-27 (mirrored for CSide however): Fills target rows 12-15 with source rows 0-3
561  }
562  }
563  for (int myrow = 0; myrow<24; myrow++){
564  for (int mycol = 0; mycol<ncols-28; mycol++){
565  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[40+myrow][mycol]; // For columns 0-23 (mirrored for CSide however): Fills target rows 0-23 with source rows 40-63
566  }
567  }
568  for (int myrow = 24; myrow<32; myrow++){
569  for (int mycol = 0; mycol<ncols-28; mycol++){
570  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-24][mycol]; // For columns 24-END (mirrored for CSide however): Fills target rows 24-31 with source rows 0-8
571  }
572  }
573  //FPGA 3 correcponds to U3, index 2
574  ATH_CHECK(m_jFEXFPGATool->init(2, m_id));
575  m_jFEXFPGATool->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
576  ATH_CHECK(m_jFEXFPGATool->execute(inputOutputCollection, jetCalibrationParameters));
577  m_smallRJet_tobWords.push_back(m_jFEXFPGATool->getSmallRJetTOBs());
578  m_largeRJet_tobWords.push_back(m_jFEXFPGATool->getLargeRJetTOBs());
579  m_tau_tobWords.push_back(m_jFEXFPGATool->getTauTOBs());
580  if (m_id==0 || m_id==5) m_fwdEl_tobWords.push_back(m_jFEXFPGATool->getFwdElTOBs());
581  m_jFEXFPGATool->reset();
582  //FPGA 3---------------------------------------------------------------------------------------------------------------------------------------------
583 
584  return StatusCode::SUCCESS;
585 
586  }

◆ extraDeps_update_handler()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::extraDeps_update_handler ( Gaudi::Details::PropertyBase &  ExtraDeps)
protectedinherited

Add StoreName to extra input/output deps as needed.

use the logic of the VarHandleKey to parse the DataObjID keys supplied via the ExtraInputs and ExtraOuputs Properties to add the StoreName if it's not explicitly given

◆ finalize()

StatusCode LVL1::jFEXSim::finalize ( )
overridevirtual

standard Athena-Algorithm method

Definition at line 44 of file jFEXSim.cxx.

45  {
46  return StatusCode::SUCCESS;
47  }

◆ getFwdElTOBs()

std::vector< std::vector< std::vector< uint32_t > > > LVL1::jFEXSim::getFwdElTOBs ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 798 of file jFEXSim.cxx.

798  {
799 
800  return m_fwdEl_tobWords;
801 
802 }

◆ getLargeRJetTOBs()

std::vector< std::vector< std::unique_ptr< jFEXTOB > > > LVL1::jFEXSim::getLargeRJetTOBs ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 767 of file jFEXSim.cxx.

768 {
769  std::vector< std::vector<std::unique_ptr<jFEXTOB>> > ljTOBs;
770  ljTOBs.clear();
771  ljTOBs.resize(m_largeRJet_tobWords.size());
772 
773  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
774  for (unsigned int i = 0; i < m_largeRJet_tobWords.size(); ++i){
775  for(unsigned int j = 0; j < m_largeRJet_tobWords[i].size(); ++j){
776  ljTOBs.at(i).push_back(std::move(m_largeRJet_tobWords[i][j]));
777  }
778  }
779  return ljTOBs;
780 }

◆ getMetTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXSim::getMetTOBs ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 819 of file jFEXSim.cxx.

819  {
820 
821  std::vector<std::unique_ptr<jFEXTOB>> metTOBs;
822  metTOBs.clear();
823 
824  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
825  for (unsigned int i = 0; i < m_Met_tobWords.size(); ++i){
826  for(unsigned int j = 0; j < m_Met_tobWords[i].size(); ++j){
827  metTOBs.push_back(std::move(m_Met_tobWords[i][j]));
828  }
829  }
830 
831  return metTOBs;
832 }

◆ getSmallRJetTOBs()

std::vector< std::vector< std::unique_ptr< jFEXTOB > > > LVL1::jFEXSim::getSmallRJetTOBs ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 751 of file jFEXSim.cxx.

752 {
753  std::vector< std::vector<std::unique_ptr<jFEXTOB>>> sjTOBs;
754  sjTOBs.clear();
755  sjTOBs.resize(m_smallRJet_tobWords.size());
756 
757  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
758  for (unsigned int i = 0; i < m_smallRJet_tobWords.size(); ++i){
759  for(unsigned int j = 0; j < m_smallRJet_tobWords[i].size(); ++j){
760  sjTOBs.at(i).push_back(std::move(m_smallRJet_tobWords[i][j]));
761  }
762  }
763  return sjTOBs;
764 
765 }

◆ getSumEtTOBs()

std::vector< std::unique_ptr< jFEXTOB > > LVL1::jFEXSim::getSumEtTOBs ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 804 of file jFEXSim.cxx.

804  {
805 
806  std::vector<std::unique_ptr<jFEXTOB>> sumetTOBs;
807  sumetTOBs.clear();
808 
809  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
810  for (unsigned int i = 0; i < m_sumET_tobWords.size(); ++i){
811  for(unsigned int j = 0; j < m_sumET_tobWords[i].size(); ++j){
812  sumetTOBs.push_back(std::move(m_sumET_tobWords[i][j]));
813  }
814  }
815 
816  return sumetTOBs;
817 }

◆ getTauTOBs()

std::vector< std::vector< std::unique_ptr< jFEXTOB > > > LVL1::jFEXSim::getTauTOBs ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 782 of file jFEXSim.cxx.

783 {
784  std::vector< std::vector<std::unique_ptr<jFEXTOB>> > tauTOBs;
785  tauTOBs.clear();
786  tauTOBs.resize(m_tau_tobWords.size());
787 
788  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
789  for (unsigned int i = 0; i < m_tau_tobWords.size(); ++i){
790  for(unsigned int j = 0; j < m_tau_tobWords[i].size(); ++j){
791  tauTOBs.at(i).push_back(std::move(m_tau_tobWords[i][j]));
792  }
793  }
794 
795  return tauTOBs;
796 }

◆ ID()

virtual int LVL1::jFEXSim::ID ( )
inlineoverridevirtual

Implements LVL1::IjFEXSim.

Definition at line 53 of file jFEXSim.h.

53 {return m_id;}

◆ init()

void LVL1::jFEXSim::init ( int  id)
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 81 of file jFEXSim.cxx.

82  {
83  m_id = id;
84  }

◆ initialize()

StatusCode LVL1::jFEXSim::initialize ( )
overridevirtual

standard Athena-Algorithm method

Definition at line 36 of file jFEXSim.cxx.

37  {
38  ATH_CHECK( m_jFEXFPGATool.retrieve() );
39  return StatusCode::SUCCESS;
40  }

◆ inputHandles()

virtual std::vector<Gaudi::DataHandle*> AthCommonDataStore< AthCommonMsg< AlgTool > >::inputHandles ( ) const
overridevirtualinherited

Return this algorithm's input handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ interfaceID()

const InterfaceID & LVL1::IjFEXSim::interfaceID ( )
inlinestaticinherited

Definition at line 62 of file IjFEXSim.h.

63  {
64  return IID_IjFEXSim;
65  }

◆ msg() [1/2]

MsgStream& AthCommonMsg< AlgTool >::msg ( ) const
inlineinherited

Definition at line 24 of file AthCommonMsg.h.

24  {
25  return this->msgStream();
26  }

◆ msg() [2/2]

MsgStream& AthCommonMsg< AlgTool >::msg ( const MSG::Level  lvl) const
inlineinherited

Definition at line 27 of file AthCommonMsg.h.

27  {
28  return this->msgStream(lvl);
29  }

◆ msgLvl()

bool AthCommonMsg< AlgTool >::msgLvl ( const MSG::Level  lvl) const
inlineinherited

Definition at line 30 of file AthCommonMsg.h.

30  {
31  return this->msgLevel(lvl);
32  }

◆ outputHandles()

virtual std::vector<Gaudi::DataHandle*> AthCommonDataStore< AthCommonMsg< AlgTool > >::outputHandles ( ) const
overridevirtualinherited

Return this algorithm's output handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ renounce()

std::enable_if_t<std::is_void_v<std::result_of_t<decltype(&T::renounce)(T)> > && !std::is_base_of_v<SG::VarHandleKeyArray, T> && std::is_base_of_v<Gaudi::DataHandle, T>, void> AthCommonDataStore< AthCommonMsg< AlgTool > >::renounce ( T &  h)
inlineprotectedinherited

Definition at line 380 of file AthCommonDataStore.h.

381  {
382  h.renounce();
383  PBASE::renounce (h);
384  }

◆ renounceArray()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::renounceArray ( SG::VarHandleKeyArray &  handlesArray)
inlineprotectedinherited

remove all handles from I/O resolution

Definition at line 364 of file AthCommonDataStore.h.

364  {
365  handlesArray.renounce();
366  }

◆ reset()

void LVL1::jFEXSim::reset ( )
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 50 of file jFEXSim.cxx.

51  {
52 
53  m_id = -1;
54  m_jFEXFPGACollection.clear();
55 
56  int rows = sizeof m_jTowersIDs_Thin / sizeof m_jTowersIDs_Thin[0];
57  int cols = sizeof m_jTowersIDs_Thin[0] / sizeof m_jTowersIDs_Thin[0][0];
58  for (int i=0; i<rows; i++){
59  for (int j=0; j<cols; j++){
60  m_jTowersIDs_Thin[i][j] = 0;
61  }
62  }
63 
64 
65  rows = sizeof m_jTowersIDs_Wide / sizeof m_jTowersIDs_Wide[0];
66  cols = sizeof m_jTowersIDs_Wide[0] / sizeof m_jTowersIDs_Wide[0][0];
67  for (int i=0; i<rows; i++){
68  for (int j=0; j<cols; j++){
69  m_jTowersIDs_Wide[i][j] = 0;
70  }
71  }
72 
73  m_smallRJet_tobWords.clear();
74  m_tau_tobWords.clear();
75  m_fwdEl_tobWords.clear();
76  m_largeRJet_tobWords.clear();
77  m_sumET_tobWords.clear();
78  m_Met_tobWords.clear();
79  }

◆ SetTowersAndCells_SG() [1/2]

void LVL1::jFEXSim::SetTowersAndCells_SG ( int  tmp[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 837 of file jFEXSim.cxx.

837  { // METHOD USING ONLY IDS
838 
839  const int nrows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
840  const int ncols = FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width;
841 
842  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(nrows*ncols),&m_jTowersIDs_Thin[0][0]);
843 
844  int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
845 
846  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
847  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
848  for (int myrow = 0; myrow<nrows; myrow++){
849  for (int mycol = 0; mycol<ncols; mycol++){
850  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
851  }
852  }
853  m_jFEXFPGACollection.at(0)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
854  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
855 
856  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
857  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
858  for (int myrow = nrows; myrow<nrows*2; myrow++){
859  for (int mycol = 0; mycol<ncols; mycol++){
860  tmp_jTowersIDs_subset_FPGA[myrow-nrows][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
861  }
862  }
863  m_jFEXFPGACollection.at(1)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
864  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
865 
866 
867  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
868  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
869  for (int myrow = nrows*2; myrow<nrows*3; myrow++){
870  for (int mycol = 0; mycol<ncols; mycol++){
871  tmp_jTowersIDs_subset_FPGA[myrow-(nrows*2)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
872  }
873  }
874  m_jFEXFPGACollection.at(2)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
875  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
876 
877  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
878  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
879  for (int myrow = nrows*3; myrow<nrows*4; myrow++){
880  for (int mycol = 0; mycol<ncols; mycol++){
881  tmp_jTowersIDs_subset_FPGA[myrow-(nrows*3)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
882  }
883  }
884  m_jFEXFPGACollection.at(3)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
885  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
886 
887  }

◆ SetTowersAndCells_SG() [2/2]

void LVL1::jFEXSim::SetTowersAndCells_SG ( int  tmp[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXSim.

Definition at line 698 of file jFEXSim.cxx.

698  { // METHOD USING ONLY IDS
699 
700  const int nrows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
701  const int ncols = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width;
702  // We may need a function along the lines of "SetForwardTowersAndCells_SG"(int tmp_jTowerIDs_subset[16][28]
703 
704  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(nrows*ncols),&m_jTowersIDs_Wide[0][0]);
705 
706  int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
707 
708  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
709  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
710  for (int myrow = 0; myrow<nrows; myrow++){
711  for (int mycol = 0; mycol<ncols; mycol++){
712  tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
713  }
714  }
715  m_jFEXFPGACollection.at(0)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
716  //FPGA 0----------------------------------------------------------------------------------------------------------------------------------------------
717 
718  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
719  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
720  for (int myrow = nrows; myrow<nrows*2; myrow++){
721  for (int mycol = 0; mycol<ncols; mycol++){
722  tmp_jTowersIDs_subset_FPGA[myrow-nrows][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
723  }
724  }
725  m_jFEXFPGACollection.at(1)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
726  //FPGA 1----------------------------------------------------------------------------------------------------------------------------------------------
727 
728 
729  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
730  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
731  for (int myrow = nrows*2; myrow<nrows*3; myrow++){
732  for (int mycol = 0; mycol<ncols; mycol++){
733  tmp_jTowersIDs_subset_FPGA[myrow-(nrows*2)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
734  }
735  }
736  m_jFEXFPGACollection.at(2)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
737  //FPGA 2----------------------------------------------------------------------------------------------------------------------------------------------
738 
739  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
740  memset(tmp_jTowersIDs_subset_FPGA, 0, sizeof tmp_jTowersIDs_subset_FPGA);
741  for (int myrow = nrows*3; myrow<nrows*4; myrow++){
742  for (int mycol = 0; mycol<ncols; mycol++){
743  tmp_jTowersIDs_subset_FPGA[myrow-(nrows*3)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
744  }
745  }
746  m_jFEXFPGACollection.at(3)->SetTowersAndCells_SG(tmp_jTowersIDs_subset_FPGA);
747  //FPGA 3----------------------------------------------------------------------------------------------------------------------------------------------
748 
749 }

◆ sysInitialize()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysInitialize ( )
overridevirtualinherited

Perform system initialization for an algorithm.

We override this to declare all the elements of handle key arrays at the end of initialization. See comments on updateVHKA.

Reimplemented in DerivationFramework::CfAthAlgTool, AthCheckedComponent< AthAlgTool >, AthCheckedComponent<::AthAlgTool >, and asg::AsgMetadataTool.

◆ sysStart()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysStart ( )
overridevirtualinherited

Handle START transition.

We override this in order to make sure that conditions handle keys can cache a pointer to the conditions container.

◆ updateVHKA()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::updateVHKA ( Gaudi::Details::PropertyBase &  )
inlineinherited

Definition at line 308 of file AthCommonDataStore.h.

308  {
309  // debug() << "updateVHKA for property " << p.name() << " " << p.toString()
310  // << " size: " << m_vhka.size() << endmsg;
311  for (auto &a : m_vhka) {
312  std::vector<SG::VarHandleKey*> keys = a->keys();
313  for (auto k : keys) {
314  k->setOwner(this);
315  }
316  }
317  }

Member Data Documentation

◆ m_detStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_detStore
privateinherited

Pointer to StoreGate (detector store by default)

Definition at line 393 of file AthCommonDataStore.h.

◆ m_evtStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_evtStore
privateinherited

Pointer to StoreGate (event store by default)

Definition at line 390 of file AthCommonDataStore.h.

◆ m_fwdEl_tobWords

std::vector<std::vector<std::vector<uint32_t> > > LVL1::jFEXSim::m_fwdEl_tobWords
private

Definition at line 82 of file jFEXSim.h.

◆ m_id

int LVL1::jFEXSim::m_id
private

Internal data.

Definition at line 74 of file jFEXSim.h.

◆ m_jFEXFPGACollection

std::vector<jFEXFPGA*> LVL1::jFEXSim::m_jFEXFPGACollection
private

Definition at line 80 of file jFEXSim.h.

◆ m_jFEXFPGATool

ToolHandle<IjFEXFPGA> LVL1::jFEXSim::m_jFEXFPGATool {this, "jFEXFPGATool", "LVL1::jFEXFPGA", "Tool that simulates the FPGA hardware"}
private

Definition at line 84 of file jFEXSim.h.

◆ m_jTowersColl

std::unordered_map<int,jTower> LVL1::jFEXSim::m_jTowersColl
private

Definition at line 78 of file jFEXSim.h.

◆ m_jTowersIDs_Thin

int LVL1::jFEXSim::m_jTowersIDs_Thin[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]
private

Definition at line 76 of file jFEXSim.h.

◆ m_jTowersIDs_Wide

int LVL1::jFEXSim::m_jTowersIDs_Wide[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]
private

Definition at line 75 of file jFEXSim.h.

◆ m_largeRJet_tobWords

std::vector< std::vector<std::unique_ptr<jFEXTOB> > > LVL1::jFEXSim::m_largeRJet_tobWords
private

Definition at line 89 of file jFEXSim.h.

◆ m_Met_tobWords

std::vector< std::vector<std::unique_ptr<jFEXTOB> > > LVL1::jFEXSim::m_Met_tobWords
private

Definition at line 91 of file jFEXSim.h.

◆ m_sCellsCollection

CaloCellContainer LVL1::jFEXSim::m_sCellsCollection
private

Definition at line 79 of file jFEXSim.h.

◆ m_smallRJet_tobWords

std::vector< std::vector<std::unique_ptr<jFEXTOB> > > LVL1::jFEXSim::m_smallRJet_tobWords
private

Definition at line 88 of file jFEXSim.h.

◆ m_sumET_tobWords

std::vector< std::vector<std::unique_ptr<jFEXTOB> > > LVL1::jFEXSim::m_sumET_tobWords
private

Definition at line 90 of file jFEXSim.h.

◆ m_tau_tobWords

std::vector< std::vector<std::unique_ptr<jFEXTOB> > > LVL1::jFEXSim::m_tau_tobWords
private

Definition at line 87 of file jFEXSim.h.

◆ m_varHandleArraysDeclared

bool AthCommonDataStore< AthCommonMsg< AlgTool > >::m_varHandleArraysDeclared
privateinherited

Definition at line 399 of file AthCommonDataStore.h.

◆ m_vhka

std::vector<SG::VarHandleKeyArray*> AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
privateinherited

Definition at line 398 of file AthCommonDataStore.h.

The documentation for this class was generated from the following files:
python.PerfMonSerializer.p
def p
Definition: PerfMonSerializer.py:743
LVL1::jFEXSim::m_id
int m_id
Internal data.
Definition: jFEXSim.h:74
LVL1::FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width
constexpr static int jFEX_thin_algoSpace_width
Definition: FEXAlgoSpaceDefs.h:26
AthCommonDataStore::declareProperty
Gaudi::Details::PropertyBase & declareProperty(Gaudi::Property< T > &t)
Definition: AthCommonDataStore.h:145
LVL1::jFEXSim::m_largeRJet_tobWords
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_largeRJet_tobWords
Definition: jFEXSim.h:89
LVL1::jFEXSim::m_jFEXFPGACollection
std::vector< jFEXFPGA * > m_jFEXFPGACollection
Definition: jFEXSim.h:80
AthCommonDataStore< AthCommonMsg< AlgTool > >::m_evtStore
StoreGateSvc_t m_evtStore
Pointer to StoreGate (event store by default)
Definition: AthCommonDataStore.h:390
AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
std::vector< SG::VarHandleKeyArray * > m_vhka
Definition: AthCommonDataStore.h:398
LVL1::FEXAlgoSpaceDefs::jFEX_algoSpace_height
constexpr static int jFEX_algoSpace_height
Definition: FEXAlgoSpaceDefs.h:27
read_hist_ntuple.t
t
Definition: read_hist_ntuple.py:5
SG::VarHandleKeyArray::setOwner
virtual void setOwner(IDataHandleHolder *o)=0
beamspotnt.cols
list cols
Definition: bin/beamspotnt.py:1114
AthCommonDataStore
Definition: AthCommonDataStore.h:52
ATH_MSG_ERROR
#define ATH_MSG_ERROR(x)
Definition: AthMsgStreamMacros.h:33
lumiFormat.i
int i
Definition: lumiFormat.py:92
LVL1::FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width
constexpr static int jFEX_wide_algoSpace_width
Definition: FEXAlgoSpaceDefs.h:25
test_pyathena.parent
parent
Definition: test_pyathena.py:15
ATH_CHECK
#define ATH_CHECK
Definition: AthCheckMacros.h:40
beamspotnt.rows
list rows
Definition: bin/beamspotnt.py:1112
AthCommonDataStore< AthCommonMsg< AlgTool > >::m_detStore
StoreGateSvc_t m_detStore
Pointer to StoreGate (detector store by default)
Definition: AthCommonDataStore.h:393
LVL1::jFEXSim::m_Met_tobWords
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_Met_tobWords
Definition: jFEXSim.h:91
AthAlgTool::AthAlgTool
AthAlgTool()
Default constructor:
SG::VarHandleKeyArray::renounce
virtual void renounce()=0
SG::HandleClassifier::type
std::conditional< std::is_base_of< SG::VarHandleKeyArray, T >::value, VarHandleKeyArrayType, type2 >::type type
Definition: HandleClassifier.h:54
merge_scale_histograms.doc
string doc
Definition: merge_scale_histograms.py:9
id
SG::auxid_t id
Definition: Control/AthContainers/Root/debug.cxx:191
name
std::string name
Definition: Control/AthContainers/Root/debug.cxx:192
LVL1::jFEXSim::m_jFEXFPGATool
ToolHandle< IjFEXFPGA > m_jFEXFPGATool
Definition: jFEXSim.h:84
a
TList * a
Definition: liststreamerinfos.cxx:10
h
python.CaloScaleNoiseConfig.type
type
Definition: CaloScaleNoiseConfig.py:78
LVL1::jFEXSim::m_sumET_tobWords
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_sumET_tobWords
Definition: jFEXSim.h:90
SG::VarHandleBase::vhKey
SG::VarHandleKey & vhKey()
Return a non-const reference to the HandleKey.
Definition: StoreGate/src/VarHandleBase.cxx:616
declareProperty
#define declareProperty(n, p, h)
Definition: BaseFakeBkgTool.cxx:15
python.Bindings.keys
keys
Definition: Control/AthenaPython/python/Bindings.py:790
calibdata.copy
bool copy
Definition: calibdata.py:27
LVL1::jFEXSim::m_jTowersIDs_Wide
int m_jTowersIDs_Wide[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]
Definition: jFEXSim.h:75
LVL1::jFEXSim::m_tau_tobWords
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_tau_tobWords
Definition: jFEXSim.h:87
LVL1::jFEXSim::m_jTowersIDs_Thin
int m_jTowersIDs_Thin[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]
Definition: jFEXSim.h:76
LVL1::jFEXSim::m_smallRJet_tobWords
std::vector< std::vector< std::unique_ptr< jFEXTOB > > > m_smallRJet_tobWords
Definition: jFEXSim.h:88
AthCommonDataStore::declareGaudiProperty
Gaudi::Details::PropertyBase & declareGaudiProperty(Gaudi::Property< T > &hndl, const SG::VarHandleKeyType &)
specialization for handling Gaudi::Property<SG::VarHandleKey>
Definition: AthCommonDataStore.h:156
LVL1::jFEXSim::m_fwdEl_tobWords
std::vector< std::vector< std::vector< uint32_t > > > m_fwdEl_tobWords
Definition: jFEXSim.h:82
fitman.k
k
Definition: fitman.py:528
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