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LVL1::jFEXPileupAndNoise Class Reference

#include <jFEXPileupAndNoise.h>

Inheritance diagram for LVL1::jFEXPileupAndNoise:
Collaboration diagram for LVL1::jFEXPileupAndNoise:

Public Member Functions

 jFEXPileupAndNoise (const std::string &type, const std::string &name, const IInterface *parent)
 Constructors.
virtual StatusCode initialize () override
 standard Athena-Algorithm method
virtual StatusCode safetyTest () override
virtual StatusCode reset () override
virtual void setup (int FPGA[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]) override
virtual void setup (int FPGA[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]) override
virtual std::unordered_map< int, std::vector< int > > GetEt_values () override
virtual std::unordered_map< int, std::vector< int > > Get_EM_Et_values () override
virtual std::unordered_map< int, std::vector< int > > Get_HAD_Et_values () override
virtual ~jFEXPileupAndNoise ()
 Destructor.
virtual std::vector< int > CalculatePileup () override
virtual StatusCode ApplyPileup () override
virtual void ApplyNoise2Jets (bool b) override
virtual void ApplyNoise2Met (bool b) override
ServiceHandle< StoreGateSvc > & evtStore ()
 The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.
const ServiceHandle< StoreGateSvc > & detStore () const
 The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.
virtual StatusCode sysInitialize () override
 Perform system initialization for an algorithm.
virtual StatusCode sysStart () override
 Handle START transition.
virtual std::vector< Gaudi::DataHandle * > inputHandles () const override
 Return this algorithm's input handles.
virtual std::vector< Gaudi::DataHandle * > outputHandles () const override
 Return this algorithm's output handles.
Gaudi::Details::PropertyBase & declareProperty (Gaudi::Property< T, V, H > &t)
void updateVHKA (Gaudi::Details::PropertyBase &)
MsgStream & msg () const
bool msgLvl (const MSG::Level lvl) const

Static Public Member Functions

static const InterfaceID & interfaceID ()

Protected Member Functions

void renounceArray (SG::VarHandleKeyArray &handlesArray)
 remove all handles from I/O resolution
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > renounce (T &h)
void extraDeps_update_handler (Gaudi::Details::PropertyBase &ExtraDeps)
 Add StoreName to extra input/output deps as needed.

Private Types

typedef ServiceHandle< StoreGateSvcStoreGateSvc_t

Private Member Functions

void reset_conters ()
void SubtractPileup ()
void ApplyNoiseCuts (std::unordered_map< int, std::vector< int > > &map_Etvalues, int layer)
int rhoDivLUT (int ntowers)
int getTTowerEta (const LVL1::jTower *tmpTower)
int getTTowerET (const LVL1::jTower *tmpTower)
int getET_EM (const LVL1::jTower *tmpTower)
int getET_HAD (const LVL1::jTower *tmpTower)
int getTTArea_EM (const LVL1::jTower *tmpTower)
int getTTArea_HAD (const LVL1::jTower *tmpTower)
int getTTAreaINV_EM (const LVL1::jTower *tmpTower)
int getTTAreaINV_HAD (const LVL1::jTower *tmpTower)
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyType &)
 specialization for handling Gaudi::Property<SG::VarHandleKey>

Private Attributes

SG::ReadHandleKey< LVL1::jTowerContainerm_jTowerContainerKey {this, "MyjTowers", "jTowerContainer", "Input container for jTowers"}
SG::ReadHandle< jTowerContainerm_jTowerContainer
SG::ReadCondHandleKey< jFEXDBCondDatam_BDToolKey {this, "BDToolKey", "jFEXDBParams", "DB tool key"}
int m_FPGA_central [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] ={{0}}
int m_FPGA_forward [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] ={{0}}
int m_etaMAX =0
std::unordered_map< int, int > m_FPGA_ET_EM
std::unordered_map< int, int > m_FPGA_ET_HAD
int m_rho_EM = 0
int m_rho_HAD1 = 0
int m_rho_HAD2 = 0
int m_rho_HAD3 = 0
int m_rho_FCAL = 0
int m_count_rho_EM = 0
int m_count_rho_HAD1 = 0
int m_count_rho_HAD2 = 0
int m_count_rho_HAD3 = 0
int m_count_rho_FCAL = 0
bool m_is_FWD = false
bool m_apply_pileup2jets = false
bool m_apply_pileup2met = false
bool m_apply_noise2jets = false
bool m_apply_noise2met = false
std::unordered_map< int, std::vector< int > > m_map_Etvalues_EM
std::unordered_map< int, std::vector< int > > m_map_Etvalues_HAD
StoreGateSvc_t m_evtStore
 Pointer to StoreGate (event store by default)
StoreGateSvc_t m_detStore
 Pointer to StoreGate (detector store by default)
std::vector< SG::VarHandleKeyArray * > m_vhka
bool m_varHandleArraysDeclared

Detailed Description

Definition at line 26 of file jFEXPileupAndNoise.h.

Member Typedef Documentation

◆ StoreGateSvc_t

typedef ServiceHandle<StoreGateSvc> AthCommonDataStore< AthCommonMsg< AlgTool > >::StoreGateSvc_t
privateinherited

Definition at line 388 of file AthCommonDataStore.h.

Constructor & Destructor Documentation

◆ jFEXPileupAndNoise()

LVL1::jFEXPileupAndNoise::jFEXPileupAndNoise ( const std::string & type,
const std::string & name,
const IInterface * parent )

Constructors.

Definition at line 21 of file jFEXPileupAndNoise.cxx.

21 : AthAlgTool(type, name, parent) {
22 declareInterface<IjFEXPileupAndNoise>(this);
23}
AthAlgTool()
Default constructor:

◆ ~jFEXPileupAndNoise()

LVL1::jFEXPileupAndNoise::~jFEXPileupAndNoise ( )
virtual

Destructor.

Definition at line 26 of file jFEXPileupAndNoise.cxx.

26 {
27}

Member Function Documentation

◆ ApplyNoise2Jets()

void LVL1::jFEXPileupAndNoise::ApplyNoise2Jets ( bool b)
overridevirtual

◆ ApplyNoise2Met()

void LVL1::jFEXPileupAndNoise::ApplyNoise2Met ( bool b)
overridevirtual

Implements LVL1::IjFEXPileupAndNoise.

Definition at line 287 of file jFEXPileupAndNoise.cxx.

◆ ApplyNoiseCuts()

void LVL1::jFEXPileupAndNoise::ApplyNoiseCuts ( std::unordered_map< int, std::vector< int > > & map_Etvalues,
int layer )
private

Definition at line 397 of file jFEXPileupAndNoise.cxx.

397 {
398
399 const LVL1::jTower *tmpTower;
400
401 for(auto [key,vec] : map_Etvalues){
402
403 tmpTower = m_jTowerContainer->findTower(key);
404 int Jet_NoiseCut = tmpTower->getNoiseForJet(layer);
405 int Met_NoiseCut = tmpTower->getNoiseForMet(layer);
406
407 if(m_apply_noise2jets && map_Etvalues[key][0]<=Jet_NoiseCut){ // Et for jets
408 map_Etvalues[key][0]=0.;
409 }
410 if(m_apply_noise2met && map_Etvalues[key][1]<=Met_NoiseCut){ // Et for Met
411 map_Etvalues[key][1]=0.;
412 }
413
414 }
415
416}
std::vector< size_t > vec
SG::ReadHandle< jTowerContainer > m_jTowerContainer
int getNoiseForJet(int layer) const
Definition jTower.cxx:347
int getNoiseForMet(int layer) const
Definition jTower.cxx:338

◆ ApplyPileup()

StatusCode LVL1::jFEXPileupAndNoise::ApplyPileup ( )
overridevirtual

Implements LVL1::IjFEXPileupAndNoise.

Definition at line 270 of file jFEXPileupAndNoise.cxx.

270 {
271 SG::ReadCondHandle<jFEXDBCondData> myDBTool = SG::ReadCondHandle<jFEXDBCondData>(m_BDToolKey);
272 if(! myDBTool.isValid()) {
273 ATH_MSG_ERROR("Could not retrieve DB tool " << m_BDToolKey);
274 return StatusCode::FAILURE;
275 }
276
277 m_apply_pileup2jets = myDBTool->get_doPileUpJet();
278 m_apply_pileup2met = myDBTool->get_doPileUpMet();
279
280 return StatusCode::SUCCESS;
281}
#define ATH_MSG_ERROR(x)
SG::ReadCondHandleKey< jFEXDBCondData > m_BDToolKey

◆ CalculatePileup()

std::vector< int > LVL1::jFEXPileupAndNoise::CalculatePileup ( )
overridevirtual

Implements LVL1::IjFEXPileupAndNoise.

Definition at line 100 of file jFEXPileupAndNoise.cxx.

100 {
101
103
104 SG::ReadCondHandle<jFEXDBCondData> myDBTool = SG::ReadCondHandle<jFEXDBCondData>(m_BDToolKey/*, ctx*/);
105 if(! myDBTool.isValid()) {
106 ATH_MSG_ERROR("Could not retrieve DB tool " << m_BDToolKey);
107 }
108
109 for(int iphi=0;iphi<FEXAlgoSpaceDefs::jFEX_algoSpace_height;iphi++){
110 for(int ieta=0;ieta<m_etaMAX;ieta++){
111
112 int TTID = 0;
113
114 if(m_is_FWD){
115 TTID = m_FPGA_forward[iphi][ieta];
116 }
117 else{
118 TTID = m_FPGA_central[iphi][ieta];
119 }
120
121 if(TTID == 0){
122 continue; //skipping TTID iqual to 0
123 }
124
125 const LVL1::jTower *tmpTower = m_jTowerContainer->findTower(TTID);
126
127 int tmp_eta = getTTowerEta(tmpTower);
128 // energies used below are in MeV, but to reproduce firmware behavior we need to truncate at the same position,
129 // i.e., temporarily go back to the granularity used in firmware!
130 int em_granularity = 25;
131 int had_granularity = tmp_eta < 15 ? 500 : 25; //For Tile inputs granularity is 500MeV, for LAr 25MeV
132 //storing the energies
133 int tmp_energy_EM = getET_EM(tmpTower)/em_granularity;
134 int tmp_energy_HAD = getET_HAD(tmpTower)/had_granularity;
135 int tmp_EM_AreaINV = getTTAreaINV_EM(tmpTower);
136 int tmp_HD_AreaINV = getTTAreaINV_HAD(tmpTower);
137 m_FPGA_ET_EM[TTID] = getET_EM(tmpTower);
138 m_FPGA_ET_HAD[TTID] = getET_HAD(tmpTower);
139
140 tmp_energy_EM = (tmp_energy_EM * tmp_EM_AreaINV)/(1<<FEXAlgoSpaceDefs::pu_AreaINV);
141 tmp_energy_HAD= (tmp_energy_HAD* tmp_HD_AreaINV)/(1<<FEXAlgoSpaceDefs::pu_AreaINV);
142
143 //calculating rho's
144
145 // EM layer ( not EM FCAL!! )
146
147 if(tmp_eta < 32 ){
148 if(tmp_energy_EM > myDBTool->get_PUThrLowEm() and tmp_energy_EM < myDBTool->get_PUThrHighEm()) {
149 m_rho_EM += tmp_energy_EM;
151 }
152 }
153
154 // Tile layer
155 if(tmp_eta < 15){
156 if(tmp_energy_HAD > myDBTool->get_PUThrLowHadTrex() and tmp_energy_HAD < myDBTool->get_PUThrHighHadTrex()){
157 m_rho_HAD1 += tmp_energy_HAD;
159 }
160 }
161 // HEC Overlap layer!
162 else if(tmp_eta < 16 ){
163 if(tmp_energy_HAD > myDBTool->get_PUThrLowHadHecOverlap() and tmp_energy_HAD < myDBTool->get_PUThrHighHadHecOverlap()){
164 m_rho_HAD2 += tmp_energy_HAD;
166 }
167 }
168 // Rest of HEC without overlap
169 else if(tmp_eta < 32 ){
170 if(tmp_energy_HAD > myDBTool->get_PUThrLowHadLar() and tmp_energy_HAD < myDBTool->get_PUThrHighHadLar()){
171 m_rho_HAD3 += tmp_energy_HAD;
173 }
174 }
175 // FCAL is treated here!
176 else if(tmp_eta >= 32){
177
178 // Contributes the HAD layer (FCAL2 and FCAL3)
180 if(tmp_energy_HAD > myDBTool->get_PUThrLowFcal() and tmp_energy_HAD < myDBTool->get_PUThrHighFcal()){
181 m_rho_FCAL += tmp_energy_HAD;
183 }
184 }
185 // FCAL1 is EM layer so the energy is suposed to be in the EM layer
186 else{
187 if(tmp_energy_EM > myDBTool->get_PUThrLowFcal() and tmp_energy_EM < myDBTool->get_PUThrHighFcal()){
188 m_rho_FCAL += tmp_energy_EM;
190 }
191 }
192 }
193 }
194 }//end of iphi loop
195
196 //calculating rho values for each region
202
203 //return values in MeV -> m_rho_HAD1 corresponds to TileCal, so 500MeV/count, rest is 25MeV/count
204 //note: do not convert the internal values yet, this needs to happen after the PU correction is applied
205 // to fully reproduce FW behavior!
206 std::vector<int> rho_values {m_rho_EM*25,m_rho_HAD1*500,m_rho_HAD2*25,m_rho_HAD3*25,m_rho_FCAL*25};
207
209
210 return rho_values;
211}
static constexpr unsigned int pu_AreaINV
static constexpr unsigned int pu_rhoLUT
static constexpr int jFEX_FCAL2_start
static constexpr int jFEX_algoSpace_height
std::unordered_map< int, int > m_FPGA_ET_EM
int m_FPGA_central[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]
std::unordered_map< int, int > m_FPGA_ET_HAD
int getET_HAD(const LVL1::jTower *tmpTower)
int getTTowerEta(const LVL1::jTower *tmpTower)
int getTTAreaINV_EM(const LVL1::jTower *tmpTower)
int getET_EM(const LVL1::jTower *tmpTower)
int getTTAreaINV_HAD(const LVL1::jTower *tmpTower)
int m_FPGA_forward[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]

◆ declareGaudiProperty()

Gaudi::Details::PropertyBase & AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T, V, H > & hndl,
const SG::VarHandleKeyType &  )
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKey>

Definition at line 156 of file AthCommonDataStore.h.

158 {
160 hndl.value(),
161 hndl.documentation());
162
163 }
Gaudi::Details::PropertyBase & declareProperty(Gaudi::Property< T, V, H > &t)

◆ declareProperty()

Gaudi::Details::PropertyBase & AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( Gaudi::Property< T, V, H > & t)
inlineinherited

Definition at line 145 of file AthCommonDataStore.h.

145 {
146 typedef typename SG::HandleClassifier<T>::type htype;
148 }
Gaudi::Details::PropertyBase & declareGaudiProperty(Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyType &)
specialization for handling Gaudi::Property<SG::VarHandleKey>

◆ detStore()

const ServiceHandle< StoreGateSvc > & AthCommonDataStore< AthCommonMsg< AlgTool > >::detStore ( ) const
inlineinherited

The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 95 of file AthCommonDataStore.h.

◆ evtStore()

ServiceHandle< StoreGateSvc > & AthCommonDataStore< AthCommonMsg< AlgTool > >::evtStore ( )
inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 85 of file AthCommonDataStore.h.

◆ extraDeps_update_handler()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::extraDeps_update_handler ( Gaudi::Details::PropertyBase & ExtraDeps)
protectedinherited

Add StoreName to extra input/output deps as needed.

use the logic of the VarHandleKey to parse the DataObjID keys supplied via the ExtraInputs and ExtraOuputs Properties to add the StoreName if it's not explicitly given

◆ Get_EM_Et_values()

std::unordered_map< int, std::vector< int > > LVL1::jFEXPileupAndNoise::Get_EM_Et_values ( )
overridevirtual

Implements LVL1::IjFEXPileupAndNoise.

Definition at line 293 of file jFEXPileupAndNoise.cxx.

293 {
294
295 // map for energies sent to the FPGA
296 m_map_Etvalues_EM.clear();
297
298
299 for(int iphi=0; iphi<FEXAlgoSpaceDefs::jFEX_algoSpace_height; iphi++) {
300 for(int ieta=0; ieta<m_etaMAX; ieta++) {
301
302 int TTID = 0;
303
304 if(m_is_FWD) {
305 TTID = m_FPGA_forward[iphi][ieta];
306 }
307 else {
308 TTID = m_FPGA_central[iphi][ieta];
309 }
310
311 if(TTID == 0) continue; //skipping TTID iqual to 0
312 const LVL1::jTower *tmpTower = m_jTowerContainer->findTower(TTID);
313
314 // tmp variable to fill the map
315 std::vector<int> v_energies;
316 v_energies.clear();
317 v_energies.resize(2,0);
318
319 //saving the SG energy
320 int tmp_TotalEt_jet=getET_EM(tmpTower);
321 int tmp_TotalEt_met=getET_EM(tmpTower);
322
323 // if true changing the raw energy to the pileup subtracted energy for jets
325 tmp_TotalEt_jet = m_FPGA_ET_EM[TTID];
326 }
327
328 // if true changing the raw energy to the pileup subtracted energy for met
330 tmp_TotalEt_met = m_FPGA_ET_EM[TTID];
331 }
332
333 v_energies[0]=tmp_TotalEt_jet;
334 v_energies[1]=tmp_TotalEt_met;
335
336 m_map_Etvalues_EM.insert(std::make_pair(TTID, v_energies));
337 }
338 }
339
341
342 return m_map_Etvalues_EM;
343}
std::unordered_map< int, std::vector< int > > m_map_Etvalues_EM
void ApplyNoiseCuts(std::unordered_map< int, std::vector< int > > &map_Etvalues, int layer)

◆ Get_HAD_Et_values()

std::unordered_map< int, std::vector< int > > LVL1::jFEXPileupAndNoise::Get_HAD_Et_values ( )
overridevirtual

Implements LVL1::IjFEXPileupAndNoise.

Definition at line 345 of file jFEXPileupAndNoise.cxx.

345 {
346
347 // map for energies sent to the FPGA
348 m_map_Etvalues_HAD.clear();
349
350
351 for(int iphi=0; iphi<FEXAlgoSpaceDefs::jFEX_algoSpace_height; iphi++) {
352 for(int ieta=0; ieta<m_etaMAX; ieta++) {
353
354 int TTID = 0;
355
356 if(m_is_FWD) {
357 TTID = m_FPGA_forward[iphi][ieta];
358 }
359 else {
360 TTID = m_FPGA_central[iphi][ieta];
361 }
362
363 if(TTID == 0) continue; //skipping TTID iqual to 0
364 const LVL1::jTower *tmpTower = m_jTowerContainer->findTower(TTID);
365
366 // tmp variable to fill the map
367 std::vector<int> v_energies;
368 v_energies.clear();
369 v_energies.resize(2,0);
370
371 //saving the SG energy
372 int tmp_TotalEt_jet=getET_HAD(tmpTower);
373 int tmp_TotalEt_met=getET_HAD(tmpTower);
374
375 // if true changing the raw energy to the pileup subtracted energy for jets
377 tmp_TotalEt_jet = m_FPGA_ET_HAD[TTID];
378 }
379
380 // if true changing the raw energy to the pileup subtracted energy for met
382 tmp_TotalEt_met = m_FPGA_ET_HAD[TTID];
383 }
384
385 v_energies[0]=tmp_TotalEt_jet;
386 v_energies[1]=tmp_TotalEt_met;
387
388 m_map_Etvalues_HAD.insert(std::make_pair(TTID, v_energies));
389 }
390 }
391
393
394 return m_map_Etvalues_HAD;
395}
std::unordered_map< int, std::vector< int > > m_map_Etvalues_HAD

◆ getET_EM()

int LVL1::jFEXPileupAndNoise::getET_EM ( const LVL1::jTower * tmpTower)
private

Definition at line 454 of file jFEXPileupAndNoise.cxx.

454 {
455 return tmpTower->getET_EM();
456}
int getET_EM() const
Get EM ET value in MeV.
Definition jTower.h:131

◆ getET_HAD()

int LVL1::jFEXPileupAndNoise::getET_HAD ( const LVL1::jTower * tmpTower)
private

Definition at line 458 of file jFEXPileupAndNoise.cxx.

458 {
459 return tmpTower->getET_HAD();
460}
int getET_HAD() const
Get HAD ET value in MeV.
Definition jTower.h:134

◆ GetEt_values()

std::unordered_map< int, std::vector< int > > LVL1::jFEXPileupAndNoise::GetEt_values ( )
overridevirtual

Implements LVL1::IjFEXPileupAndNoise.

Definition at line 418 of file jFEXPileupAndNoise.cxx.

418 {
419
420 // map for energies sent to the FPGA
421 std::unordered_map<int,std::vector<int> > map_Etvalues;
422 map_Etvalues.clear();
423
424
425 /*
426 * The vector Et_energy has size 2
427 * Et_energy[0] is used un the Jet algos
428 * Et_energy[1] is used un the Met/SumEt algos
429 */
430 std::vector<int> Et_energy;
431
432 for(auto [key,vec] : m_map_Etvalues_EM){
433
434 Et_energy.clear();
435 Et_energy.resize(2,0);
436
437 Et_energy[0]=m_map_Etvalues_EM[key][0]+m_map_Etvalues_HAD[key][0];
438 Et_energy[1]=m_map_Etvalues_EM[key][1]+m_map_Etvalues_HAD[key][1];
439 map_Etvalues[key] = Et_energy;
440 }
441 return map_Etvalues;
442}

◆ getTTArea_EM()

int LVL1::jFEXPileupAndNoise::getTTArea_EM ( const LVL1::jTower * tmpTower)
private

Definition at line 463 of file jFEXPileupAndNoise.cxx.

463 {
464 return tmpTower->getTTowerArea(0);
465}
int getTTowerArea(int layer) const
Definition jTower.cxx:321

◆ getTTArea_HAD()

int LVL1::jFEXPileupAndNoise::getTTArea_HAD ( const LVL1::jTower * tmpTower)
private

Definition at line 468 of file jFEXPileupAndNoise.cxx.

468 {
469 return tmpTower->getTTowerArea(1);
470}

◆ getTTAreaINV_EM()

int LVL1::jFEXPileupAndNoise::getTTAreaINV_EM ( const LVL1::jTower * tmpTower)
private

Definition at line 473 of file jFEXPileupAndNoise.cxx.

473 {
474 return tmpTower->getTTowerAreaInv(0);
475}
int getTTowerAreaInv(int layer) const
Definition jTower.cxx:329

◆ getTTAreaINV_HAD()

int LVL1::jFEXPileupAndNoise::getTTAreaINV_HAD ( const LVL1::jTower * tmpTower)
private

Definition at line 478 of file jFEXPileupAndNoise.cxx.

478 {
479 return tmpTower->getTTowerAreaInv(1);
480}

◆ getTTowerET()

int LVL1::jFEXPileupAndNoise::getTTowerET ( const LVL1::jTower * tmpTower)
private

Definition at line 450 of file jFEXPileupAndNoise.cxx.

450 {
451 return tmpTower->getTotalET();
452}
int getTotalET() const
Get ET sum of all cells in the jTower in MeV.
Definition jTower.cxx:198

◆ getTTowerEta()

int LVL1::jFEXPileupAndNoise::getTTowerEta ( const LVL1::jTower * tmpTower)
private

Definition at line 446 of file jFEXPileupAndNoise.cxx.

446 {
447 return tmpTower->iEta() < 0 ? std::abs(tmpTower->iEta()+1) : tmpTower->iEta() ;
448}
int iEta() const
Get coordinates of tower.
Definition jTower.cxx:166
setScale setgFexType iEta

◆ initialize()

StatusCode LVL1::jFEXPileupAndNoise::initialize ( )
overridevirtual

standard Athena-Algorithm method

Implements LVL1::IjFEXPileupAndNoise.

Definition at line 29 of file jFEXPileupAndNoise.cxx.

29 {
30
31 ATH_CHECK(m_jTowerContainerKey.initialize());
32 ATH_CHECK( m_BDToolKey.initialize() );
33
34
35 return StatusCode::SUCCESS;
36}
#define ATH_CHECK
Evaluate an expression and check for errors.
SG::ReadHandleKey< LVL1::jTowerContainer > m_jTowerContainerKey

◆ inputHandles()

virtual std::vector< Gaudi::DataHandle * > AthCommonDataStore< AthCommonMsg< AlgTool > >::inputHandles ( ) const
overridevirtualinherited

Return this algorithm's input handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ interfaceID()

const InterfaceID & LVL1::IjFEXPileupAndNoise::interfaceID ( )
inlinestaticinherited

Definition at line 45 of file IjFEXPileupAndNoise.h.

46{
48}
static const InterfaceID IID_IjFEXPileupAndNoise("LVL1::IjFEXPileupAndNoise", 1, 0)

◆ msg()

MsgStream & AthCommonMsg< AlgTool >::msg ( ) const
inlineinherited

Definition at line 24 of file AthCommonMsg.h.

24 {
25 return this->msgStream();
26 }

◆ msgLvl()

bool AthCommonMsg< AlgTool >::msgLvl ( const MSG::Level lvl) const
inlineinherited

Definition at line 30 of file AthCommonMsg.h.

30 {
31 return this->msgLevel(lvl);
32 }

◆ outputHandles()

virtual std::vector< Gaudi::DataHandle * > AthCommonDataStore< AthCommonMsg< AlgTool > >::outputHandles ( ) const
overridevirtualinherited

Return this algorithm's output handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ renounce()

std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > AthCommonDataStore< AthCommonMsg< AlgTool > >::renounce ( T & h)
inlineprotectedinherited

Definition at line 380 of file AthCommonDataStore.h.

381 {
382 h.renounce();
384 }
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > renounce(T &h)

◆ renounceArray()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::renounceArray ( SG::VarHandleKeyArray & handlesArray)
inlineprotectedinherited

remove all handles from I/O resolution

Definition at line 364 of file AthCommonDataStore.h.

364 {
366 }

◆ reset()

StatusCode LVL1::jFEXPileupAndNoise::reset ( )
overridevirtual

Implements LVL1::IjFEXPileupAndNoise.

Definition at line 50 of file jFEXPileupAndNoise.cxx.

50 {
51
52 m_is_FWD=0;
57
59
60 return StatusCode::SUCCESS;
61}

◆ reset_conters()

void LVL1::jFEXPileupAndNoise::reset_conters ( )
private

Definition at line 63 of file jFEXPileupAndNoise.cxx.

63 {
64
65 m_rho_EM = 0;
66 m_rho_HAD1 = 0;
67 m_rho_HAD2 = 0;
68 m_rho_HAD3 = 0;
69 m_rho_FCAL = 0;
70
76
77}

◆ rhoDivLUT()

int LVL1::jFEXPileupAndNoise::rhoDivLUT ( int ntowers)
private

Definition at line 213 of file jFEXPileupAndNoise.cxx.

213 {
214
215 //This is to save one bit in the firmware (19 bit will set be set to 1 instead of the 20th bit and rest are 0)
216 if(ntowers == 1) return ((1<<FEXAlgoSpaceDefs::pu_rhoLUT) - 1);
217 return static_cast<int>((1.0/ntowers)*(1<<FEXAlgoSpaceDefs::pu_rhoLUT) );
218}

◆ safetyTest()

StatusCode LVL1::jFEXPileupAndNoise::safetyTest ( )
overridevirtual

Implements LVL1::IjFEXPileupAndNoise.

Definition at line 39 of file jFEXPileupAndNoise.cxx.

39 {
40
41 m_jTowerContainer = SG::ReadHandle<jTowerContainer>(m_jTowerContainerKey);
42 if(! m_jTowerContainer.isValid()) {
43 ATH_MSG_ERROR("Could not retrieve jTowerContainer " << m_jTowerContainerKey.key());
44 return StatusCode::FAILURE;
45 }
46
47 return StatusCode::SUCCESS;
48}

◆ setup() [1/2]

void LVL1::jFEXPileupAndNoise::setup ( int FPGA[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXPileupAndNoise.

Definition at line 81 of file jFEXPileupAndNoise.cxx.

81 {
82
83 ATH_MSG_DEBUG("---------------- jFEXPileupAndNoise::setup ----------------");
84 m_is_FWD = 0; //central region
87}
#define ATH_MSG_DEBUG(x)
static constexpr int jFEX_thin_algoSpace_width

◆ setup() [2/2]

void LVL1::jFEXPileupAndNoise::setup ( int FPGA[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width])
overridevirtual

Implements LVL1::IjFEXPileupAndNoise.

Definition at line 91 of file jFEXPileupAndNoise.cxx.

91 {
92
93 ATH_MSG_DEBUG("---------------- jFEXPileupAndNoise::setup ----------------");
94 m_is_FWD = 1; //forward region
97}
static constexpr int jFEX_wide_algoSpace_width

◆ SubtractPileup()

void LVL1::jFEXPileupAndNoise::SubtractPileup ( )
private

Definition at line 220 of file jFEXPileupAndNoise.cxx.

220 {
221
222 for(int iphi=0; iphi<FEXAlgoSpaceDefs::jFEX_algoSpace_height; iphi++) {
223 for(int ieta=0; ieta<m_etaMAX; ieta++) {
224
225 int TTID = 0;
226
227 if(m_is_FWD) {
228 TTID = m_FPGA_forward[iphi][ieta];
229 }
230 else {
231 TTID = m_FPGA_central[iphi][ieta];
232 }
233
234 if(TTID == 0) continue; //skipping TTID iqual to 0
235
236 const LVL1::jTower *tmpTower = m_jTowerContainer->findTower(TTID);
237 int tmp_eta = getTTowerEta(tmpTower);
238 int tmp_EM_Area = getTTArea_EM(tmpTower);
239 int tmp_HD_Area = getTTArea_HAD(tmpTower);
240
241 if(tmp_eta < 32) {
242 m_FPGA_ET_EM[TTID] =m_FPGA_ET_EM[TTID] - ((m_rho_EM * tmp_EM_Area)/(1<<FEXAlgoSpaceDefs::pu_Area)) * 25; //factor 25: jFEX internal counts -> MeV (LAr)
243 }
244
245 if(tmp_eta < 15) {
246 m_FPGA_ET_HAD[TTID]=m_FPGA_ET_HAD[TTID] - ((m_rho_HAD1 * tmp_HD_Area)/(1<<FEXAlgoSpaceDefs::pu_Area)) * 500; //factor 500: jFEX internal counts -> MeV (Tile)
247 }
248 else if(tmp_eta < 16 ) {
249 m_FPGA_ET_HAD[TTID]=m_FPGA_ET_HAD[TTID] - ((m_rho_HAD2 * tmp_HD_Area)/(1<<FEXAlgoSpaceDefs::pu_Area)) * 25; //factor 25: jFEX internal counts -> MeV (LAr)
250 }
251 else if(tmp_eta < 32 ) {
252 m_FPGA_ET_HAD[TTID]=m_FPGA_ET_HAD[TTID] - ((m_rho_HAD3 * tmp_HD_Area)/(1<<FEXAlgoSpaceDefs::pu_Area)) * 25; //factor 25: jFEX internal counts -> MeV (LAr)
253 }
254 else if(tmp_eta >= 32) {
255 // Contributes the HAD layer (FCAL2 and FCAL3)
257 m_FPGA_ET_HAD[TTID] = m_FPGA_ET_HAD[TTID] - ((m_rho_FCAL * (tmp_HD_Area))/(1<<FEXAlgoSpaceDefs::pu_Area)) * 25; //factor 25: jFEX internal counts -> MeV (LAr)
258 }
259 // FCAL1 is EM layer so the energy is suposed to be in the EM layer
260 else{
261 m_FPGA_ET_EM[TTID] = m_FPGA_ET_EM[TTID] - ((m_rho_FCAL * (tmp_EM_Area))/(1<<FEXAlgoSpaceDefs::pu_Area)) * 25; //factor 25: jFEX internal counts -> MeV (LAr)
262 }
263 }
264 }
265 }
266}
static constexpr unsigned int pu_Area
int getTTArea_HAD(const LVL1::jTower *tmpTower)
int getTTArea_EM(const LVL1::jTower *tmpTower)

◆ sysInitialize()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysInitialize ( )
overridevirtualinherited

Perform system initialization for an algorithm.

We override this to declare all the elements of handle key arrays at the end of initialization. See comments on updateVHKA.

Reimplemented in asg::AsgMetadataTool, AthCheckedComponent< AthAlgTool >, AthCheckedComponent<::AthAlgTool >, and DerivationFramework::CfAthAlgTool.

◆ sysStart()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysStart ( )
overridevirtualinherited

Handle START transition.

We override this in order to make sure that conditions handle keys can cache a pointer to the conditions container.

◆ updateVHKA()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::updateVHKA ( Gaudi::Details::PropertyBase & )
inlineinherited

Definition at line 308 of file AthCommonDataStore.h.

308 {
309 // debug() << "updateVHKA for property " << p.name() << " " << p.toString()
310 // << " size: " << m_vhka.size() << endmsg;
311 for (auto &a : m_vhka) {
313 for (auto k : keys) {
314 k->setOwner(this);
315 }
316 }
317 }
std::vector< SG::VarHandleKeyArray * > m_vhka

Member Data Documentation

◆ m_apply_noise2jets

bool LVL1::jFEXPileupAndNoise::m_apply_noise2jets = false
private

Definition at line 88 of file jFEXPileupAndNoise.h.

◆ m_apply_noise2met

bool LVL1::jFEXPileupAndNoise::m_apply_noise2met = false
private

Definition at line 89 of file jFEXPileupAndNoise.h.

◆ m_apply_pileup2jets

bool LVL1::jFEXPileupAndNoise::m_apply_pileup2jets = false
private

Definition at line 86 of file jFEXPileupAndNoise.h.

◆ m_apply_pileup2met

bool LVL1::jFEXPileupAndNoise::m_apply_pileup2met = false
private

Definition at line 87 of file jFEXPileupAndNoise.h.

◆ m_BDToolKey

SG::ReadCondHandleKey<jFEXDBCondData> LVL1::jFEXPileupAndNoise::m_BDToolKey {this, "BDToolKey", "jFEXDBParams", "DB tool key"}
private

Definition at line 60 of file jFEXPileupAndNoise.h.

60{this, "BDToolKey", "jFEXDBParams", "DB tool key"};

◆ m_count_rho_EM

int LVL1::jFEXPileupAndNoise::m_count_rho_EM = 0
private

Definition at line 78 of file jFEXPileupAndNoise.h.

◆ m_count_rho_FCAL

int LVL1::jFEXPileupAndNoise::m_count_rho_FCAL = 0
private

Definition at line 82 of file jFEXPileupAndNoise.h.

◆ m_count_rho_HAD1

int LVL1::jFEXPileupAndNoise::m_count_rho_HAD1 = 0
private

Definition at line 79 of file jFEXPileupAndNoise.h.

◆ m_count_rho_HAD2

int LVL1::jFEXPileupAndNoise::m_count_rho_HAD2 = 0
private

Definition at line 80 of file jFEXPileupAndNoise.h.

◆ m_count_rho_HAD3

int LVL1::jFEXPileupAndNoise::m_count_rho_HAD3 = 0
private

Definition at line 81 of file jFEXPileupAndNoise.h.

◆ m_detStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_detStore
privateinherited

Pointer to StoreGate (detector store by default)

Definition at line 393 of file AthCommonDataStore.h.

◆ m_etaMAX

int LVL1::jFEXPileupAndNoise::m_etaMAX =0
private

Definition at line 65 of file jFEXPileupAndNoise.h.

◆ m_evtStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_evtStore
privateinherited

Pointer to StoreGate (event store by default)

Definition at line 390 of file AthCommonDataStore.h.

◆ m_FPGA_central

int LVL1::jFEXPileupAndNoise::m_FPGA_central[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] ={{0}}
private

Definition at line 62 of file jFEXPileupAndNoise.h.

62{{0}};

◆ m_FPGA_ET_EM

std::unordered_map<int,int > LVL1::jFEXPileupAndNoise::m_FPGA_ET_EM
private

Definition at line 67 of file jFEXPileupAndNoise.h.

◆ m_FPGA_ET_HAD

std::unordered_map<int,int > LVL1::jFEXPileupAndNoise::m_FPGA_ET_HAD
private

Definition at line 68 of file jFEXPileupAndNoise.h.

◆ m_FPGA_forward

int LVL1::jFEXPileupAndNoise::m_FPGA_forward[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] ={{0}}
private

Definition at line 63 of file jFEXPileupAndNoise.h.

63{{0}};

◆ m_is_FWD

bool LVL1::jFEXPileupAndNoise::m_is_FWD = false
private

Definition at line 85 of file jFEXPileupAndNoise.h.

◆ m_jTowerContainer

SG::ReadHandle<jTowerContainer> LVL1::jFEXPileupAndNoise::m_jTowerContainer
private

Definition at line 58 of file jFEXPileupAndNoise.h.

◆ m_jTowerContainerKey

SG::ReadHandleKey<LVL1::jTowerContainer> LVL1::jFEXPileupAndNoise::m_jTowerContainerKey {this, "MyjTowers", "jTowerContainer", "Input container for jTowers"}
private

Definition at line 57 of file jFEXPileupAndNoise.h.

57{this, "MyjTowers", "jTowerContainer", "Input container for jTowers"};

◆ m_map_Etvalues_EM

std::unordered_map<int,std::vector<int> > LVL1::jFEXPileupAndNoise::m_map_Etvalues_EM
private

Definition at line 106 of file jFEXPileupAndNoise.h.

◆ m_map_Etvalues_HAD

std::unordered_map<int,std::vector<int> > LVL1::jFEXPileupAndNoise::m_map_Etvalues_HAD
private

Definition at line 107 of file jFEXPileupAndNoise.h.

◆ m_rho_EM

int LVL1::jFEXPileupAndNoise::m_rho_EM = 0
private

Definition at line 71 of file jFEXPileupAndNoise.h.

◆ m_rho_FCAL

int LVL1::jFEXPileupAndNoise::m_rho_FCAL = 0
private

Definition at line 75 of file jFEXPileupAndNoise.h.

◆ m_rho_HAD1

int LVL1::jFEXPileupAndNoise::m_rho_HAD1 = 0
private

Definition at line 72 of file jFEXPileupAndNoise.h.

◆ m_rho_HAD2

int LVL1::jFEXPileupAndNoise::m_rho_HAD2 = 0
private

Definition at line 73 of file jFEXPileupAndNoise.h.

◆ m_rho_HAD3

int LVL1::jFEXPileupAndNoise::m_rho_HAD3 = 0
private

Definition at line 74 of file jFEXPileupAndNoise.h.

◆ m_varHandleArraysDeclared

bool AthCommonDataStore< AthCommonMsg< AlgTool > >::m_varHandleArraysDeclared
privateinherited

Definition at line 399 of file AthCommonDataStore.h.

◆ m_vhka

std::vector<SG::VarHandleKeyArray*> AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
privateinherited

Definition at line 398 of file AthCommonDataStore.h.


The documentation for this class was generated from the following files: