ATLAS Offline Software
jFEXFPGA.cxx
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1 /*
2  Copyright (C) 2002-2025 CERN for the benefit of the ATLAS collaboration
3 */
4 
5 //***************************************************************************
6 // jFEXFPGA - description
7 // -------------------
8 // begin : 19 10 2020
9 // email : jacob.julian.kempster@cern.ch
10 // ***************************************************************************/
11 
12 #include "jFEXFPGA.h"
13 #include "jFEXFormTOBs.h"
14 #include "jFEXForwardElecAlgo.h"
15 #include "jFEXForwardJetsAlgo.h"
16 #include "jFEXLargeRJetAlgo.h"
17 #include "jFEXPileupAndNoise.h"
18 #include "jFEXSmallRJetAlgo.h"
19 #include "jFEXmetAlgo.h"
20 #include "jFEXsumETAlgo.h"
21 #include "jFEXtauAlgo.h"
22 
23 #include "L1CaloFEXSim/jFEXForwardElecInfo.h"
24 #include "L1CaloFEXSim/jFEXForwardJetsInfo.h"
25 #include "L1CaloFEXSim/jFEXOutputCollection.h"
26 #include "L1CaloFEXSim/jFEXTOB.h"
27 #include "L1CaloFEXSim/jTower.h"
28 
29 #include "StoreGate/ReadHandle.h"
30 
31 
32 namespace LVL1 {
33 
34  // default constructor for persistency
35 
36 jFEXFPGA::jFEXFPGA(const std::string& type,const std::string& name,const IInterface* parent): AthAlgTool(type,name,parent) {
37  declareInterface<IjFEXFPGA>(this);
38 }
39 
41 jFEXFPGA::~jFEXFPGA()
42 {
43 }
44 
45 //================ Initialisation =================================================
46 
47 StatusCode jFEXFPGA::initialize() {
48 
49  ATH_CHECK(m_jTowerContainerKey.initialize());
50  ATH_CHECK(m_l1MenuKey.initialize());
51  ATH_CHECK(m_jFEXtauAlgoTool.retrieve());
52  return StatusCode::SUCCESS;
53 }
54 
55 StatusCode jFEXFPGA::init(int id, int jfexid) {
56  m_id = id;
57  m_jfexid = jfexid;
58 
59  return StatusCode::SUCCESS;
60 
61 }
62 
63 void jFEXFPGA::reset() {
64 
65  m_id = -1;
66  m_jfexid = -1;
67  m_tau_tobwords.clear();
68  m_SRJet_tobwords.clear();
69  m_LRJet_tobwords.clear();
70  m_sumET_tobwords.clear();
71  m_Met_tobwords.clear();
72  m_map_Etvalues_FPGA.clear();
73  m_map_EM_Etvalues_FPGA.clear();
74  m_map_HAD_Etvalues_FPGA.clear();
75  m_FwdEl_tobwords.clear();
76 }
77 
78 StatusCode jFEXFPGA::execute(jFEXOutputCollection* inputOutputCollection, const std::pair<unsigned int, const std::vector<int>&> & jetCalibrationParameters) {
79 
80  // Retrieve the L1 menu configuration
81  SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
82 
83  const TrigConf::L1ThrExtraInfo_jTAU & thr_jTAU = l1Menu->thrExtraInfo().jTAU();
84  const TrigConf::L1ThrExtraInfo_jJ & thr_jJ = l1Menu->thrExtraInfo().jJ();
85  const TrigConf::L1ThrExtraInfo_jLJ & thr_jLJ = l1Menu->thrExtraInfo().jLJ();
86  const TrigConf::L1ThrExtraInfo_jTE & thr_jTE = l1Menu->thrExtraInfo().jTE();
87  const TrigConf::L1ThrExtraInfo_jXE & thr_jXE = l1Menu->thrExtraInfo().jXE();
88 
89  SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey/*,ctx*/);
90  if(!jTowerContainer.isValid()) {
91  ATH_MSG_ERROR("Could not retrieve container " << m_jTowerContainerKey.key() );
92  return StatusCode::FAILURE;
93  }
94 
95  ATH_CHECK( m_jFEXPileupAndNoiseTool->safetyTest());
96  ATH_CHECK( m_jFEXPileupAndNoiseTool->reset());
97  if(m_jfexid == 0 || m_jfexid == 5) {
98  m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Wide);
99  }
100  else {
101  m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Thin);
102  }
103 
104  //Calculating and sustracting pileup
105  const std::vector<int> pileup_rho = m_jFEXPileupAndNoiseTool->CalculatePileup();
106 
107  //From the DB
108  ATH_CHECK(m_jFEXPileupAndNoiseTool->ApplyPileup());
109 
110  //Noise should be always applied
111  m_jFEXPileupAndNoiseTool->ApplyNoise2Jets(true);
112  m_jFEXPileupAndNoiseTool->ApplyNoise2Met(true);
113  //Getting the values
114  m_map_HAD_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_HAD_Et_values();
115  m_map_EM_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_EM_Et_values();
116  m_map_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->GetEt_values();
117  std::vector<int> pileup_ID;
118  std::vector<int> pileup_HAD_jet;
119  std::vector<int> pileup_EM_jet;
120  std::vector<int> pileup_Total_jet;
121  std::vector<int> pileup_HAD_met;
122  std::vector<int> pileup_EM_met;
123  std::vector<int> pileup_Total_met;
124  for (auto const& [key, val] : m_map_HAD_Etvalues_FPGA)
125  {
126  pileup_ID.push_back(key);
127  pileup_HAD_jet.push_back(val[0]);
128  pileup_EM_jet.push_back(m_map_EM_Etvalues_FPGA[key][0]);
129  pileup_Total_jet.push_back(m_map_Etvalues_FPGA[key][0]);
130  pileup_HAD_met.push_back(val[1]);
131  pileup_EM_met.push_back(m_map_EM_Etvalues_FPGA[key][1]);
132  pileup_Total_met.push_back(m_map_Etvalues_FPGA[key][1]);
133  }
134 
135  //saving pileup information
136  inputOutputCollection->addValue_pileup("pileup_FPGAid", m_id);
137  inputOutputCollection->addValue_pileup("pileup_jFEXid", m_jfexid);
138  inputOutputCollection->addValue_pileup("pileup_rho_EM", pileup_rho[0]);
139  inputOutputCollection->addValue_pileup("pileup_rho_HAD1", pileup_rho[1]);
140  inputOutputCollection->addValue_pileup("pileup_rho_HAD2", pileup_rho[2]);
141  inputOutputCollection->addValue_pileup("pileup_rho_HAD3", pileup_rho[3]);
142  inputOutputCollection->addValue_pileup("pileup_rho_FCAL", pileup_rho[4]);
143  inputOutputCollection->addValue_pileup("pileup_map_ID" , std::move(pileup_ID));
144  inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_jet" , std::move(pileup_HAD_jet));
145  inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_jet" , std::move(pileup_EM_jet));
146  inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_jet", std::move(pileup_Total_jet));
147  inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_met" , std::move(pileup_HAD_met));
148  inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_met" , std::move(pileup_EM_met));
149  inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_met", std::move(pileup_Total_met));
150  inputOutputCollection->fill_pileup();
151 
152  if(m_id==0 || m_id==3) {
153  ATH_CHECK( m_jFEXsumETAlgoTool->safetyTest());
154  ATH_CHECK( m_jFEXsumETAlgoTool->reset());
155  ATH_CHECK( m_jFEXmetAlgoTool->safetyTest());
156  ATH_CHECK( m_jFEXmetAlgoTool->reset());
157 
158  m_jFEXsumETAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
159  m_jFEXmetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
160 
161  unsigned int bin_pos = thr_jTE.etaBoundary_fw(m_jfex_string[m_jfexid]);
162 
163  std::unique_ptr<jFEXTOB> jXE_tob = std::make_unique<jFEXTOB>();
164  uint32_t jXE_tobword = 0;
165 
166  std::unique_ptr<jFEXTOB> jTE_tob = std::make_unique<jFEXTOB>();
167  uint32_t jTE_tobword = 0;
168 
169 
170  int hemisphere = m_id == 0 ? 1 : -1;
171 
172  if(m_jfexid > 0 && m_jfexid < 5) {
173 
174  //-----------------jFEXsumETAlgo-----------------
175  m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Thin);
176  m_jFEXsumETAlgoTool->buildBarrelSumET();
177 
178  //-----------------jFEXmetAlgo-----------------
179  m_jFEXmetAlgoTool->setup(m_jTowersIDs_Thin, hemisphere);
180  m_jFEXmetAlgoTool->buildBarrelmet();
181  }
182  else if(m_jfexid == 0 ) {
183 
184  int flipped_jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}};
185  int max_phi_it = FEXAlgoSpaceDefs::jFEX_algoSpace_height-1;
186  int max_eta_it = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-1;
187  for(int mphi = 0; mphi <= max_phi_it; mphi++) {
188  for(int meta = 0; meta <= max_eta_it; meta++) {
189  flipped_jTowersIDs[mphi][meta]=m_jTowersIDs_Wide[mphi][max_eta_it-meta];
190  }
191  }
192  //-----------------jFEXsumETAlgo-----------------
193  m_jFEXsumETAlgoTool->setup(flipped_jTowersIDs);
194  m_jFEXsumETAlgoTool->buildFWDSumET();
195 
196  //-----------------jFEXmetAlgo-----------------
197  m_jFEXmetAlgoTool->setup(flipped_jTowersIDs, hemisphere);
198  m_jFEXmetAlgoTool->buildFWDmet();
199  }
200  else if(m_jfexid == 5) {
201 
202  //-----------------jFEXsumETAlgo-----------------
203  m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Wide);
204  m_jFEXsumETAlgoTool->buildFWDSumET();
205 
206  //-----------------jFEXmetAlgo-----------------
207  m_jFEXmetAlgoTool->setup(m_jTowersIDs_Wide, hemisphere);
208  m_jFEXmetAlgoTool->buildFWDmet();
209  }
210 
211  jXE_tobword = m_IjFEXFormTOBsTool->formMetTOB(m_jFEXmetAlgoTool->GetMetXComponent(), m_jFEXmetAlgoTool->GetMetYComponent(),m_jFEXmetAlgoTool->getjXESat(),thr_jXE.resolutionMeV());
212  jXE_tob->initialize(m_id,m_jfexid,jXE_tobword,thr_jXE.resolutionMeV(),0);
213  m_Met_tobwords.push_back(std::move(jXE_tob));
214 
215  std::tuple<int,bool> jTElow;
216  std::tuple<int,bool> jTEhigh;
217 
218  // NOTE: Foward FPGA in the C-side is already flipped, however we still need to flip the jFEX module 1 and 2
219  if(m_jfexid == 1 || m_jfexid == 2){
220  jTElow = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
221  jTEhigh = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
222  }
223  else{
224  jTElow = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
225  jTEhigh = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
226  }
227 
228  jTE_tobword = m_IjFEXFormTOBsTool->formSumETTOB(jTElow,jTEhigh,thr_jTE.resolutionMeV());
229  jTE_tob->initialize(m_id,m_jfexid,jTE_tobword,thr_jTE.resolutionMeV(),0);
230  m_sumET_tobwords.push_back(std::move(jTE_tob));
231  }
232 
233  //-----------jFEXSmallRJet & Large R Jet Algo-----------------
234  ATH_MSG_DEBUG("================ Central Algorithms ================");
235 
236  int srJet_seedThresholdMeV = thr_jJ.seedThresholdMeV(m_jfex_string[m_jfexid]); //jFEX internal granularity, i.e., 25 MeV/count
237 
238 
239  //Central region algorithms
240  if(m_jfexid > 0 && m_jfexid < 5) {
241  m_jFEXSmallRJetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
242  if(!m_jFEXLargeRJetAlgoTool.empty()) m_jFEXLargeRJetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
243  m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
244 
245  for(int mphi = 8; mphi < FEXAlgoSpaceDefs::jFEX_algoSpace_height-8; mphi++) {
246  for(int meta = 8; meta < FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width-8; meta++) {
247 
248  //definition of arrays
249  int TT_seed_ID[3][3]= {{0}};
250  int TT_First_ETring[36]= {0};
251  int First_ETring_it = 0;
252 
253  int Jet_SearchWindow[7][7] = {{0}};
254  int Jet_SearchWindowDisplaced[7][7] = {{0}};
255  int largeRCluster_IDs[15][15]= {{0}};
256 
257  //filling up array to send them to the algorithms
258  for(int i = -7; i< 8; i++ ) {
259  for(int j = -7; j< 8; j++) {
260 
261  if(std::abs(i)<4 && std::abs(j)<4) {
262  Jet_SearchWindow[3 + i][3 + j] = m_jTowersIDs_Thin[mphi + i][meta +j];
263  Jet_SearchWindowDisplaced[3 + i][3 + j] = m_jTowersIDs_Thin[mphi+i+1][meta+j+1];
264  }
265 
266  uint deltaR = std::sqrt(std::pow(i,2)+std::pow(j,2));
267 
268  if(deltaR<2) {
269  TT_seed_ID[i+1][j+1] = m_jTowersIDs_Thin[mphi +i][meta +j]; // Seed 0.3x0.3 in phi-eta plane
270  }
271  else if(deltaR<4) {
272  TT_First_ETring[First_ETring_it]= m_jTowersIDs_Thin[mphi +i][meta +j]; // First energy ring, will be used as tau ISO
273  ++First_ETring_it;
274 
275  }
276  else if(deltaR<8) {
277  largeRCluster_IDs[7 +i][7 +j] = m_jTowersIDs_Thin[mphi + i][meta +j];
278  }
279  }
280  }
281 
282  // ******** jJ and jLJ algorithms ********
283  ATH_CHECK( m_jFEXSmallRJetAlgoTool->safetyTest());
284  if(!m_jFEXLargeRJetAlgoTool.empty()) ATH_CHECK( m_jFEXLargeRJetAlgoTool->safetyTest());
285  m_jFEXSmallRJetAlgoTool->setup(Jet_SearchWindow, Jet_SearchWindowDisplaced);
286  if(!m_jFEXLargeRJetAlgoTool.empty()) m_jFEXLargeRJetAlgoTool->setupCluster(largeRCluster_IDs);
287  m_jFEXSmallRJetAlgoTool->buildSeeds();
288 
289  bool is_Jet_LM = m_jFEXSmallRJetAlgoTool->isSeedLocalMaxima(srJet_seedThresholdMeV);
290 
291  if(is_Jet_LM) {
292 
293  //getting the energies
294  int SRj_Et = m_jFEXSmallRJetAlgoTool->getSmallClusterET();
295  int LRj_Et = (m_jFEXLargeRJetAlgoTool.empty()) ? 0 : m_jFEXLargeRJetAlgoTool->getLargeClusterET(SRj_Et,m_jFEXLargeRJetAlgoTool->getRingET());
296  int seed_Et = m_jFEXSmallRJetAlgoTool->getSeedET();
297 
298  bool SRj_Sat = m_jFEXSmallRJetAlgoTool->getSRjetSat();
299  bool LRj_Sat = (m_jFEXLargeRJetAlgoTool.empty()) ? false : (SRj_Sat || m_jFEXLargeRJetAlgoTool->getLRjetSat());
300 
301  int meta_LM = meta;
302  int mphi_LM = mphi;
303 
304 
305  //Creating SR TOB
306  uint32_t SRJet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, mphi_LM, meta_LM, SRj_Et, SRj_Sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
307 
308  std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
309  jJ_tob->initialize(m_id,m_jfexid,SRJet_tobword,thr_jJ.resolutionMeV(),m_jTowersIDs_Thin[mphi_LM][meta_LM],seed_Et);
310  if ( SRJet_tobword != 0 ){
311  m_SRJet_tobwords.push_back(std::move(jJ_tob));
312  }
313 
314  //Creating LR TOB
315  if(!m_jFEXLargeRJetAlgoTool.empty()) {
316  uint32_t LRJet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, mphi_LM, meta_LM, LRj_Et,
317  LRj_Sat, thr_jLJ.resolutionMeV(),
318  thr_jLJ.ptMinToTopoMeV(
319  m_jfex_string[m_jfexid]));
320 
321  std::unique_ptr <jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
322  jLJ_tob->initialize(m_id, m_jfexid, LRJet_tobword, thr_jLJ.resolutionMeV(),
323  m_jTowersIDs_Thin[mphi_LM][meta_LM], seed_Et);
324  if (LRJet_tobword != 0) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
325  }
326  }
327  // ******** jTau algorithm ********
328 
329  ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
330  m_jFEXtauAlgoTool->setup(TT_seed_ID);
331  bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima();
332 
333  // Save TOB is tau is a local maxima
334  if ( is_tau_LocalMax ) {
335 
336  //calculates the 1st energy ring
337  m_jFEXtauAlgoTool->setFirstEtRing(TT_First_ETring);
338 
339 
340  uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
341 
342  std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
343  jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),m_jTowersIDs_Thin[mphi][meta]);
344 
345  if ( jTau_tobword != 0 ){
346  m_tau_tobwords.push_back(std::move(jTau_tob));
347  }
348  }
349  }
350  }
351  } //end of if statement for checking if in central jfex modules
352 
353  //FCAL region algorithm
354  if(m_jfexid ==0 || m_jfexid ==5) {
355 
356  //**********Forward Jets***********************
357  ATH_CHECK(m_jFEXForwardJetsAlgoTool->safetyTest());
358  ATH_CHECK(m_jFEXForwardJetsAlgoTool->reset());
359  m_jFEXForwardJetsAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
360  m_jFEXForwardJetsAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid);
361 
362  m_FCALJets = m_jFEXForwardJetsAlgoTool->calculateJetETs(srJet_seedThresholdMeV);
363  for(std::unordered_map<int, jFEXForwardJetsInfo>::iterator it = m_FCALJets.begin(); it!=(m_FCALJets.end()); ++it) {
364 
365  uint32_t TTID = it->first;
366  jFEXForwardJetsInfo FCALJets = it->second;
367 
368  int iphi = FCALJets.getCentreLocalTTPhi();
369  int ieta = FCALJets.getCentreLocalTTEta();
370  m_SRJetET = FCALJets.getSeedET() + FCALJets.getFirstEnergyRingET();
371  m_LRJetET = m_SRJetET + FCALJets.getSecondEnergyRingET();
372  int seedET = FCALJets.getSeedET();
373 
374  bool SRJ_sat = FCALJets.getSRjetSat();
375 
376  uint32_t SRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, iphi, ieta, m_SRJetET, SRJ_sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
377 
378  std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
379  jJ_tob->initialize(m_id,m_jfexid,SRFCAL_Jet_tobword,thr_jJ.resolutionMeV(),TTID,seedET);
380 
381  if ( SRFCAL_Jet_tobword != 0 ){
382  m_SRJet_tobwords.push_back(std::move(jJ_tob));
383  }
384 
385  if(std::fabs(FCALJets.getCentreTTEta())<2.51 && !m_jFEXLargeRJetAlgoTool.empty()){
386  bool LRJ_sat = FCALJets.getLRjetSat();
387  uint32_t LRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, iphi, ieta, m_LRJetET, LRJ_sat, thr_jLJ.resolutionMeV(),thr_jLJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
388 
389  std::unique_ptr<jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
390  jLJ_tob->initialize(m_id,m_jfexid,LRFCAL_Jet_tobword,thr_jLJ.resolutionMeV(),TTID);
391  if ( LRFCAL_Jet_tobword != 0 ) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
392  }
393 
394  }
395  //********** Forward Electrons ***********************
396  ATH_CHECK(m_jFEXForwardElecAlgoTool->safetyTest());
397  ATH_CHECK(m_jFEXForwardElecAlgoTool->reset());
398  m_jFEXForwardElecAlgoTool->setFPGAEnergy(m_map_EM_Etvalues_FPGA,m_map_HAD_Etvalues_FPGA);
399  m_jFEXForwardElecAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid,m_id);
400  m_ForwardElecs = m_jFEXForwardElecAlgoTool->calculateEDM();
401 
403  SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
404  const TrigConf::L1ThrExtraInfo_jEM & thr_jEM = l1Menu->thrExtraInfo().jEM();
405  const uint jFEXETResolution = thr_jEM.resolutionMeV();//200
406  std::string str_jfexname = m_jfex_string[m_jfexid];
407  uint minEtThreshold = thr_jEM.ptMinToTopoMeV(str_jfexname)/jFEXETResolution;
408  //uint Cval[9] = {1,2,3,20,30,40,20,30,40};//C values for iso, emfr1 and emfr2
409  std::vector<int> Ciso;
410  std::vector<int> Chad1;
411  std::vector<int> Chad2;
412 
413  for(std::unordered_map<uint, jFEXForwardElecInfo>::iterator itel = m_ForwardElecs.begin(); itel!=(m_ForwardElecs.end()); ++itel) {
414  uint32_t TTID = itel->first;
415  jFEXForwardElecInfo elCluster = itel->second;
416  uint meta = elCluster.getCoreIeta();//check whether this is the one used by the Trigger conf
417 
418  //retrieve jet rejection thresholds from trigger configuration
419  const auto & wp_loose = thr_jEM.isolation(TrigConf::Selection::WP::LOOSE, meta);
420  const auto & wp_medium = thr_jEM.isolation(TrigConf::Selection::WP::MEDIUM, meta);
421  const auto & wp_tight = thr_jEM.isolation(TrigConf::Selection::WP::TIGHT, meta);
422  Ciso.clear();
423  Chad1.clear();
424  Chad2.clear();
425  Ciso.push_back(wp_loose.iso_fw());
426  Ciso.push_back(wp_medium.iso_fw());
427  Ciso.push_back(wp_tight.iso_fw());
428  Chad1.push_back(wp_loose.frac_fw());
429  Chad1.push_back(wp_medium.frac_fw());
430  Chad1.push_back(wp_tight.frac_fw());
431  Chad2.push_back(wp_loose.frac2_fw());
432  Chad2.push_back(wp_medium.frac2_fw());
433  Chad2.push_back(wp_tight.frac2_fw());
434  int Cval[9] = {Ciso[0], Ciso[1], Ciso[2], Chad1[0], Chad1[1], Chad1[2], Chad2[0], Chad2[1], Chad2[2]};
435 
436  elCluster.setup(Cval,jFEXETResolution);
437  elCluster.calcFwdElEDM();
438 
439  uint etEM = elCluster.getEt();
440  uint32_t FwdEl_tobword = elCluster.getTobWord();
441 
442 
443  std::vector<uint32_t> FwdEltob_aux{FwdEl_tobword,TTID};
444  if ( FwdEl_tobword != 0 && etEM>minEtThreshold) m_FwdEl_tobwords.push_back(FwdEltob_aux);
445  }
446 
447  //******************************** TAU **********************************************
448  int jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}};
449  int max_meta=17;
450 
451  if(m_jfexid ==0) {
452  for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
453  for(int j=28; j<(FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-6); j++) { //lower values of j (j<28) are the Fcals not entering in the jFEX tau range
454  jTowersIDs[i][j-28+8]=m_jTowersIDs_Wide[i][j]; // second argument in m_jTowersIDs is to center the FPGA core area in te same region as the central FPGAs
455  }
456  }
457 
458  }
459  else if(m_jfexid ==5 ) {
460 
461  // Filling m_jTowersIDs with the m_jTowersIDs_Wide ID values up to 2.5 eta
462  for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
463  for(int j=4; j<17; j++) { //higher values of j (j>16) are the Fcals not entering in the jFEX tau range
464  jTowersIDs[i][j]=m_jTowersIDs_Wide[i][j];
465  }
466  }
467  }
468  ATH_MSG_DEBUG("============================ jFEXtauAlgo ============================");
469  ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
470  m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
471  for(int mphi = 8; mphi < 24; mphi++) {
472  for(int meta = 8; meta < max_meta; meta++) {
473 
474  bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima_fwd(jTowersIDs[mphi][meta]);
475 
476  // Save TOB is tau is a local maxima
477  if ( is_tau_LocalMax ) {
478 
479  uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
480 
481  std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
482  jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),jTowersIDs[mphi][meta]);
483  if ( jTau_tobword != 0 ){
484  m_tau_tobwords.push_back(std::move(jTau_tob));
485  }
486  }
487  }
488  }
489  } //end of if statement for checking if in central jfex modules
490  return StatusCode::SUCCESS;
491 } //end of the execute function
492 
493 void jFEXFPGA::SetTowersAndCells_SG(int tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]) {
494 
495  const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
496  const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
497 
498  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Wide[0][0]);
499 
500  ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
501 
502  for (int thisRow=rows-1; thisRow>=0; thisRow--){
503  for (int thisCol=0; thisCol<cols; thisCol++){
504  if(thisCol != cols-1){ ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " "); }
505  else { ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " |"); }
506  }
507  }
508 
509 }
510 
511 void jFEXFPGA::SetTowersAndCells_SG(int tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]) {
512 
513  const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
514  const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
515 
516  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Thin[0][0]);
517 
518  //this prints out the jTower IDs that each FPGA is responsible for
519  ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
520 
521  for (int thisRow=rows-1; thisRow>=0; thisRow--) {
522  for (int thisCol=0; thisCol<cols; thisCol++) {
523  if(thisCol != cols-1) {
524  ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " ");
525  }
526  else {
527  ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " |");
528  }
529  }
530  }
531 
532 }
533 
534 std::vector <std::unique_ptr<jFEXTOB>> jFEXFPGA::getSmallRJetTOBs()
535 {
536  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
537 
538  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
539  for(auto &j : m_SRJet_tobwords) {
540  tobsSort.push_back(std::move(j));
541  }
542  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jJ_etBit, 0x7ff));
543 
544  return tobsSort;
545 }
546 
547 std::vector <std::unique_ptr<jFEXTOB>> jFEXFPGA::getLargeRJetTOBs()
548 {
549  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
550 
551  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
552  for(auto &j : m_LRJet_tobwords) {
553  tobsSort.push_back(std::move(j));
554  }
555  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jLJ_etBit, 0x1fff));
556 
557  return tobsSort;
558 }
559 
560 
561  std::vector <std::vector <uint32_t>> jFEXFPGA::getFwdElTOBs()
562  {
563  auto tobsSort = m_FwdEl_tobwords;
564 
565  ATH_MSG_DEBUG("number of Forward Elec tobs: " << tobsSort.size() << " in FPGA: " << m_id<< " before truncation");
566  //sort tobs by their et
567  std::sort (tobsSort.begin(), tobsSort.end(), etFwdElSort);
568 
569  return tobsSort;
570  }
571 
572 
573 std::vector <std::unique_ptr<jFEXTOB>> jFEXFPGA::getTauTOBs() {
574 
575  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
576 
577  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
578  for(auto &j : m_tau_tobwords) {
579  tobsSort.push_back(std::move(j));
580  }
581  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jTau_etBit, 0x7ff));
582 
583  return tobsSort;
584 }
585 
586 std::vector<std::unique_ptr<jFEXTOB>> jFEXFPGA::getSumEtTOBs() {
587 
588  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
589 
590  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
591  for(auto &j : m_sumET_tobwords) {
592  tobsSort.push_back(std::move(j));
593  }
594 
595  return tobsSort;
596 }
597 
598 
599 
600 std::vector<std::unique_ptr<jFEXTOB>> jFEXFPGA::getMetTOBs() {
601 
602  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
603 
604  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
605  for(auto &j : m_Met_tobwords) {
606  tobsSort.push_back(std::move(j));
607  }
608 
609  return tobsSort;
610 }
611 
612 
613 //Returns the Electromagnetic energy for Jet Algos (NOT MET/SumET)
614 int jFEXFPGA::getTTowerET_EM(unsigned int TTID) {
615 
616  if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
617  return m_map_EM_Etvalues_FPGA[TTID][0];
618  }
619 
620  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_EM, TTower ID not found in map: " << TTID );
621  return -99999;
622 }
623 
624 
625 //Returns the Hadronic energy for Jet Algos (NOT MET/SumET)
626 int jFEXFPGA::getTTowerET_HAD(unsigned int TTID) {
627 
628  if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
629  return m_map_HAD_Etvalues_FPGA[TTID][0];
630  }
631 
632  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_HAD, TTower ID not found in map: " << TTID );
633  return -99999;
634 }
635 
636 
637 //Returns the Total TT energy for Jet Algos (NOT MET/SumET)
638 int jFEXFPGA::getTTowerET(unsigned int TTID) {
639 
640  return getTTowerET_EM(TTID)+getTTowerET_HAD(TTID);
641 }
642 
643 
644 //Returns the Total TT energy for MET/SumÉT Algos
645 int jFEXFPGA::getTTowerET_forMET(unsigned int TTID) {
646 
647  int tmp_EM = 0;
648  if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
649  tmp_EM = m_map_EM_Etvalues_FPGA[TTID][1];
650  }
651  else{
652  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (EM energy), TTower ID not found in map: " << TTID );
653  tmp_EM = -99999;
654  }
655 
656 
657  int tmp_HAD = 0;
658  if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
659  tmp_HAD = m_map_HAD_Etvalues_FPGA[TTID][1];
660  }
661  else{
662  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (HAD energy), TTower ID not found in map: " << TTID );
663  tmp_HAD = -99999;
664  }
665 
666 
667  return tmp_EM + tmp_HAD;
668 }
669 
670 
671 //Returns de ET of a given TT ID for Algorithm
672 int jFEXFPGA::getTTowerET_SG(unsigned int TTID) {
673 
674  if(TTID == 0){
675  return -999;
676  }
677  SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey);
678  const LVL1::jTower * tmpTower = jTowerContainer->findTower(TTID);
679  return tmpTower->getTotalET();
680 }
681 
682 
683 } // end of namespace bracket
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Calculate variables for top word.
Definition: jFEXForwardElecInfo.cxx:188
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StatusCode initialize(bool used=true)
If this object is used as a property, then this should be called during the initialize phase.
Definition: AthToolSupport/AsgDataHandles/Root/VarHandleKey.cxx:103
LVL1::jFEXFPGA::SetTowersAndCells_SG
virtual void SetTowersAndCells_SG(int[][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]) override
Definition: jFEXFPGA.cxx:493
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Definition: jTowerContainer.h:33
LVL1::jFEXFPGA::m_jfexid
int m_jfexid
Definition: jFEXFPGA.h:110
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Definition: HLTChainList.h:35
jFEXForwardJetsInfo.h
LVL1::jFEXFPGA::m_LRJet_tobwords
std::vector< std::unique_ptr< jFEXTOB > > m_LRJet_tobwords
Definition: jFEXFPGA.h:105
LVL1::jFEXOutputCollection::fill_pileup
void fill_pileup()
Definition: jFEXOutputCollection.cxx:136
id
SG::auxid_t id
Definition: Control/AthContainers/Root/debug.cxx:239
LVL1::jFEXFPGA::getFwdElTOBs
virtual std::vector< std::vector< uint32_t > > getFwdElTOBs() override
sorted Electron tobs
Definition: jFEXFPGA.cxx:561
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LVL1::jFEXForwardJetsInfo::getSRjetSat
bool getSRjetSat()
Definition: jFEXForwardJetsInfo.h:31
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Definition: L1ThrExtraInfo.h:298
LVL1::jFEXFPGA::etFwdElSort
static bool etFwdElSort(const std::vector< uint32_t > &i, const std::vector< uint32_t > &j)
Definition: jFEXFPGA.h:101
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unsigned int resolutionMeV() const
Definition: L1ThresholdBase.h:101
LVL1::jFEXForwardElecInfo::getEt
uint getEt()
Definition: jFEXForwardElecInfo.cxx:160
LVL1::jFEXFPGA::m_jFEXForwardElecAlgoTool
ToolHandle< IjFEXForwardElecAlgo > m_jFEXForwardElecAlgoTool
Definition: jFEXFPGA.h:140
LVL1::jFEXFPGA::m_jFEXmetAlgoTool
ToolHandle< IjFEXmetAlgo > m_jFEXmetAlgoTool
Definition: jFEXFPGA.h:138
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virtual StatusCode execute(jFEXOutputCollection *inputOutputCollection, const std::pair< unsigned int, const std::vector< int > & > &jetCalibrationParameters) override
Definition: jFEXFPGA.cxx:78
LVL1::jFEXFPGA::getSumEtTOBs
virtual std::vector< std::unique_ptr< jFEXTOB > > getSumEtTOBs() override
Form a tob word out of the potential candidate SumET tob.
Definition: jFEXFPGA.cxx:586
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@ MEDIUM
LVL1::jFEXFPGA::m_map_EM_Etvalues_FPGA
std::unordered_map< int, std::vector< int > > m_map_EM_Etvalues_FPGA
Definition: jFEXFPGA.h:120
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@ TIGHT
LVL1::jFEXForwardJetsInfo::getSecondEnergyRingET
int getSecondEnergyRingET()
Definition: jFEXForwardJetsInfo.cxx:105
LVL1::jFEXFPGA::m_map_HAD_Etvalues_FPGA
std::unordered_map< int, std::vector< int > > m_map_HAD_Etvalues_FPGA
Definition: jFEXFPGA.h:119
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Definition: jFEXOutputCollection.cxx:97
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Definition: jFEXFPGA.h:109
LVL1::jFEXFPGA::~jFEXFPGA
virtual ~jFEXFPGA()
Destructor.
Definition: jFEXFPGA.cxx:41
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val
Definition: Pythia8_RapidityOrderMPI.py:14
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int getTTowerET_EM(unsigned int TTID) override
Definition: jFEXFPGA.cxx:614
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jFEXmetAlgo.h
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int getSeedET()
Definition: jFEXForwardJetsInfo.cxx:68
LVL1::jTower
The jTower class is an interface object for jFEX trigger algorithms The purposes are twofold:
Definition: jTower.h:36
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unsigned int ptMinToTopoMeV(const std::string &module) const
Definition: L1ThrExtraInfo.h:224
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Definition: jFEXForwardElecInfo.h:23
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Definition: L1ThrExtraInfo.h:437
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Definition: calibdata.py:26
ReadHandle.h
Handle class for reading from StoreGate.
AthAlgTool
Definition: AthAlgTool.h:26
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const L1ThrExtraInfo_jTE & jTE() const
Definition: L1ThrExtraInfo.cxx:173
jFEXFormTOBs.h
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Definition: L1ThrExtraInfo.h:191
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int m_SRJetET
Definition: jFEXFPGA.h:126
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constexpr int pow(int base, int exp) noexcept
Definition: ap_fixedTest.cxx:15
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float deltaR
Definition: makeComparison.py:36
LVL1::jFEXFPGA::getTTowerET_SG
int getTTowerET_SG(unsigned int TTID)
Definition: jFEXFPGA.cxx:672
LVL1::jFEXForwardElecInfo::getTobWord
uint32_t getTobWord()
Definition: jFEXForwardElecInfo.cxx:172
LVL1::jFEXFPGA::m_jFEXLargeRJetAlgoTool
ToolHandle< IjFEXLargeRJetAlgo > m_jFEXLargeRJetAlgoTool
Definition: jFEXFPGA.h:135
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Definition: L1ThrExtraInfo.h:392
LVL1::jFEXFPGA::m_jFEXPileupAndNoiseTool
ToolHandle< IjFEXPileupAndNoise > m_jFEXPileupAndNoiseTool
Definition: jFEXFPGA.h:141
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Definition: TElectronEfficiencyCorrectionTool.cxx:37
LVL1::jFEXFPGA::m_jTowersIDs_Thin
int m_jTowersIDs_Thin[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]
Definition: jFEXFPGA.h:115
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