ATLAS Offline Software
jFEXFPGA.cxx
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1 /*
2  Copyright (C) 2002-2024 CERN for the benefit of the ATLAS collaboration
3 */
4 
5 //***************************************************************************
6 // jFEXFPGA - description
7 // -------------------
8 // begin : 19 10 2020
9 // email : jacob.julian.kempster@cern.ch
10 // ***************************************************************************/
11 
12 #include "L1CaloFEXSim/jFEXFPGA.h"
13 #include "L1CaloFEXSim/jTower.h"
14 #include "L1CaloFEXSim/jFEXSmallRJetAlgo.h"
15 #include "L1CaloFEXSim/jFEXLargeRJetAlgo.h"
16 #include "L1CaloFEXSim/jFEXOutputCollection.h"
17 #include "L1CaloFEXSim/jFEXtauAlgo.h"
18 #include "L1CaloFEXSim/jFEXsumETAlgo.h"
19 #include "L1CaloFEXSim/jFEXmetAlgo.h"
20 #include "L1CaloFEXSim/jFEXForwardJetsAlgo.h"
21 #include "L1CaloFEXSim/jFEXForwardJetsInfo.h"
22 #include "L1CaloFEXSim/jFEXForwardElecAlgo.h"
23 #include "L1CaloFEXSim/jFEXForwardElecInfo.h"
24 #include "L1CaloFEXSim/jFEXPileupAndNoise.h"
25 #include "L1CaloFEXSim/jFEXFormTOBs.h"
26 #include "L1CaloFEXSim/jFEXTOB.h"
27 
28 
29 namespace LVL1 {
30 
31  // default constructor for persistency
32 
33 jFEXFPGA::jFEXFPGA(const std::string& type,const std::string& name,const IInterface* parent): AthAlgTool(type,name,parent) {
34  declareInterface<IjFEXFPGA>(this);
35 }
36 
38 jFEXFPGA::~jFEXFPGA()
39 {
40 }
41 
42 //================ Initialisation =================================================
43 
44 StatusCode jFEXFPGA::initialize() {
45 
46  ATH_CHECK(m_jTowerContainerKey.initialize());
47  ATH_CHECK(m_l1MenuKey.initialize());
48  ATH_CHECK(m_jFEXtauAlgoTool.retrieve());
49  return StatusCode::SUCCESS;
50 }
51 
52 StatusCode jFEXFPGA::init(int id, int jfexid) {
53  m_id = id;
54  m_jfexid = jfexid;
55 
56  return StatusCode::SUCCESS;
57 
58 }
59 
60 void jFEXFPGA::reset() {
61 
62  m_id = -1;
63  m_jfexid = -1;
64  m_tau_tobwords.clear();
65  m_SRJet_tobwords.clear();
66  m_LRJet_tobwords.clear();
67  m_sumET_tobwords.clear();
68  m_Met_tobwords.clear();
69  m_map_Etvalues_FPGA.clear();
70  m_map_EM_Etvalues_FPGA.clear();
71  m_map_HAD_Etvalues_FPGA.clear();
72  m_FwdEl_tobwords.clear();
73 }
74 
75 StatusCode jFEXFPGA::execute(jFEXOutputCollection* inputOutputCollection, const std::pair<unsigned int, const std::vector<int>&> & jetCalibrationParameters) {
76 
77  // Retrieve the L1 menu configuration
78  SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
79 
80  const TrigConf::L1ThrExtraInfo_jTAU & thr_jTAU = l1Menu->thrExtraInfo().jTAU();
81  const TrigConf::L1ThrExtraInfo_jJ & thr_jJ = l1Menu->thrExtraInfo().jJ();
82  const TrigConf::L1ThrExtraInfo_jLJ & thr_jLJ = l1Menu->thrExtraInfo().jLJ();
83  const TrigConf::L1ThrExtraInfo_jTE & thr_jTE = l1Menu->thrExtraInfo().jTE();
84  const TrigConf::L1ThrExtraInfo_jXE & thr_jXE = l1Menu->thrExtraInfo().jXE();
85 
86  SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey/*,ctx*/);
87  if(!jTowerContainer.isValid()) {
88  ATH_MSG_ERROR("Could not retrieve container " << m_jTowerContainerKey.key() );
89  return StatusCode::FAILURE;
90  }
91 
92  ATH_CHECK( m_jFEXPileupAndNoiseTool->safetyTest());
93  ATH_CHECK( m_jFEXPileupAndNoiseTool->reset());
94  if(m_jfexid == 0 || m_jfexid == 5) {
95  m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Wide);
96  }
97  else {
98  m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Thin);
99  }
100 
101  //Calculating and sustracting pileup
102  const std::vector<int> pileup_rho = m_jFEXPileupAndNoiseTool->CalculatePileup();
103 
104  //From the DB
105  ATH_CHECK(m_jFEXPileupAndNoiseTool->ApplyPileup());
106 
107  //Noise should be always applied
108  m_jFEXPileupAndNoiseTool->ApplyNoise2Jets(true);
109  m_jFEXPileupAndNoiseTool->ApplyNoise2Met(true);
110  //Getting the values
111  m_map_HAD_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_HAD_Et_values();
112  m_map_EM_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_EM_Et_values();
113  m_map_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->GetEt_values();
114  std::vector<int> pileup_ID;
115  std::vector<int> pileup_HAD_jet;
116  std::vector<int> pileup_EM_jet;
117  std::vector<int> pileup_Total_jet;
118  std::vector<int> pileup_HAD_met;
119  std::vector<int> pileup_EM_met;
120  std::vector<int> pileup_Total_met;
121  for (auto const& [key, val] : m_map_HAD_Etvalues_FPGA)
122  {
123  pileup_ID.push_back(key);
124  pileup_HAD_jet.push_back(val[0]);
125  pileup_EM_jet.push_back(m_map_EM_Etvalues_FPGA[key][0]);
126  pileup_Total_jet.push_back(m_map_Etvalues_FPGA[key][0]);
127  pileup_HAD_met.push_back(val[1]);
128  pileup_EM_met.push_back(m_map_EM_Etvalues_FPGA[key][1]);
129  pileup_Total_met.push_back(m_map_Etvalues_FPGA[key][1]);
130  }
131 
132  //saving pileup information
133  inputOutputCollection->addValue_pileup("pileup_FPGAid", m_id);
134  inputOutputCollection->addValue_pileup("pileup_jFEXid", m_jfexid);
135  inputOutputCollection->addValue_pileup("pileup_rho_EM", pileup_rho[0]);
136  inputOutputCollection->addValue_pileup("pileup_rho_HAD1", pileup_rho[1]);
137  inputOutputCollection->addValue_pileup("pileup_rho_HAD2", pileup_rho[2]);
138  inputOutputCollection->addValue_pileup("pileup_rho_HAD3", pileup_rho[3]);
139  inputOutputCollection->addValue_pileup("pileup_rho_FCAL", pileup_rho[4]);
140  inputOutputCollection->addValue_pileup("pileup_map_ID" , std::move(pileup_ID));
141  inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_jet" , std::move(pileup_HAD_jet));
142  inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_jet" , std::move(pileup_EM_jet));
143  inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_jet", std::move(pileup_Total_jet));
144  inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_met" , std::move(pileup_HAD_met));
145  inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_met" , std::move(pileup_EM_met));
146  inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_met", std::move(pileup_Total_met));
147  inputOutputCollection->fill_pileup();
148 
149  if(m_id==0 || m_id==3) {
150  ATH_CHECK( m_jFEXsumETAlgoTool->safetyTest());
151  ATH_CHECK( m_jFEXsumETAlgoTool->reset());
152  ATH_CHECK( m_jFEXmetAlgoTool->safetyTest());
153  ATH_CHECK( m_jFEXmetAlgoTool->reset());
154 
155  m_jFEXsumETAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
156  m_jFEXmetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
157 
158  unsigned int bin_pos = thr_jTE.etaBoundary_fw(m_jfex_string[m_jfexid]);
159 
160  std::unique_ptr<jFEXTOB> jXE_tob = std::make_unique<jFEXTOB>();
161  uint32_t jXE_tobword = 0;
162 
163  std::unique_ptr<jFEXTOB> jTE_tob = std::make_unique<jFEXTOB>();
164  uint32_t jTE_tobword = 0;
165 
166 
167  int hemisphere = m_id == 0 ? 1 : -1;
168 
169  if(m_jfexid > 0 && m_jfexid < 5) {
170 
171  //-----------------jFEXsumETAlgo-----------------
172  m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Thin);
173  m_jFEXsumETAlgoTool->buildBarrelSumET();
174 
175  //-----------------jFEXmetAlgo-----------------
176  m_jFEXmetAlgoTool->setup(m_jTowersIDs_Thin, hemisphere);
177  m_jFEXmetAlgoTool->buildBarrelmet();
178  }
179  else if(m_jfexid == 0 ) {
180 
181  int flipped_jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}};
182  int max_phi_it = FEXAlgoSpaceDefs::jFEX_algoSpace_height-1;
183  int max_eta_it = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-1;
184  for(int mphi = 0; mphi <= max_phi_it; mphi++) {
185  for(int meta = 0; meta <= max_eta_it; meta++) {
186  flipped_jTowersIDs[mphi][meta]=m_jTowersIDs_Wide[mphi][max_eta_it-meta];
187  }
188  }
189  //-----------------jFEXsumETAlgo-----------------
190  m_jFEXsumETAlgoTool->setup(flipped_jTowersIDs);
191  m_jFEXsumETAlgoTool->buildFWDSumET();
192 
193  //-----------------jFEXmetAlgo-----------------
194  m_jFEXmetAlgoTool->setup(flipped_jTowersIDs, hemisphere);
195  m_jFEXmetAlgoTool->buildFWDmet();
196  }
197  else if(m_jfexid == 5) {
198 
199  //-----------------jFEXsumETAlgo-----------------
200  m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Wide);
201  m_jFEXsumETAlgoTool->buildFWDSumET();
202 
203  //-----------------jFEXmetAlgo-----------------
204  m_jFEXmetAlgoTool->setup(m_jTowersIDs_Wide, hemisphere);
205  m_jFEXmetAlgoTool->buildFWDmet();
206  }
207 
208  jXE_tobword = m_IjFEXFormTOBsTool->formMetTOB(m_jFEXmetAlgoTool->GetMetXComponent(), m_jFEXmetAlgoTool->GetMetYComponent(),m_jFEXmetAlgoTool->getjXESat(),thr_jXE.resolutionMeV());
209  jXE_tob->initialize(m_id,m_jfexid,jXE_tobword,thr_jXE.resolutionMeV(),0);
210  m_Met_tobwords.push_back(std::move(jXE_tob));
211 
212  std::tuple<int,bool> jTElow;
213  std::tuple<int,bool> jTEhigh;
214 
215  // NOTE: Foward FPGA in the C-side is already flipped, however we still need to flip the jFEX module 1 and 2
216  if(m_jfexid == 1 || m_jfexid == 2){
217  jTElow = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
218  jTEhigh = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
219  }
220  else{
221  jTElow = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
222  jTEhigh = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
223  }
224 
225  jTE_tobword = m_IjFEXFormTOBsTool->formSumETTOB(jTElow,jTEhigh,thr_jTE.resolutionMeV());
226  jTE_tob->initialize(m_id,m_jfexid,jTE_tobword,thr_jTE.resolutionMeV(),0);
227  m_sumET_tobwords.push_back(std::move(jTE_tob));
228  }
229 
230  //-----------jFEXSmallRJet & Large R Jet Algo-----------------
231  ATH_MSG_DEBUG("================ Central Algorithms ================");
232 
233  int srJet_seedThresholdMeV = thr_jJ.seedThresholdMeV(m_jfex_string[m_jfexid]); //jFEX internal granularity, i.e., 25 MeV/count
234 
235 
236  //Central region algorithms
237  if(m_jfexid > 0 && m_jfexid < 5) {
238  m_jFEXSmallRJetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
239  m_jFEXLargeRJetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
240  m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
241 
242  for(int mphi = 8; mphi < FEXAlgoSpaceDefs::jFEX_algoSpace_height-8; mphi++) {
243  for(int meta = 8; meta < FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width-8; meta++) {
244 
245  //definition of arrays
246  int TT_seed_ID[3][3]= {{0}};
247  int TT_First_ETring[36]= {0};
248  int First_ETring_it = 0;
249 
250  int Jet_SearchWindow[7][7] = {{0}};
251  int Jet_SearchWindowDisplaced[7][7] = {{0}};
252  int largeRCluster_IDs[15][15]= {{0}};
253 
254  //filling up array to send them to the algorithms
255  for(int i = -7; i< 8; i++ ) {
256  for(int j = -7; j< 8; j++) {
257 
258  if(std::abs(i)<4 && std::abs(j)<4) {
259  Jet_SearchWindow[3 + i][3 + j] = m_jTowersIDs_Thin[mphi + i][meta +j];
260  Jet_SearchWindowDisplaced[3 + i][3 + j] = m_jTowersIDs_Thin[mphi+i+1][meta+j+1];
261  }
262 
263  uint deltaR = std::sqrt(std::pow(i,2)+std::pow(j,2));
264 
265  if(deltaR<2) {
266  TT_seed_ID[i+1][j+1] = m_jTowersIDs_Thin[mphi +i][meta +j]; // Seed 0.3x0.3 in phi-eta plane
267  }
268  else if(deltaR<4) {
269  TT_First_ETring[First_ETring_it]= m_jTowersIDs_Thin[mphi +i][meta +j]; // First energy ring, will be used as tau ISO
270  ++First_ETring_it;
271 
272  }
273  else if(deltaR<8) {
274  largeRCluster_IDs[7 +i][7 +j] = m_jTowersIDs_Thin[mphi + i][meta +j];
275  }
276  }
277  }
278 
279  // ******** jJ and jLJ algorithms ********
280  ATH_CHECK( m_jFEXSmallRJetAlgoTool->safetyTest());
281  ATH_CHECK( m_jFEXLargeRJetAlgoTool->safetyTest());
282  m_jFEXSmallRJetAlgoTool->setup(Jet_SearchWindow, Jet_SearchWindowDisplaced);
283  m_jFEXLargeRJetAlgoTool->setupCluster(largeRCluster_IDs);
284  m_jFEXSmallRJetAlgoTool->buildSeeds();
285 
286  bool is_Jet_LM = m_jFEXSmallRJetAlgoTool->isSeedLocalMaxima(srJet_seedThresholdMeV);
287 
288  if(is_Jet_LM) {
289 
290  //getting the energies
291  int SRj_Et = m_jFEXSmallRJetAlgoTool->getSmallClusterET();
292  int LRj_Et = m_jFEXLargeRJetAlgoTool->getLargeClusterET(SRj_Et,m_jFEXLargeRJetAlgoTool->getRingET());
293  int seed_Et = m_jFEXSmallRJetAlgoTool->getSeedET();
294 
295  bool SRj_Sat = m_jFEXSmallRJetAlgoTool->getSRjetSat();
296  bool LRj_Sat = SRj_Sat || m_jFEXLargeRJetAlgoTool->getLRjetSat();
297 
298  int meta_LM = meta;
299  int mphi_LM = mphi;
300 
301 
302  //Creating SR TOB
303  uint32_t SRJet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, mphi_LM, meta_LM, SRj_Et, SRj_Sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
304 
305  std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
306  jJ_tob->initialize(m_id,m_jfexid,SRJet_tobword,thr_jJ.resolutionMeV(),m_jTowersIDs_Thin[mphi_LM][meta_LM],seed_Et);
307  if ( SRJet_tobword != 0 ){
308  m_SRJet_tobwords.push_back(std::move(jJ_tob));
309  }
310 
311  //Creating LR TOB
312  uint32_t LRJet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, mphi_LM, meta_LM, LRj_Et, LRj_Sat, thr_jLJ.resolutionMeV(), thr_jLJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
313 
314  std::unique_ptr<jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
315  jLJ_tob->initialize(m_id,m_jfexid,LRJet_tobword,thr_jLJ.resolutionMeV(),m_jTowersIDs_Thin[mphi_LM][meta_LM],seed_Et);
316  if ( LRJet_tobword != 0 ) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
317 
318  }
319  // ******** jTau algorithm ********
320 
321  ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
322  m_jFEXtauAlgoTool->setup(TT_seed_ID);
323  bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima();
324 
325  // Save TOB is tau is a local maxima
326  if ( is_tau_LocalMax ) {
327 
328  //calculates the 1st energy ring
329  m_jFEXtauAlgoTool->setFirstEtRing(TT_First_ETring);
330 
331 
332  uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
333 
334  std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
335  jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),m_jTowersIDs_Thin[mphi][meta]);
336 
337  if ( jTau_tobword != 0 ){
338  m_tau_tobwords.push_back(std::move(jTau_tob));
339  }
340  }
341  }
342  }
343  } //end of if statement for checking if in central jfex modules
344 
345  //FCAL region algorithm
346  if(m_jfexid ==0 || m_jfexid ==5) {
347 
348  //**********Forward Jets***********************
349  ATH_CHECK(m_jFEXForwardJetsAlgoTool->safetyTest());
350  ATH_CHECK(m_jFEXForwardJetsAlgoTool->reset());
351  m_jFEXForwardJetsAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
352  m_jFEXForwardJetsAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid);
353 
354  m_FCALJets = m_jFEXForwardJetsAlgoTool->calculateJetETs(srJet_seedThresholdMeV);
355  for(std::unordered_map<int, jFEXForwardJetsInfo>::iterator it = m_FCALJets.begin(); it!=(m_FCALJets.end()); ++it) {
356 
357  uint32_t TTID = it->first;
358  jFEXForwardJetsInfo FCALJets = it->second;
359 
360  int iphi = FCALJets.getCentreLocalTTPhi();
361  int ieta = FCALJets.getCentreLocalTTEta();
362  m_SRJetET = FCALJets.getSeedET() + FCALJets.getFirstEnergyRingET();
363  m_LRJetET = m_SRJetET + FCALJets.getSecondEnergyRingET();
364  int seedET = FCALJets.getSeedET();
365 
366  bool SRJ_sat = FCALJets.getSRjetSat();
367 
368  uint32_t SRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, iphi, ieta, m_SRJetET, SRJ_sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
369 
370  std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
371  jJ_tob->initialize(m_id,m_jfexid,SRFCAL_Jet_tobword,thr_jJ.resolutionMeV(),TTID,seedET);
372 
373  if ( SRFCAL_Jet_tobword != 0 ){
374  m_SRJet_tobwords.push_back(std::move(jJ_tob));
375  }
376 
377  if(std::fabs(FCALJets.getCentreTTEta())<2.51){
378  bool LRJ_sat = FCALJets.getLRjetSat();
379  uint32_t LRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, iphi, ieta, m_LRJetET, LRJ_sat, thr_jLJ.resolutionMeV(),thr_jLJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
380 
381  std::unique_ptr<jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
382  jLJ_tob->initialize(m_id,m_jfexid,LRFCAL_Jet_tobword,thr_jLJ.resolutionMeV(),TTID);
383  if ( LRFCAL_Jet_tobword != 0 ) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
384  }
385 
386  }
387  //********** Forward Electrons ***********************
388  ATH_CHECK(m_jFEXForwardElecAlgoTool->safetyTest());
389  ATH_CHECK(m_jFEXForwardElecAlgoTool->reset());
390  m_jFEXForwardElecAlgoTool->setFPGAEnergy(m_map_EM_Etvalues_FPGA,m_map_HAD_Etvalues_FPGA);
391  m_jFEXForwardElecAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid,m_id);
392  m_ForwardElecs = m_jFEXForwardElecAlgoTool->calculateEDM();
393 
395  SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
396  const TrigConf::L1ThrExtraInfo_jEM & thr_jEM = l1Menu->thrExtraInfo().jEM();
397  const uint jFEXETResolution = thr_jEM.resolutionMeV();//200
398  std::string str_jfexname = m_jfex_string[m_jfexid];
399  uint minEtThreshold = thr_jEM.ptMinToTopoMeV(str_jfexname)/jFEXETResolution;
400  //uint Cval[9] = {1,2,3,20,30,40,20,30,40};//C values for iso, emfr1 and emfr2
401  std::vector<int> Ciso;
402  std::vector<int> Chad1;
403  std::vector<int> Chad2;
404 
405  for(std::unordered_map<uint, jFEXForwardElecInfo>::iterator itel = m_ForwardElecs.begin(); itel!=(m_ForwardElecs.end()); ++itel) {
406  uint32_t TTID = itel->first;
407  jFEXForwardElecInfo elCluster = itel->second;
408  uint meta = elCluster.getCoreIeta();//check whether this is the one used by the Trigger conf
409 
410  //retrieve jet rejection thresholds from trigger configuration
411  const auto & wp_loose = thr_jEM.isolation(TrigConf::Selection::WP::LOOSE, meta);
412  const auto & wp_medium = thr_jEM.isolation(TrigConf::Selection::WP::MEDIUM, meta);
413  const auto & wp_tight = thr_jEM.isolation(TrigConf::Selection::WP::TIGHT, meta);
414  Ciso.clear();
415  Chad1.clear();
416  Chad2.clear();
417  Ciso.push_back(wp_loose.iso_fw());
418  Ciso.push_back(wp_medium.iso_fw());
419  Ciso.push_back(wp_tight.iso_fw());
420  Chad1.push_back(wp_loose.frac_fw());
421  Chad1.push_back(wp_medium.frac_fw());
422  Chad1.push_back(wp_tight.frac_fw());
423  Chad2.push_back(wp_loose.frac2_fw());
424  Chad2.push_back(wp_medium.frac2_fw());
425  Chad2.push_back(wp_tight.frac2_fw());
426  int Cval[9] = {Ciso[0], Ciso[1], Ciso[2], Chad1[0], Chad1[1], Chad1[2], Chad2[0], Chad2[1], Chad2[2]};
427 
428  elCluster.setup(Cval,jFEXETResolution);
429  elCluster.calcFwdElEDM();
430 
431  uint etEM = elCluster.getEt();
432  uint32_t FwdEl_tobword = elCluster.getTobWord();
433 
434 
435  std::vector<uint32_t> FwdEltob_aux{FwdEl_tobword,TTID};
436  if ( FwdEl_tobword != 0 && etEM>minEtThreshold) m_FwdEl_tobwords.push_back(FwdEltob_aux);
437  }
438 
439  //******************************** TAU **********************************************
440  int jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}};
441  int max_meta=17;
442 
443  if(m_jfexid ==0) {
444  for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
445  for(int j=28; j<(FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-6); j++) { //lower values of j (j<28) are the Fcals not entering in the jFEX tau range
446  jTowersIDs[i][j-28+8]=m_jTowersIDs_Wide[i][j]; // second argument in m_jTowersIDs is to center the FPGA core area in te same region as the central FPGAs
447  }
448  }
449 
450  }
451  else if(m_jfexid ==5 ) {
452 
453  // Filling m_jTowersIDs with the m_jTowersIDs_Wide ID values up to 2.5 eta
454  for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
455  for(int j=4; j<17; j++) { //higher values of j (j>16) are the Fcals not entering in the jFEX tau range
456  jTowersIDs[i][j]=m_jTowersIDs_Wide[i][j];
457  }
458  }
459  }
460  ATH_MSG_DEBUG("============================ jFEXtauAlgo ============================");
461  ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
462  m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
463  for(int mphi = 8; mphi < 24; mphi++) {
464  for(int meta = 8; meta < max_meta; meta++) {
465 
466  bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima_fwd(jTowersIDs[mphi][meta]);
467 
468  // Save TOB is tau is a local maxima
469  if ( is_tau_LocalMax ) {
470 
471  uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
472 
473  std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
474  jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),jTowersIDs[mphi][meta]);
475  if ( jTau_tobword != 0 ){
476  m_tau_tobwords.push_back(std::move(jTau_tob));
477  }
478  }
479  }
480  }
481  } //end of if statement for checking if in central jfex modules
482  return StatusCode::SUCCESS;
483 } //end of the execute function
484 
485 void jFEXFPGA::SetTowersAndCells_SG(int tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]){
486 
487  const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
488  const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
489 
490  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Wide[0][0]);
491 
492  ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
493 
494  for (int thisRow=rows-1; thisRow>=0; thisRow--){
495  for (int thisCol=0; thisCol<cols; thisCol++){
496  if(thisCol != cols-1){ ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " "); }
497  else { ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " |"); }
498  }
499  }
500 
501 }
502 
503 void jFEXFPGA::SetTowersAndCells_SG(int tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]) {
504 
505  const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
506  const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
507 
508  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Thin[0][0]);
509 
510  //this prints out the jTower IDs that each FPGA is responsible for
511  ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
512 
513  for (int thisRow=rows-1; thisRow>=0; thisRow--) {
514  for (int thisCol=0; thisCol<cols; thisCol++) {
515  if(thisCol != cols-1) {
516  ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " ");
517  }
518  else {
519  ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " |");
520  }
521  }
522  }
523 
524 }
525 
526 std::vector <std::unique_ptr<jFEXTOB>> jFEXFPGA::getSmallRJetTOBs()
527 {
528 
529  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
530  tobsSort.clear();
531 
532  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
533  for(auto &j : m_SRJet_tobwords) {
534  tobsSort.push_back(std::move(j));
535  }
536  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jJ_etBit, 0x7ff));
537 
538  return tobsSort;
539 
540 }
541 
542 std::vector <std::unique_ptr<jFEXTOB>> jFEXFPGA::getLargeRJetTOBs()
543 {
544 
545 
546  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
547  tobsSort.clear();
548 
549  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
550  for(auto &j : m_LRJet_tobwords) {
551  tobsSort.push_back(std::move(j));
552  }
553  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jLJ_etBit, 0x1fff));
554 
555  return tobsSort;
556 
557 }
558 
559 
560  std::vector <std::vector <uint32_t>> jFEXFPGA::getFwdElTOBs()
561  {
562  auto tobsSort = m_FwdEl_tobwords;
563 
564  ATH_MSG_DEBUG("number of Forward Elec tobs: " << tobsSort.size() << " in FPGA: " << m_id<< " before truncation");
565  //sort tobs by their et
566  std::sort (tobsSort.begin(), tobsSort.end(), etFwdElSort);
567 
568  return tobsSort;
569 
570  }
571 
572 
573 std::vector <std::unique_ptr<jFEXTOB>> jFEXFPGA::getTauTOBs() {
574 
575  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
576  tobsSort.clear();
577 
578  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
579  for(auto &j : m_tau_tobwords) {
580  tobsSort.push_back(std::move(j));
581  }
582  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jTau_etBit, 0x7ff));
583 
584  return tobsSort;
585 }
586 
587 std::vector<std::unique_ptr<jFEXTOB>> jFEXFPGA::getSumEtTOBs() {
588 
589  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
590  tobsSort.clear();
591 
592  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
593  for(auto &j : m_sumET_tobwords) {
594  tobsSort.push_back(std::move(j));
595  }
596 
597  return tobsSort;
598 
599 }
600 
601 
602 
603 std::vector<std::unique_ptr<jFEXTOB>> jFEXFPGA::getMetTOBs() {
604 
605  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
606  tobsSort.clear();
607 
608  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
609  for(auto &j : m_Met_tobwords) {
610  tobsSort.push_back(std::move(j));
611  }
612 
613  return tobsSort;
614 
615 }
616 
617 
618 //Returns the Electromagnetic energy for Jet Algos (NOT MET/SumET)
619 int jFEXFPGA::getTTowerET_EM(unsigned int TTID) {
620 
621  if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
622  return m_map_EM_Etvalues_FPGA[TTID][0];
623  }
624 
625  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_EM, TTower ID not found in map: " << TTID );
626  return -99999;
627 
628 }
629 
630 
631 //Returns the Hadronic energy for Jet Algos (NOT MET/SumET)
632 int jFEXFPGA::getTTowerET_HAD(unsigned int TTID) {
633 
634  if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
635  return m_map_HAD_Etvalues_FPGA[TTID][0];
636  }
637 
638  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_HAD, TTower ID not found in map: " << TTID );
639  return -99999;
640 
641 }
642 
643 
644 //Returns the Total TT energy for Jet Algos (NOT MET/SumET)
645 int jFEXFPGA::getTTowerET(unsigned int TTID) {
646 
647  return getTTowerET_EM(TTID)+getTTowerET_HAD(TTID);
648 
649 }
650 
651 
652 //Returns the Total TT energy for MET/SumÉT Algos
653 int jFEXFPGA::getTTowerET_forMET(unsigned int TTID) {
654 
655  int tmp_EM = 0;
656  if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
657  tmp_EM = m_map_EM_Etvalues_FPGA[TTID][1];
658  }
659  else{
660  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (EM energy), TTower ID not found in map: " << TTID );
661  tmp_EM = -99999;
662  }
663 
664 
665  int tmp_HAD = 0;
666  if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
667  tmp_HAD = m_map_HAD_Etvalues_FPGA[TTID][1];
668  }
669  else{
670  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (HAD energy), TTower ID not found in map: " << TTID );
671  tmp_HAD = -99999;
672  }
673 
674 
675  return tmp_EM + tmp_HAD;
676 
677 }
678 
679 
680 //Returns de ET of a given TT ID for Algorithm
681 int jFEXFPGA::getTTowerET_SG(unsigned int TTID) {
682 
683  if(TTID == 0){
684  return -999;
685  }
686  SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey);
687  const LVL1::jTower * tmpTower = jTowerContainer->findTower(TTID);
688  return tmpTower->getTotalET();
689 }
690 
691 
692 
693 
694 
695 
696 } // end of namespace bracket
xAOD::iterator
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Definition: JetConstituentVector.cxx:68
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Calculate variables for top word.
Definition: jFEXForwardElecInfo.cxx:198
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Get ET sum of all cells in the jTower in MeV.
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If this object is used as a property, then this should be called during the initialize phase.
Definition: AthToolSupport/AsgDataHandles/Root/VarHandleKey.cxx:103
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Definition: jFEXFPGA.cxx:485
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Definition: jTowerContainer.h:33
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Definition: jFEXFPGA.h:112
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Definition: HLTChainList.h:35
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Definition: jFEXFPGA.h:107
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Definition: jFEXOutputCollection.cxx:136
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Definition: Control/AthContainers/Root/debug.cxx:227
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virtual std::vector< std::vector< uint32_t > > getFwdElTOBs() override
sorted Electron tobs
Definition: jFEXFPGA.cxx:560
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Definition: jFEXForwardJetsInfo.h:39
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Definition: jFEXFPGA.h:101
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Definition: L1ThresholdBase.h:101
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Definition: jFEXForwardElecInfo.cxx:170
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ToolHandle< IjFEXForwardElecAlgo > m_jFEXForwardElecAlgoTool
Definition: jFEXFPGA.h:141
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Definition: jFEXFPGA.h:139
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Definition: jFEXFPGA.cxx:75
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Definition: jFEXFPGA.cxx:587
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@ MEDIUM
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Definition: jFEXFPGA.h:122
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Definition: jFEXForwardJetsInfo.cxx:116
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Definition: jFEXOutputCollection.cxx:97
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Definition: jFEXFPGA.h:111
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Destructor.
Definition: jFEXFPGA.cxx:38
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Definition: jFEXFPGA.cxx:619
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Definition: jFEXForwardJetsInfo.cxx:79
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The jTower class is an interface object for jFEX trigger algorithms The purposes are twofold:
Definition: jTower.h:40
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unsigned int ptMinToTopoMeV(const std::string &module) const
Definition: L1ThrExtraInfo.h:222
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Definition: jFEXForwardElecInfo.h:28
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Definition: L1ThrExtraInfo.h:435
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Definition: calibdata.py:27
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Definition: AthAlgTool.h:26
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Definition: L1ThrExtraInfo.cxx:173
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Definition: L1ThrExtraInfo.h:189
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Definition: jFEXFPGA.h:128
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constexpr int pow(int base, int exp) noexcept
Definition: ap_fixedTest.cxx:15
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Definition: makeComparison.py:36
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Definition: jFEXFPGA.cxx:681
LVL1::jFEXForwardElecInfo::getTobWord
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Definition: jFEXForwardElecInfo.cxx:182
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Definition: jFEXFPGA.h:136
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Definition: L1ThrExtraInfo.h:390
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ToolHandle< IjFEXPileupAndNoise > m_jFEXPileupAndNoiseTool
Definition: jFEXFPGA.h:142
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Definition: TElectronEfficiencyCorrectionTool.cxx:37
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int m_jTowersIDs_Thin[FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]
Definition: jFEXFPGA.h:117
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