ATLAS Offline Software
jFEXFPGA.cxx
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1 /*
2  Copyright (C) 2002-2023 CERN for the benefit of the ATLAS collaboration
3 */
4 
5 //***************************************************************************
6 // jFEXFPGA - description
7 // -------------------
8 // begin : 19 10 2020
9 // email : jacob.julian.kempster@cern.ch
10 // ***************************************************************************/
11 
12 #include "L1CaloFEXSim/jFEXFPGA.h"
13 #include "L1CaloFEXSim/jTower.h"
14 #include "L1CaloFEXSim/jTowerContainer.h"
15 #include "L1CaloFEXSim/jFEXSmallRJetAlgo.h"
16 #include "L1CaloFEXSim/jFEXLargeRJetAlgo.h"
17 #include "L1CaloFEXSim/jFEXOutputCollection.h"
18 #include "L1CaloFEXSim/FEXAlgoSpaceDefs.h"
19 #include "L1CaloFEXSim/jFEXtauAlgo.h"
20 #include "L1CaloFEXSim/jFEXsumETAlgo.h"
21 #include "L1CaloFEXSim/jFEXmetAlgo.h"
22 #include "L1CaloFEXSim/jFEXForwardJetsAlgo.h"
23 #include "L1CaloFEXSim/jFEXForwardJetsInfo.h"
24 #include "L1CaloFEXSim/jFEXForwardElecAlgo.h"
25 #include "L1CaloFEXSim/jFEXForwardElecInfo.h"
26 #include "L1CaloFEXSim/jFEXPileupAndNoise.h"
27 #include "L1CaloFEXSim/jFEXFormTOBs.h"
28 #include "CaloEvent/CaloCellContainer.h"
29 #include "CaloIdentifier/CaloIdManager.h"
30 #include "CaloIdentifier/CaloCell_SuperCell_ID.h"
31 #include "AthenaBaseComps/AthAlgorithm.h"
32 #include <vector>
33 #include "TrigConfData/L1Menu.h"
34 #include "TH1F.h"
35 #include "GaudiKernel/ServiceHandle.h"
36 #include "GaudiKernel/ISvcLocator.h"
37 #include "GaudiKernel/ITHistSvc.h"
38 #include "GaudiKernel/IClassIDSvc.h"
39 #include "StoreGate/WriteHandle.h"
40 #include "StoreGate/ReadHandle.h"
41 #include "SGTools/TestStore.h"
42 #include "StoreGate/StoreGateSvc.h"
43 
44 
45 namespace LVL1 {
46 
47  // default constructor for persistency
48 
49 jFEXFPGA::jFEXFPGA(const std::string& type,const std::string& name,const IInterface* parent): AthAlgTool(type,name,parent) {
50  declareInterface<IjFEXFPGA>(this);
51 }
52 
54 jFEXFPGA::~jFEXFPGA()
55 {
56 }
57 
58 //================ Initialisation =================================================
59 
60 StatusCode jFEXFPGA::initialize() {
61 
62  ATH_CHECK(m_jTowerContainerKey.initialize());
63  ATH_CHECK(m_l1MenuKey.initialize());
64  ATH_CHECK(m_jFEXtauAlgoTool.retrieve());
65  return StatusCode::SUCCESS;
66 }
67 
68 StatusCode jFEXFPGA::init(int id, int jfexid) {
69  m_id = id;
70  m_jfexid = jfexid;
71 
72  return StatusCode::SUCCESS;
73 
74 }
75 
76 void jFEXFPGA::reset() {
77 
78  m_id = -1;
79  m_jfexid = -1;
80  m_tau_tobwords.clear();
81  m_SRJet_tobwords.clear();
82  m_LRJet_tobwords.clear();
83  m_sumET_tobwords.clear();
84  m_Met_tobwords.clear();
85  m_map_Etvalues_FPGA.clear();
86  m_map_EM_Etvalues_FPGA.clear();
87  m_map_HAD_Etvalues_FPGA.clear();
88  m_FwdEl_tobwords.clear();
89 }
90 
91 StatusCode jFEXFPGA::execute(jFEXOutputCollection* inputOutputCollection, const std::pair<unsigned int, const std::vector<int>&> & jetCalibrationParameters) {
92 
93  // Retrieve the L1 menu configuration
94  SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
95 
96  const TrigConf::L1ThrExtraInfo_jTAU & thr_jTAU = l1Menu->thrExtraInfo().jTAU();
97  const TrigConf::L1ThrExtraInfo_jJ & thr_jJ = l1Menu->thrExtraInfo().jJ();
98  const TrigConf::L1ThrExtraInfo_jLJ & thr_jLJ = l1Menu->thrExtraInfo().jLJ();
99  const TrigConf::L1ThrExtraInfo_jTE & thr_jTE = l1Menu->thrExtraInfo().jTE();
100  const TrigConf::L1ThrExtraInfo_jXE & thr_jXE = l1Menu->thrExtraInfo().jXE();
101 
102  SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey/*,ctx*/);
103  if(!jTowerContainer.isValid()) {
104  ATH_MSG_ERROR("Could not retrieve container " << m_jTowerContainerKey.key() );
105  return StatusCode::FAILURE;
106  }
107 
108  ATH_CHECK( m_jFEXPileupAndNoiseTool->safetyTest());
109  ATH_CHECK( m_jFEXPileupAndNoiseTool->reset());
110  if(m_jfexid == 0 || m_jfexid == 5) {
111  m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Wide);
112  }
113  else {
114  m_jFEXPileupAndNoiseTool->setup(m_jTowersIDs_Thin);
115  }
116 
117  //Calculating and sustracting pileup
118  const std::vector<int> pileup_rho = m_jFEXPileupAndNoiseTool->CalculatePileup();
119 
120  //From the DB
121  ATH_CHECK(m_jFEXPileupAndNoiseTool->ApplyPileup());
122 
123  //Noise should be always applied
124  m_jFEXPileupAndNoiseTool->ApplyNoise2Jets(true);
125  m_jFEXPileupAndNoiseTool->ApplyNoise2Met(true);
126  //Getting the values
127  m_map_HAD_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_HAD_Et_values();
128  m_map_EM_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->Get_EM_Et_values();
129  m_map_Etvalues_FPGA = m_jFEXPileupAndNoiseTool->GetEt_values();
130  std::vector<int> pileup_ID;
131  std::vector<int> pileup_HAD_jet;
132  std::vector<int> pileup_EM_jet;
133  std::vector<int> pileup_Total_jet;
134  std::vector<int> pileup_HAD_met;
135  std::vector<int> pileup_EM_met;
136  std::vector<int> pileup_Total_met;
137  for (auto const& [key, val] : m_map_HAD_Etvalues_FPGA)
138  {
139  pileup_ID.push_back(key);
140  pileup_HAD_jet.push_back(val[0]);
141  pileup_EM_jet.push_back(m_map_EM_Etvalues_FPGA[key][0]);
142  pileup_Total_jet.push_back(m_map_Etvalues_FPGA[key][0]);
143  pileup_HAD_met.push_back(val[1]);
144  pileup_EM_met.push_back(m_map_EM_Etvalues_FPGA[key][1]);
145  pileup_Total_met.push_back(m_map_Etvalues_FPGA[key][1]);
146  }
147 
148  //saving pileup information
149  inputOutputCollection->addValue_pileup("pileup_FPGAid", m_id);
150  inputOutputCollection->addValue_pileup("pileup_jFEXid", m_jfexid);
151  inputOutputCollection->addValue_pileup("pileup_rho_EM", pileup_rho[0]);
152  inputOutputCollection->addValue_pileup("pileup_rho_HAD1", pileup_rho[1]);
153  inputOutputCollection->addValue_pileup("pileup_rho_HAD2", pileup_rho[2]);
154  inputOutputCollection->addValue_pileup("pileup_rho_HAD3", pileup_rho[3]);
155  inputOutputCollection->addValue_pileup("pileup_rho_FCAL", pileup_rho[4]);
156  inputOutputCollection->addValue_pileup("pileup_map_ID" , pileup_ID);
157  inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_jet" , pileup_HAD_jet);
158  inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_jet" , pileup_EM_jet);
159  inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_jet", pileup_Total_jet);
160  inputOutputCollection->addValue_pileup("pileup_map_Et_values_HAD_met" , pileup_HAD_met);
161  inputOutputCollection->addValue_pileup("pileup_map_Et_values_EM_met" , pileup_EM_met);
162  inputOutputCollection->addValue_pileup("pileup_map_Et_values_Total_met", pileup_Total_met);
163  inputOutputCollection->fill_pileup();
164 
165  if(m_id==0 || m_id==3) {
166  ATH_CHECK( m_jFEXsumETAlgoTool->safetyTest());
167  ATH_CHECK( m_jFEXsumETAlgoTool->reset());
168  ATH_CHECK( m_jFEXmetAlgoTool->safetyTest());
169  ATH_CHECK( m_jFEXmetAlgoTool->reset());
170 
171  m_jFEXsumETAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
172  m_jFEXmetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
173 
174  unsigned int bin_pos = thr_jTE.etaBoundary_fw(m_jfex_string[m_jfexid]);
175 
176  std::unique_ptr<jFEXTOB> jXE_tob = std::make_unique<jFEXTOB>();
177  uint32_t jXE_tobword = 0;
178 
179  std::unique_ptr<jFEXTOB> jTE_tob = std::make_unique<jFEXTOB>();
180  uint32_t jTE_tobword = 0;
181 
182 
183  int hemisphere = m_id == 0 ? 1 : -1;
184 
185  if(m_jfexid > 0 && m_jfexid < 5) {
186 
187  //-----------------jFEXsumETAlgo-----------------
188  m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Thin);
189  m_jFEXsumETAlgoTool->buildBarrelSumET();
190 
191  //-----------------jFEXmetAlgo-----------------
192  m_jFEXmetAlgoTool->setup(m_jTowersIDs_Thin, hemisphere);
193  m_jFEXmetAlgoTool->buildBarrelmet();
194  }
195  else if(m_jfexid == 0 ) {
196 
197  int flipped_jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width] = {{0}};
198  int max_phi_it = FEXAlgoSpaceDefs::jFEX_algoSpace_height-1;
199  int max_eta_it = FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-1;
200  for(int mphi = 0; mphi <= max_phi_it; mphi++) {
201  for(int meta = 0; meta <= max_eta_it; meta++) {
202  flipped_jTowersIDs[mphi][meta]=m_jTowersIDs_Wide[mphi][max_eta_it-meta];
203  }
204  }
205  //-----------------jFEXsumETAlgo-----------------
206  m_jFEXsumETAlgoTool->setup(flipped_jTowersIDs);
207  m_jFEXsumETAlgoTool->buildFWDSumET();
208 
209  //-----------------jFEXmetAlgo-----------------
210  m_jFEXmetAlgoTool->setup(flipped_jTowersIDs, hemisphere);
211  m_jFEXmetAlgoTool->buildFWDmet();
212  }
213  else if(m_jfexid == 5) {
214 
215  //-----------------jFEXsumETAlgo-----------------
216  m_jFEXsumETAlgoTool->setup(m_jTowersIDs_Wide);
217  m_jFEXsumETAlgoTool->buildFWDSumET();
218 
219  //-----------------jFEXmetAlgo-----------------
220  m_jFEXmetAlgoTool->setup(m_jTowersIDs_Wide, hemisphere);
221  m_jFEXmetAlgoTool->buildFWDmet();
222  }
223 
224  jXE_tobword = m_IjFEXFormTOBsTool->formMetTOB(m_jFEXmetAlgoTool->GetMetXComponent(), m_jFEXmetAlgoTool->GetMetYComponent(),m_jFEXmetAlgoTool->getjXESat(),thr_jXE.resolutionMeV());
225  jXE_tob->initialize(m_id,m_jfexid,jXE_tobword,thr_jXE.resolutionMeV(),0);
226  m_Met_tobwords.push_back(std::move(jXE_tob));
227 
228  std::tuple<int,bool> jTElow;
229  std::tuple<int,bool> jTEhigh;
230 
231  // NOTE: Foward FPGA in the C-side is already flipped, however we still need to flip the jFEX module 1 and 2
232  if(m_jfexid == 1 || m_jfexid == 2){
233  jTElow = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
234  jTEhigh = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
235  }
236  else{
237  jTElow = m_jFEXsumETAlgoTool->getETlowerEta(bin_pos);
238  jTEhigh = m_jFEXsumETAlgoTool->getETupperEta(bin_pos);
239  }
240 
241  jTE_tobword = m_IjFEXFormTOBsTool->formSumETTOB(jTElow,jTEhigh,thr_jTE.resolutionMeV());
242  jTE_tob->initialize(m_id,m_jfexid,jTE_tobword,thr_jTE.resolutionMeV(),0);
243  m_sumET_tobwords.push_back(std::move(jTE_tob));
244  }
245 
246  //-----------jFEXSmallRJet & Large R Jet Algo-----------------
247  ATH_MSG_DEBUG("================ Central Algorithms ================");
248 
249  //Central region algorithms
250  if(m_jfexid > 0 && m_jfexid < 5) {
251  m_jFEXSmallRJetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
252  m_jFEXLargeRJetAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
253  m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
254 
255  for(int mphi = 8; mphi < FEXAlgoSpaceDefs::jFEX_algoSpace_height-8; mphi++) {
256  for(int meta = 8; meta < FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width-8; meta++) {
257 
258  //definition of arrays
259  int TT_seed_ID[3][3]= {{0}};
260  int TT_First_ETring[36]= {0};
261  int First_ETring_it = 0;
262 
263  int Jet_SearchWindow[7][7] = {{0}};
264  int Jet_SearchWindowDisplaced[7][7] = {{0}};
265  int largeRCluster_IDs[15][15]= {{0}};
266 
267  //filling up array to send them to the algorithms
268  for(int i = -7; i< 8; i++ ) {
269  for(int j = -7; j< 8; j++) {
270 
271  if(std::abs(i)<4 && std::abs(j)<4) {
272  Jet_SearchWindow[3 + i][3 + j] = m_jTowersIDs_Thin[mphi + i][meta +j];
273  Jet_SearchWindowDisplaced[3 + i][3 + j] = m_jTowersIDs_Thin[mphi+i+1][meta+j+1];
274  }
275 
276  uint deltaR = std::sqrt(std::pow(i,2)+std::pow(j,2));
277 
278  if(deltaR<2) {
279  TT_seed_ID[i+1][j+1] = m_jTowersIDs_Thin[mphi +i][meta +j]; // Seed 0.3x0.3 in phi-eta plane
280  }
281  else if(deltaR<4) {
282  TT_First_ETring[First_ETring_it]= m_jTowersIDs_Thin[mphi +i][meta +j]; // First energy ring, will be used as tau ISO
283  ++First_ETring_it;
284 
285  }
286  else if(deltaR<8) {
287  largeRCluster_IDs[7 +i][7 +j] = m_jTowersIDs_Thin[mphi + i][meta +j];
288  }
289  }
290  }
291 
292  // ******** jJ and jLJ algorithms ********
293  ATH_CHECK( m_jFEXSmallRJetAlgoTool->safetyTest());
294  ATH_CHECK( m_jFEXLargeRJetAlgoTool->safetyTest());
295  m_jFEXSmallRJetAlgoTool->setup(Jet_SearchWindow, Jet_SearchWindowDisplaced);
296  m_jFEXLargeRJetAlgoTool->setupCluster(largeRCluster_IDs);
297  m_jFEXSmallRJetAlgoTool->buildSeeds();
298 
299  bool is_Jet_LM = m_jFEXSmallRJetAlgoTool->isSeedLocalMaxima();
300 
301  if(is_Jet_LM) {
302 
303  //getting the energies
304  int SRj_Et = m_jFEXSmallRJetAlgoTool->getSmallClusterET();
305  int LRj_Et = m_jFEXLargeRJetAlgoTool->getLargeClusterET(SRj_Et,m_jFEXLargeRJetAlgoTool->getRingET());
306 
307  bool SRj_Sat = m_jFEXSmallRJetAlgoTool->getSRjetSat();
308  bool LRj_Sat = SRj_Sat || m_jFEXLargeRJetAlgoTool->getLRjetSat();
309 
310  int meta_LM = meta;
311  int mphi_LM = mphi;
312 
313  //Creating SR TOB
314  uint32_t SRJet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, mphi_LM, meta_LM, SRj_Et, SRj_Sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
315 
316  std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
317  jJ_tob->initialize(m_id,m_jfexid,SRJet_tobword,thr_jJ.resolutionMeV(),m_jTowersIDs_Thin[mphi_LM][meta_LM]);
318  if ( SRJet_tobword != 0 ){
319  m_SRJet_tobwords.push_back(std::move(jJ_tob));
320  }
321 
322  //Creating LR TOB
323  uint32_t LRJet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, mphi_LM, meta_LM, LRj_Et, LRj_Sat, thr_jLJ.resolutionMeV(), thr_jLJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
324 
325  std::unique_ptr<jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
326  jLJ_tob->initialize(m_id,m_jfexid,LRJet_tobword,thr_jLJ.resolutionMeV(),m_jTowersIDs_Thin[mphi_LM][meta_LM]);
327  if ( LRJet_tobword != 0 ) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
328 
329  }
330  // ******** jTau algorithm ********
331 
332  ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
333  m_jFEXtauAlgoTool->setup(TT_seed_ID);
334  bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima();
335 
336  // Save TOB is tau is a local maxima
337  if ( is_tau_LocalMax ) {
338 
339  //calculates the 1st energy ring
340  m_jFEXtauAlgoTool->setFirstEtRing(TT_First_ETring);
341 
342 
343  uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
344 
345  std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
346  jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),m_jTowersIDs_Thin[mphi][meta]);
347 
348  if ( jTau_tobword != 0 ){
349  m_tau_tobwords.push_back(std::move(jTau_tob));
350  }
351  }
352  }
353  }
354  } //end of if statement for checking if in central jfex modules
355 
356  //FCAL region algorithm
357  if(m_jfexid ==0 || m_jfexid ==5) {
358 
359  //**********Forward Jets***********************
360  ATH_CHECK(m_jFEXForwardJetsAlgoTool->safetyTest());
361  ATH_CHECK(m_jFEXForwardJetsAlgoTool->reset());
362  m_jFEXForwardJetsAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
363  m_jFEXForwardJetsAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid);
364 
365  m_FCALJets = m_jFEXForwardJetsAlgoTool->calculateJetETs();
366  for(std::unordered_map<int, jFEXForwardJetsInfo>::iterator it = m_FCALJets.begin(); it!=(m_FCALJets.end()); ++it) {
367 
368  uint32_t TTID = it->first;
369  jFEXForwardJetsInfo FCALJets = it->second;
370 
371  int iphi = FCALJets.getCentreLocalTTPhi();
372  int ieta = FCALJets.getCentreLocalTTEta();
373  m_SRJetET = FCALJets.getSeedET() + FCALJets.getFirstEnergyRingET();
374  m_LRJetET = m_SRJetET + FCALJets.getSecondEnergyRingET();
375 
376  bool SRJ_sat = FCALJets.getSRjetSat();
377 
378  uint32_t SRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formSRJetTOB(m_jfexid, iphi, ieta, m_SRJetET, SRJ_sat, thr_jJ.resolutionMeV(), thr_jJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]), jetCalibrationParameters);
379 
380  std::unique_ptr<jFEXTOB> jJ_tob = std::make_unique<jFEXTOB>();
381  jJ_tob->initialize(m_id,m_jfexid,SRFCAL_Jet_tobword,thr_jJ.resolutionMeV(),TTID);
382 
383  if ( SRFCAL_Jet_tobword != 0 ){
384  m_SRJet_tobwords.push_back(std::move(jJ_tob));
385  }
386 
387  if(std::fabs(FCALJets.getCentreTTEta())<2.51){
388  bool LRJ_sat = FCALJets.getLRjetSat();
389  uint32_t LRFCAL_Jet_tobword = m_IjFEXFormTOBsTool->formLRJetTOB(m_jfexid, iphi, ieta, m_LRJetET, LRJ_sat, thr_jLJ.resolutionMeV(),thr_jLJ.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
390 
391  std::unique_ptr<jFEXTOB> jLJ_tob = std::make_unique<jFEXTOB>();
392  jLJ_tob->initialize(m_id,m_jfexid,LRFCAL_Jet_tobword,thr_jLJ.resolutionMeV(),TTID);
393  if ( LRFCAL_Jet_tobword != 0 ) m_LRJet_tobwords.push_back(std::move(jLJ_tob));
394  }
395 
396  }
397  //********** Forward Electrons ***********************
398  ATH_CHECK(m_jFEXForwardElecAlgoTool->safetyTest());
399  ATH_CHECK(m_jFEXForwardElecAlgoTool->reset());
400  m_jFEXForwardElecAlgoTool->setFPGAEnergy(m_map_EM_Etvalues_FPGA,m_map_HAD_Etvalues_FPGA);
401  m_jFEXForwardElecAlgoTool->setup(m_jTowersIDs_Wide,m_jfexid,m_id);
402  m_ForwardElecs = m_jFEXForwardElecAlgoTool->calculateEDM();
403 
405  SG::ReadHandle<TrigConf::L1Menu> l1Menu (m_l1MenuKey/*, ctx*/);
406  const TrigConf::L1ThrExtraInfo_jEM & thr_jEM = l1Menu->thrExtraInfo().jEM();
407  const uint jFEXETResolution = thr_jEM.resolutionMeV();//200
408  std::string str_jfexname = m_jfex_string[m_jfexid];
409  uint minEtThreshold = thr_jEM.ptMinToTopoMeV(str_jfexname)/jFEXETResolution;
410  //uint Cval[9] = {1,2,3,20,30,40,20,30,40};//C values for iso, emfr1 and emfr2
411  std::vector<int> Ciso;
412  std::vector<int> Chad1;
413  std::vector<int> Chad2;
414 
415  for(std::unordered_map<uint, jFEXForwardElecInfo>::iterator itel = m_ForwardElecs.begin(); itel!=(m_ForwardElecs.end()); ++itel) {
416  uint32_t TTID = itel->first;
417  jFEXForwardElecInfo elCluster = itel->second;
418  uint meta = elCluster.getCoreIeta();//check whether this is the one used by the Trigger conf
419 
420  //retrieve jet rejection thresholds from trigger configuration
421  auto wp_loose = thr_jEM.isolation(TrigConf::Selection::WP::LOOSE, meta);
422  auto wp_medium = thr_jEM.isolation(TrigConf::Selection::WP::MEDIUM, meta);
423  auto wp_tight = thr_jEM.isolation(TrigConf::Selection::WP::TIGHT, meta);
424  Ciso.clear();
425  Chad1.clear();
426  Chad2.clear();
427  Ciso.push_back(wp_loose.iso_fw());
428  Ciso.push_back(wp_medium.iso_fw());
429  Ciso.push_back(wp_tight.iso_fw());
430  Chad1.push_back(wp_loose.frac_fw());
431  Chad1.push_back(wp_medium.frac_fw());
432  Chad1.push_back(wp_tight.frac_fw());
433  Chad2.push_back(wp_loose.frac2_fw());
434  Chad2.push_back(wp_medium.frac2_fw());
435  Chad2.push_back(wp_tight.frac2_fw());
436  int Cval[9] = {Ciso[0], Ciso[1], Ciso[2], Chad1[0], Chad1[1], Chad1[2], Chad2[0], Chad2[1], Chad2[2]};
437 
438  elCluster.setup(Cval,jFEXETResolution);
439  elCluster.calcFwdElEDM();
440 
441  uint etEM = elCluster.getEt();
442  uint32_t FwdEl_tobword = elCluster.getTobWord();
443 
444 
445  std::vector<uint32_t> FwdEltob_aux{FwdEl_tobword,TTID};
446  if ( FwdEl_tobword != 0 && etEM>minEtThreshold) m_FwdEl_tobwords.push_back(FwdEltob_aux);
447  }
448 
449  //******************************** TAU **********************************************
450  int jTowersIDs [FEXAlgoSpaceDefs::jFEX_algoSpace_height][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width] = {{0}};
451  int max_meta=17;
452 
453  if(m_jfexid ==0) {
454  for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
455  for(int j=28; j<(FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width-6); j++) { //lower values of j (j<28) are the Fcals not entering in the jFEX tau range
456  jTowersIDs[i][j-28+8]=m_jTowersIDs_Wide[i][j]; // second argument in m_jTowersIDs is to center the FPGA core area in te same region as the central FPGAs
457  }
458  }
459 
460  }
461  else if(m_jfexid ==5 ) {
462 
463  // Filling m_jTowersIDs with the m_jTowersIDs_Wide ID values up to 2.5 eta
464  for(int i=0; i<FEXAlgoSpaceDefs::jFEX_algoSpace_height; i++) {
465  for(int j=4; j<17; j++) { //higher values of j (j>16) are the Fcals not entering in the jFEX tau range
466  jTowersIDs[i][j]=m_jTowersIDs_Wide[i][j];
467  }
468  }
469  }
470  ATH_MSG_DEBUG("============================ jFEXtauAlgo ============================");
471  ATH_CHECK( m_jFEXtauAlgoTool->safetyTest());
472  m_jFEXtauAlgoTool->setFPGAEnergy(m_map_Etvalues_FPGA);
473  for(int mphi = 8; mphi < 24; mphi++) {
474  for(int meta = 8; meta < max_meta; meta++) {
475 
476  bool is_tau_LocalMax = m_jFEXtauAlgoTool->isSeedLocalMaxima_fwd(jTowersIDs[mphi][meta]);
477 
478  // Save TOB is tau is a local maxima
479  if ( is_tau_LocalMax ) {
480 
481  uint32_t jTau_tobword = m_IjFEXFormTOBsTool->formTauTOB(m_jfexid,mphi,meta,m_jFEXtauAlgoTool->getClusterEt(),m_jFEXtauAlgoTool->getFirstEtRing(),m_jFEXtauAlgoTool->getTauSat(),thr_jTAU.resolutionMeV(),thr_jTAU.ptMinToTopoMeV(m_jfex_string[m_jfexid]));
482 
483  std::unique_ptr<jFEXTOB> jTau_tob = std::make_unique<jFEXTOB>();
484  jTau_tob->initialize(m_id,m_jfexid,jTau_tobword,thr_jTAU.resolutionMeV(),jTowersIDs[mphi][meta]);
485  if ( jTau_tobword != 0 ){
486  m_tau_tobwords.push_back(std::move(jTau_tob));
487  }
488  }
489  }
490  }
491  } //end of if statement for checking if in central jfex modules
492  return StatusCode::SUCCESS;
493 } //end of the execute function
494 
495 void jFEXFPGA::SetTowersAndCells_SG(int tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_wide_algoSpace_width]){
496 
497  const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
498  const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
499 
500  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Wide[0][0]);
501 
502  ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
503 
504  for (int thisRow=rows-1; thisRow>=0; thisRow--){
505  for (int thisCol=0; thisCol<cols; thisCol++){
506  if(thisCol != cols-1){ ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " "); }
507  else { ATH_MSG_DEBUG("| " << m_jTowersIDs_Wide[thisRow][thisCol] << " |"); }
508  }
509  }
510 
511 }
512 
513 void jFEXFPGA::SetTowersAndCells_SG(int tmp_jTowersIDs_subset[][FEXAlgoSpaceDefs::jFEX_thin_algoSpace_width]) {
514 
515  const int rows = FEXAlgoSpaceDefs::jFEX_algoSpace_height;
516  const int cols = sizeof tmp_jTowersIDs_subset[0] / sizeof tmp_jTowersIDs_subset[0][0];
517 
518  std::copy(&tmp_jTowersIDs_subset[0][0], &tmp_jTowersIDs_subset[0][0]+(rows*cols),&m_jTowersIDs_Thin[0][0]);
519 
520  //this prints out the jTower IDs that each FPGA is responsible for
521  ATH_MSG_DEBUG("\n==== jFEXFPGA ========= FPGA (" << m_id << ") [on jFEX " << m_jfexid << "] IS RESPONSIBLE FOR jTOWERS :");
522 
523  for (int thisRow=rows-1; thisRow>=0; thisRow--) {
524  for (int thisCol=0; thisCol<cols; thisCol++) {
525  if(thisCol != cols-1) {
526  ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " ");
527  }
528  else {
529  ATH_MSG_DEBUG("| " << m_jTowersIDs_Thin[thisRow][thisCol] << " |");
530  }
531  }
532  }
533 
534 }
535 
536 std::vector <std::unique_ptr<jFEXTOB>> jFEXFPGA::getSmallRJetTOBs()
537 {
538 
539  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
540  tobsSort.clear();
541 
542  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
543  for(auto &j : m_SRJet_tobwords) {
544  tobsSort.push_back(std::move(j));
545  }
546  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jJ_etBit, 0x7ff));
547 
548  return tobsSort;
549 
550 }
551 
552 std::vector <std::unique_ptr<jFEXTOB>> jFEXFPGA::getLargeRJetTOBs()
553 {
554 
555 
556  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
557  tobsSort.clear();
558 
559  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
560  for(auto &j : m_LRJet_tobwords) {
561  tobsSort.push_back(std::move(j));
562  }
563  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jLJ_etBit, 0x1fff));
564 
565  return tobsSort;
566 
567 }
568 
569  std::vector <std::vector <uint32_t>> jFEXFPGA::getFwdElTOBs()
570  {
571  auto tobsSort = m_FwdEl_tobwords;
572 
573  ATH_MSG_DEBUG("number of Forward Elec tobs: " << tobsSort.size() << " in FPGA: " << m_id<< " before truncation");
574  //sort tobs by their et
575  std::sort (tobsSort.begin(), tobsSort.end(), etFwdElSort);
576 
577  return tobsSort;
578 
579  }
580 
581 
582 std::vector <std::unique_ptr<jFEXTOB>> jFEXFPGA::getTauTOBs() {
583 
584  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
585  tobsSort.clear();
586 
587  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
588  for(auto &j : m_tau_tobwords) {
589  tobsSort.push_back(std::move(j));
590  }
591  std::sort (tobsSort.begin(), tobsSort.end(), std::bind(TOBetSort<std::unique_ptr<jFEXTOB>>, std::placeholders::_1, std::placeholders::_2, FEXAlgoSpaceDefs::jTau_etBit, 0x7ff));
592 
593  return tobsSort;
594 }
595 
596 std::vector<std::unique_ptr<jFEXTOB>> jFEXFPGA::getSumEtTOBs() {
597 
598  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
599  tobsSort.clear();
600 
601  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
602  for(auto &j : m_sumET_tobwords) {
603  tobsSort.push_back(std::move(j));
604  }
605 
606  return tobsSort;
607 
608 }
609 
610 
611 
612 std::vector<std::unique_ptr<jFEXTOB>> jFEXFPGA::getMetTOBs() {
613 
614  std::vector<std::unique_ptr<jFEXTOB>> tobsSort;
615  tobsSort.clear();
616 
617  // We need the copy since we cannot move a member of the class, since it will not be part of it anymore
618  for(auto &j : m_Met_tobwords) {
619  tobsSort.push_back(std::move(j));
620  }
621 
622  return tobsSort;
623 
624 }
625 
626 
627 //Returns the Electromagnetic energy for Jet Algos (NOT MET/SumET)
628 int jFEXFPGA::getTTowerET_EM(unsigned int TTID) {
629 
630  if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
631  return m_map_EM_Etvalues_FPGA[TTID][0];
632  }
633 
634  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_EM, TTower ID not found in map: " << TTID );
635  return -99999;
636 
637 }
638 
639 
640 //Returns the Hadronic energy for Jet Algos (NOT MET/SumET)
641 int jFEXFPGA::getTTowerET_HAD(unsigned int TTID) {
642 
643  if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
644  return m_map_HAD_Etvalues_FPGA[TTID][0];
645  }
646 
647  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_HAD, TTower ID not found in map: " << TTID );
648  return -99999;
649 
650 }
651 
652 
653 //Returns the Total TT energy for Jet Algos (NOT MET/SumET)
654 int jFEXFPGA::getTTowerET(unsigned int TTID) {
655 
656  return getTTowerET_EM(TTID)+getTTowerET_HAD(TTID);
657 
658 }
659 
660 
661 //Returns the Total TT energy for MET/SumÉT Algos
662 int jFEXFPGA::getTTowerET_forMET(unsigned int TTID) {
663 
664  int tmp_EM = 0;
665  if(m_map_EM_Etvalues_FPGA.find(TTID) != m_map_EM_Etvalues_FPGA.end()){
666  tmp_EM = m_map_EM_Etvalues_FPGA[TTID][1];
667  }
668  else{
669  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (EM energy), TTower ID not found in map: " << TTID );
670  tmp_EM = -99999;
671  }
672 
673 
674  int tmp_HAD = 0;
675  if(m_map_HAD_Etvalues_FPGA.find(TTID) != m_map_HAD_Etvalues_FPGA.end()){
676  tmp_HAD = m_map_HAD_Etvalues_FPGA[TTID][1];
677  }
678  else{
679  ATH_MSG_DEBUG("In jFEXFPGA::getTTowerET_forMET (HAD energy), TTower ID not found in map: " << TTID );
680  tmp_HAD = -99999;
681  }
682 
683 
684  return tmp_EM + tmp_HAD;
685 
686 }
687 
688 
689 //Returns de ET of a given TT ID for Algorithm
690 int jFEXFPGA::getTTowerET_SG(unsigned int TTID) {
691 
692  if(TTID == 0){
693  return -999;
694  }
695  SG::ReadHandle<jTowerContainer> jTowerContainer(m_jTowerContainerKey);
696  const LVL1::jTower * tmpTower = jTowerContainer->findTower(TTID);
697  return tmpTower->getTotalET();
698 }
699 
700 
701 
702 
703 
704 
705 } // end of namespace bracket
xAOD::iterator
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Definition: JetConstituentVector.cxx:68
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Calculate variables for top word.
Definition: jFEXForwardElecInfo.cxx:198
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Form a tob word out of the potential candidate MET tob.
Definition: jFEXFPGA.cxx:612
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Definition: jFEXFPGA.h:118
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Definition: jFEXFPGA.cxx:49
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Definition: FEXAlgoSpaceDefs.h:119
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eFexTowerBuilder creates xAOD::eFexTowerContainer from supercells (LATOME) and triggerTowers (TREX) i...
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Definition: AthMsgStreamMacros.h:29
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Definition: test_pyathena.py:15
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Helper class for offline supercell identifiers.
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Get ET sum of all cells in the jTower in MeV.
Definition: jTower.cxx:201
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Definition: AthCheckMacros.h:40
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Form a tob word out of the potential candidate SmallRJet tob.
Definition: jFEXFPGA.cxx:536
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constexpr static int jTau_etBit
Definition: FEXAlgoSpaceDefs.h:100
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ToolHandle< IjFEXFormTOBs > m_IjFEXFormTOBsTool
Definition: jFEXFPGA.h:147
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Definition: bin/beamspotnt.py:1112
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Definition: jFEXOutputCollection.h:23
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If this object is used as a property, then this should be called during the initialize phase.
Definition: AthToolSupport/AsgDataHandles/Root/VarHandleKey.cxx:103
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Definition: jFEXFPGA.cxx:495
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Definition: jTowerContainer.h:33
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Definition: jFEXFPGA.h:116
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Definition: HLTChainList.h:35
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Dummy event store, for regression tests.
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Definition: jFEXFPGA.h:111
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Definition: jFEXOutputCollection.cxx:136
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Definition: Control/AthContainers/Root/debug.cxx:194
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sorted Electron tobs
Definition: jFEXFPGA.cxx:569
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Definition: jFEXForwardJetsInfo.h:39
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Definition: L1ThrExtraInfo.h:296
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Definition: L1ThresholdBase.h:101
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Definition: jFEXForwardElecInfo.cxx:170
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Definition: jFEXFPGA.h:145
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Definition: jFEXFPGA.h:143
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Definition: jFEXFPGA.cxx:91
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Form a tob word out of the potential candidate SumET tob.
Definition: jFEXFPGA.cxx:596
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Definition: jFEXFPGA.h:126
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Definition: jFEXForwardJetsInfo.cxx:116
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Definition: jFEXOutputCollection.cxx:97
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Definition: jFEXFPGA.h:115
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Destructor.
Definition: jFEXFPGA.cxx:54
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Definition: jFEXForwardJetsInfo.cxx:79
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The jTower class is an interface object for jFEX trigger algorithms The purposes are twofold:
Definition: jTower.h:40
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unsigned int ptMinToTopoMeV(const std::string &module) const
Definition: L1ThrExtraInfo.h:222
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Definition: jFEXForwardElecInfo.h:28
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Definition: L1ThrExtraInfo.h:424
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Definition: calibdata.py:27
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Handle class for reading from StoreGate.
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Definition: AthAlgTool.h:26
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const L1ThrExtraInfo_jTE & jTE() const
Definition: L1ThrExtraInfo.cxx:173
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Definition: L1ThrExtraInfo.h:189
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int m_SRJetET
Definition: jFEXFPGA.h:132
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Definition: makeComparison.py:36
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Definition: jFEXFPGA.cxx:690
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Definition: jFEXForwardElecInfo.cxx:182
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Definition: jFEXFPGA.h:140
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Definition: L1ThrExtraInfo.h:390
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ToolHandle< IjFEXPileupAndNoise > m_jFEXPileupAndNoiseTool
Definition: jFEXFPGA.h:146
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Definition: TElectronEfficiencyCorrectionTool.cxx:37
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Definition: jFEXFPGA.h:121
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