20 declareInterface<IjFEXSim>(
this);
29 return StatusCode::SUCCESS;
36 return StatusCode::SUCCESS;
49 for (
int j=0; j<
cols; j++){
58 for (
int j=0; j<
cols; j++){
99 int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
109 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
111 for (
int myrow = 0; myrow<2; myrow++){
112 for (
int mycol = 0; mycol<24; mycol++){
113 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[14+myrow][mycol];
116 for (
int myrow = 2; myrow<6; myrow++){
117 for (
int mycol = 0; mycol<24; mycol++){
118 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol];
121 for (
int myrow = 6; myrow<8; myrow++){
122 for (
int mycol = 0; mycol<24; mycol++){
123 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol];
126 for (
int myrow = 0; myrow<4; myrow++){
127 for (
int mycol = 24; mycol<28; mycol++){
128 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[28+myrow][mycol];
131 for (
int myrow = 4; myrow<12; myrow++){
132 for (
int mycol = 24; mycol<28; mycol++){
133 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol];
136 for (
int myrow = 12; myrow<16; myrow++){
137 for (
int mycol = 24; mycol<28; mycol++){
138 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol];
141 for (
int myrow = 0; myrow<8; myrow++){
142 for (
int mycol = 28; mycol<ncols; mycol++){
143 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[56+myrow][mycol];
146 for (
int myrow = 8; myrow<32; myrow++){
147 for (
int mycol = 28; mycol<ncols; mycol++){
148 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-8][mycol];
164 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
166 for (
int myrow = 0; myrow<2; myrow++){
167 for (
int mycol = 0; mycol<24; mycol++){
168 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[2+myrow][mycol];
171 for (
int myrow = 2; myrow<6; myrow++){
172 for (
int mycol = 0; mycol<24; mycol++){
173 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol];
176 for (
int myrow = 6; myrow<8; myrow++){
177 for (
int mycol = 0; mycol<24; mycol++){
178 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol];
181 for (
int myrow = 0; myrow<4; myrow++){
182 for (
int mycol = 24; mycol<28; mycol++){
183 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[4+myrow][mycol];
186 for (
int myrow = 4; myrow<12; myrow++){
187 for (
int mycol = 24; mycol<28; mycol++){
188 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol];
191 for (
int myrow = 12; myrow<16; myrow++){
192 for (
int mycol = 24; mycol<28; mycol++){
193 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol];
196 for (
int myrow = 0; myrow<8; myrow++){
197 for (
int mycol = 28; mycol<ncols; mycol++){
198 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[8+myrow][mycol];
201 for (
int myrow = 8; myrow<32; myrow++){
202 for (
int mycol = 28; mycol<ncols; mycol++){
203 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+8][mycol];
218 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
220 for (
int myrow = 0; myrow<2; myrow++){
221 for (
int mycol = 0; mycol<24; mycol++){
222 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[6+myrow][mycol];
225 for (
int myrow = 2; myrow<6; myrow++){
226 for (
int mycol = 0; mycol<24; mycol++){
227 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol];
230 for (
int myrow = 6; myrow<8; myrow++){
231 for (
int mycol = 0; mycol<24; mycol++){
232 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol];
235 for (
int myrow = 0; myrow<4; myrow++){
236 for (
int mycol = 24; mycol<28; mycol++){
237 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[12+myrow][mycol];
240 for (
int myrow = 4; myrow<12; myrow++){
241 for (
int mycol = 24; mycol<28; mycol++){
242 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol];
245 for (
int myrow = 12; myrow<16; myrow++){
246 for (
int mycol = 24; mycol<28; mycol++){
247 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol];
250 for (
int myrow = 0; myrow<8; myrow++){
251 for (
int mycol = 28; mycol<ncols; mycol++){
252 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[24+myrow][mycol];
255 for (
int myrow = 8; myrow<32; myrow++){
256 for (
int mycol = 28; mycol<ncols; mycol++){
257 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+24][mycol];
275 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
277 for (
int myrow = 0; myrow<2; myrow++){
278 for (
int mycol = 0; mycol<24; mycol++){
279 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[10+myrow][mycol];
282 for (
int myrow = 2; myrow<6; myrow++){
283 for (
int mycol = 0; mycol<24; mycol++){
284 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+10][mycol];
287 for (
int myrow = 6; myrow<8; myrow++){
288 for (
int mycol = 0; mycol<24; mycol++){
289 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-6][mycol];
292 for (
int myrow = 0; myrow<4; myrow++){
293 for (
int mycol = 24; mycol<28; mycol++){
294 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[20+myrow][mycol];
297 for (
int myrow = 4; myrow<12; myrow++){
298 for (
int mycol = 24; mycol<28; mycol++){
299 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+20][mycol];
302 for (
int myrow = 12; myrow<16; myrow++){
303 for (
int mycol = 24; mycol<28; mycol++){
304 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-12][mycol];
307 for (
int myrow = 0; myrow<24; myrow++){
308 for (
int mycol = 28; mycol<ncols; mycol++){
309 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[40+myrow][mycol];
312 for (
int myrow = 24; myrow<32; myrow++){
313 for (
int mycol = 28; mycol<ncols; mycol++){
314 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-24][mycol];
328 return StatusCode::SUCCESS;
347 int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
357 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
359 for (
int myrow = 0; myrow<2; myrow++){
360 for (
int mycol = ncols-24; mycol<ncols; mycol++){
361 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[14+myrow][mycol];
364 for (
int myrow = 2; myrow<6; myrow++){
365 for (
int mycol = ncols-24; mycol<ncols; mycol++){
366 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol];
369 for (
int myrow = 6; myrow<8; myrow++){
370 for (
int mycol = ncols-24; mycol<ncols; mycol++){
371 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol];
374 for (
int myrow = 0; myrow<4; myrow++){
375 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
376 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[28+myrow][mycol];
379 for (
int myrow = 4; myrow<12; myrow++){
380 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
381 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol];
384 for (
int myrow = 12; myrow<16; myrow++){
385 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
386 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol];
389 for (
int myrow = 0; myrow<8; myrow++){
390 for (
int mycol = 0; mycol<ncols-28; mycol++){
391 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[56+myrow][mycol];
394 for (
int myrow = 8; myrow<32; myrow++){
395 for (
int mycol = 0; mycol<ncols-28; mycol++){
396 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-8][mycol];
412 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
414 for (
int myrow = 0; myrow<2; myrow++){
415 for (
int mycol = ncols-24; mycol<ncols; mycol++){
416 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[2+myrow][mycol];
419 for (
int myrow = 2; myrow<6; myrow++){
420 for (
int mycol = ncols-24; mycol<ncols; mycol++){
421 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol];
424 for (
int myrow = 6; myrow<8; myrow++){
425 for (
int mycol = ncols-24; mycol<ncols; mycol++){
426 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol];
429 for (
int myrow = 0; myrow<4; myrow++){
430 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
431 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[4+myrow][mycol];
434 for (
int myrow = 4; myrow<12; myrow++){
435 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
436 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol];
439 for (
int myrow = 12; myrow<16; myrow++){
440 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
441 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol];
444 for (
int myrow = 0; myrow<8; myrow++){
445 for (
int mycol = 0; mycol<ncols-28; mycol++){
446 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[8+myrow][mycol];
449 for (
int myrow = 8; myrow<32; myrow++){
450 for (
int mycol = 0; mycol<ncols-28; mycol++){
451 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+8][mycol];
465 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
467 for (
int myrow = 0; myrow<2; myrow++){
468 for (
int mycol = ncols-24; mycol<ncols; mycol++){
469 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[6+myrow][mycol];
472 for (
int myrow = 2; myrow<6; myrow++){
473 for (
int mycol = ncols-24; mycol<ncols; mycol++){
474 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol];
477 for (
int myrow = 6; myrow<8; myrow++){
478 for (
int mycol = ncols-24; mycol<ncols; mycol++){
479 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol];
482 for (
int myrow = 0; myrow<4; myrow++){
483 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
484 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[12+myrow][mycol];
487 for (
int myrow = 4; myrow<12; myrow++){
488 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
489 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol];
492 for (
int myrow = 12; myrow<16; myrow++){
493 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
494 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol];
497 for (
int myrow = 0; myrow<8; myrow++){
498 for (
int mycol = 0; mycol<ncols-28; mycol++){
499 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[24+myrow][mycol];
502 for (
int myrow = 8; myrow<32; myrow++){
503 for (
int mycol = 0; mycol<ncols-28; mycol++){
504 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+24][mycol];
521 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
523 for (
int myrow = 0; myrow<2; myrow++){
524 for (
int mycol = ncols-24; mycol<ncols; mycol++){
525 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[10+myrow][mycol];
528 for (
int myrow = 2; myrow<6; myrow++){
529 for (
int mycol = ncols-24; mycol<ncols; mycol++){
530 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+10][mycol];
533 for (
int myrow = 6; myrow<8; myrow++){
534 for (
int mycol = ncols-24; mycol<ncols; mycol++){
535 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-6][mycol];
538 for (
int myrow = 0; myrow<4; myrow++){
539 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
540 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[20+myrow][mycol];
543 for (
int myrow = 4; myrow<12; myrow++){
544 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
545 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+20][mycol];
548 for (
int myrow = 12; myrow<16; myrow++){
549 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
550 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-12][mycol];
553 for (
int myrow = 0; myrow<24; myrow++){
554 for (
int mycol = 0; mycol<ncols-28; mycol++){
555 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[40+myrow][mycol];
558 for (
int myrow = 24; myrow<32; myrow++){
559 for (
int mycol = 0; mycol<ncols-28; mycol++){
560 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-24][mycol];
574 return StatusCode::SUCCESS;
592 int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
596 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
598 for (
int myrow = 0; myrow<8; myrow++){
599 for (
int mycol = 0; mycol<ncols; mycol++){
600 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[56+myrow][mycol];
603 for (
int myrow = 8; myrow<32; myrow++){
604 for (
int mycol = 0; mycol<ncols; mycol++){
605 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-8][mycol];
621 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
623 for (
int myrow = 0; myrow<32; myrow++){
624 for (
int mycol = 0; mycol<ncols; mycol++){
625 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[8+myrow][mycol];
640 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
642 for (
int myrow = 0; myrow<32; myrow++){
643 for (
int mycol = 0; mycol<ncols; mycol++){
644 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[24+myrow][mycol];
661 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
663 for (
int myrow = 0; myrow<24; myrow++){
664 for (
int mycol = 0; mycol<ncols; mycol++){
665 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[40+myrow][mycol];
668 for (
int myrow = 24; myrow<32; myrow++){
669 for (
int mycol = 0; mycol<ncols; mycol++){
670 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-24][mycol];
684 return StatusCode::SUCCESS;
696 int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
699 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
700 for (
int myrow = 0; myrow<nrows; myrow++){
701 for (
int mycol = 0; mycol<ncols; mycol++){
702 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
709 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
710 for (
int myrow = nrows; myrow<nrows*2; myrow++){
711 for (
int mycol = 0; mycol<ncols; mycol++){
712 tmp_jTowersIDs_subset_FPGA[myrow-nrows][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
720 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
721 for (
int myrow = nrows*2; myrow<nrows*3; myrow++){
722 for (
int mycol = 0; mycol<ncols; mycol++){
723 tmp_jTowersIDs_subset_FPGA[myrow-(nrows*2)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
730 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
731 for (
int myrow = nrows*3; myrow<nrows*4; myrow++){
732 for (
int mycol = 0; mycol<ncols; mycol++){
733 tmp_jTowersIDs_subset_FPGA[myrow-(nrows*3)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
743 std::vector< std::vector<std::unique_ptr<jFEXTOB>>> sjTOBs;
759 std::vector< std::vector<std::unique_ptr<jFEXTOB>> > ljTOBs;
773 std::vector< std::vector<std::unique_ptr<jFEXTOB>> > tauTOBs;
793 std::vector<std::unique_ptr<jFEXTOB>> sumetTOBs;
807 std::vector<std::unique_ptr<jFEXTOB>> metTOBs;
829 int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
832 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
833 for (
int myrow = 0; myrow<nrows; myrow++){
834 for (
int mycol = 0; mycol<ncols; mycol++){
835 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
842 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
843 for (
int myrow = nrows; myrow<nrows*2; myrow++){
844 for (
int mycol = 0; mycol<ncols; mycol++){
845 tmp_jTowersIDs_subset_FPGA[myrow-nrows][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
853 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
854 for (
int myrow = nrows*2; myrow<nrows*3; myrow++){
855 for (
int mycol = 0; mycol<ncols; mycol++){
856 tmp_jTowersIDs_subset_FPGA[myrow-(nrows*2)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
863 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
864 for (
int myrow = nrows*3; myrow<nrows*4; myrow++){
865 for (
int mycol = 0; mycol<ncols; mycol++){
866 tmp_jTowersIDs_subset_FPGA[myrow-(nrows*3)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];