23 #include "GaudiKernel/ServiceHandle.h"
30 declareInterface<IjFEXSim>(
this);
39 return StatusCode::SUCCESS;
46 return StatusCode::SUCCESS;
59 for (
int j=0; j<
cols; j++){
68 for (
int j=0; j<
cols; j++){
109 int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
119 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
121 for (
int myrow = 0; myrow<2; myrow++){
122 for (
int mycol = 0; mycol<24; mycol++){
123 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[14+myrow][mycol];
126 for (
int myrow = 2; myrow<6; myrow++){
127 for (
int mycol = 0; mycol<24; mycol++){
128 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol];
131 for (
int myrow = 6; myrow<8; myrow++){
132 for (
int mycol = 0; mycol<24; mycol++){
133 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol];
136 for (
int myrow = 0; myrow<4; myrow++){
137 for (
int mycol = 24; mycol<28; mycol++){
138 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[28+myrow][mycol];
141 for (
int myrow = 4; myrow<12; myrow++){
142 for (
int mycol = 24; mycol<28; mycol++){
143 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol];
146 for (
int myrow = 12; myrow<16; myrow++){
147 for (
int mycol = 24; mycol<28; mycol++){
148 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol];
151 for (
int myrow = 0; myrow<8; myrow++){
152 for (
int mycol = 28; mycol<ncols; mycol++){
153 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[56+myrow][mycol];
156 for (
int myrow = 8; myrow<32; myrow++){
157 for (
int mycol = 28; mycol<ncols; mycol++){
158 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-8][mycol];
174 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
176 for (
int myrow = 0; myrow<2; myrow++){
177 for (
int mycol = 0; mycol<24; mycol++){
178 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[2+myrow][mycol];
181 for (
int myrow = 2; myrow<6; myrow++){
182 for (
int mycol = 0; mycol<24; mycol++){
183 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol];
186 for (
int myrow = 6; myrow<8; myrow++){
187 for (
int mycol = 0; mycol<24; mycol++){
188 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol];
191 for (
int myrow = 0; myrow<4; myrow++){
192 for (
int mycol = 24; mycol<28; mycol++){
193 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[4+myrow][mycol];
196 for (
int myrow = 4; myrow<12; myrow++){
197 for (
int mycol = 24; mycol<28; mycol++){
198 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol];
201 for (
int myrow = 12; myrow<16; myrow++){
202 for (
int mycol = 24; mycol<28; mycol++){
203 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol];
206 for (
int myrow = 0; myrow<8; myrow++){
207 for (
int mycol = 28; mycol<ncols; mycol++){
208 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[8+myrow][mycol];
211 for (
int myrow = 8; myrow<32; myrow++){
212 for (
int mycol = 28; mycol<ncols; mycol++){
213 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+8][mycol];
228 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
230 for (
int myrow = 0; myrow<2; myrow++){
231 for (
int mycol = 0; mycol<24; mycol++){
232 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[6+myrow][mycol];
235 for (
int myrow = 2; myrow<6; myrow++){
236 for (
int mycol = 0; mycol<24; mycol++){
237 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol];
240 for (
int myrow = 6; myrow<8; myrow++){
241 for (
int mycol = 0; mycol<24; mycol++){
242 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol];
245 for (
int myrow = 0; myrow<4; myrow++){
246 for (
int mycol = 24; mycol<28; mycol++){
247 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[12+myrow][mycol];
250 for (
int myrow = 4; myrow<12; myrow++){
251 for (
int mycol = 24; mycol<28; mycol++){
252 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol];
255 for (
int myrow = 12; myrow<16; myrow++){
256 for (
int mycol = 24; mycol<28; mycol++){
257 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol];
260 for (
int myrow = 0; myrow<8; myrow++){
261 for (
int mycol = 28; mycol<ncols; mycol++){
262 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[24+myrow][mycol];
265 for (
int myrow = 8; myrow<32; myrow++){
266 for (
int mycol = 28; mycol<ncols; mycol++){
267 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+24][mycol];
285 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
287 for (
int myrow = 0; myrow<2; myrow++){
288 for (
int mycol = 0; mycol<24; mycol++){
289 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[10+myrow][mycol];
292 for (
int myrow = 2; myrow<6; myrow++){
293 for (
int mycol = 0; mycol<24; mycol++){
294 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+10][mycol];
297 for (
int myrow = 6; myrow<8; myrow++){
298 for (
int mycol = 0; mycol<24; mycol++){
299 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-6][mycol];
302 for (
int myrow = 0; myrow<4; myrow++){
303 for (
int mycol = 24; mycol<28; mycol++){
304 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[20+myrow][mycol];
307 for (
int myrow = 4; myrow<12; myrow++){
308 for (
int mycol = 24; mycol<28; mycol++){
309 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+20][mycol];
312 for (
int myrow = 12; myrow<16; myrow++){
313 for (
int mycol = 24; mycol<28; mycol++){
314 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-12][mycol];
317 for (
int myrow = 0; myrow<24; myrow++){
318 for (
int mycol = 28; mycol<ncols; mycol++){
319 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[40+myrow][mycol];
322 for (
int myrow = 24; myrow<32; myrow++){
323 for (
int mycol = 28; mycol<ncols; mycol++){
324 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-24][mycol];
338 return StatusCode::SUCCESS;
357 int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
367 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
369 for (
int myrow = 0; myrow<2; myrow++){
370 for (
int mycol = ncols-24; mycol<ncols; mycol++){
371 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[14+myrow][mycol];
374 for (
int myrow = 2; myrow<6; myrow++){
375 for (
int mycol = ncols-24; mycol<ncols; mycol++){
376 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol];
379 for (
int myrow = 6; myrow<8; myrow++){
380 for (
int mycol = ncols-24; mycol<ncols; mycol++){
381 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-2][mycol];
384 for (
int myrow = 0; myrow<4; myrow++){
385 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
386 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[28+myrow][mycol];
389 for (
int myrow = 4; myrow<12; myrow++){
390 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
391 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol];
394 for (
int myrow = 12; myrow<16; myrow++){
395 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
396 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-4][mycol];
399 for (
int myrow = 0; myrow<8; myrow++){
400 for (
int mycol = 0; mycol<ncols-28; mycol++){
401 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[56+myrow][mycol];
404 for (
int myrow = 8; myrow<32; myrow++){
405 for (
int mycol = 0; mycol<ncols-28; mycol++){
406 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-8][mycol];
422 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
424 for (
int myrow = 0; myrow<2; myrow++){
425 for (
int mycol = ncols-24; mycol<ncols; mycol++){
426 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[2+myrow][mycol];
429 for (
int myrow = 2; myrow<6; myrow++){
430 for (
int mycol = ncols-24; mycol<ncols; mycol++){
431 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol];
434 for (
int myrow = 6; myrow<8; myrow++){
435 for (
int mycol = ncols-24; mycol<ncols; mycol++){
436 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+2][mycol];
439 for (
int myrow = 0; myrow<4; myrow++){
440 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
441 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[4+myrow][mycol];
444 for (
int myrow = 4; myrow<12; myrow++){
445 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
446 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol];
449 for (
int myrow = 12; myrow<16; myrow++){
450 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
451 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+4][mycol];
454 for (
int myrow = 0; myrow<8; myrow++){
455 for (
int mycol = 0; mycol<ncols-28; mycol++){
456 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[8+myrow][mycol];
459 for (
int myrow = 8; myrow<32; myrow++){
460 for (
int mycol = 0; mycol<ncols-28; mycol++){
461 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+8][mycol];
475 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
477 for (
int myrow = 0; myrow<2; myrow++){
478 for (
int mycol = ncols-24; mycol<ncols; mycol++){
479 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[6+myrow][mycol];
482 for (
int myrow = 2; myrow<6; myrow++){
483 for (
int mycol = ncols-24; mycol<ncols; mycol++){
484 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol];
487 for (
int myrow = 6; myrow<8; myrow++){
488 for (
int mycol = ncols-24; mycol<ncols; mycol++){
489 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+6][mycol];
492 for (
int myrow = 0; myrow<4; myrow++){
493 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
494 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[12+myrow][mycol];
497 for (
int myrow = 4; myrow<12; myrow++){
498 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
499 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol];
502 for (
int myrow = 12; myrow<16; myrow++){
503 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
504 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+12][mycol];
507 for (
int myrow = 0; myrow<8; myrow++){
508 for (
int mycol = 0; mycol<ncols-28; mycol++){
509 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[24+myrow][mycol];
512 for (
int myrow = 8; myrow<32; myrow++){
513 for (
int mycol = 0; mycol<ncols-28; mycol++){
514 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+24][mycol];
531 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
533 for (
int myrow = 0; myrow<2; myrow++){
534 for (
int mycol = ncols-24; mycol<ncols; mycol++){
535 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[10+myrow][mycol];
538 for (
int myrow = 2; myrow<6; myrow++){
539 for (
int mycol = ncols-24; mycol<ncols; mycol++){
540 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+10][mycol];
543 for (
int myrow = 6; myrow<8; myrow++){
544 for (
int mycol = ncols-24; mycol<ncols; mycol++){
545 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-6][mycol];
548 for (
int myrow = 0; myrow<4; myrow++){
549 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
550 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[20+myrow][mycol];
553 for (
int myrow = 4; myrow<12; myrow++){
554 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
555 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow+20][mycol];
558 for (
int myrow = 12; myrow<16; myrow++){
559 for (
int mycol = ncols-28; mycol<ncols-24; mycol++){
560 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-12][mycol];
563 for (
int myrow = 0; myrow<24; myrow++){
564 for (
int mycol = 0; mycol<ncols-28; mycol++){
565 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[40+myrow][mycol];
568 for (
int myrow = 24; myrow<32; myrow++){
569 for (
int mycol = 0; mycol<ncols-28; mycol++){
570 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-24][mycol];
584 return StatusCode::SUCCESS;
602 int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
606 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
608 for (
int myrow = 0; myrow<8; myrow++){
609 for (
int mycol = 0; mycol<ncols; mycol++){
610 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[56+myrow][mycol];
613 for (
int myrow = 8; myrow<32; myrow++){
614 for (
int mycol = 0; mycol<ncols; mycol++){
615 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-8][mycol];
631 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
633 for (
int myrow = 0; myrow<32; myrow++){
634 for (
int mycol = 0; mycol<ncols; mycol++){
635 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[8+myrow][mycol];
650 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
652 for (
int myrow = 0; myrow<32; myrow++){
653 for (
int mycol = 0; mycol<ncols; mycol++){
654 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[24+myrow][mycol];
671 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
673 for (
int myrow = 0; myrow<24; myrow++){
674 for (
int mycol = 0; mycol<ncols; mycol++){
675 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[40+myrow][mycol];
678 for (
int myrow = 24; myrow<32; myrow++){
679 for (
int mycol = 0; mycol<ncols; mycol++){
680 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow-24][mycol];
694 return StatusCode::SUCCESS;
706 int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
709 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
710 for (
int myrow = 0; myrow<nrows; myrow++){
711 for (
int mycol = 0; mycol<ncols; mycol++){
712 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
719 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
720 for (
int myrow = nrows; myrow<nrows*2; myrow++){
721 for (
int mycol = 0; mycol<ncols; mycol++){
722 tmp_jTowersIDs_subset_FPGA[myrow-nrows][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
730 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
731 for (
int myrow = nrows*2; myrow<nrows*3; myrow++){
732 for (
int mycol = 0; mycol<ncols; mycol++){
733 tmp_jTowersIDs_subset_FPGA[myrow-(nrows*2)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
740 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
741 for (
int myrow = nrows*3; myrow<nrows*4; myrow++){
742 for (
int mycol = 0; mycol<ncols; mycol++){
743 tmp_jTowersIDs_subset_FPGA[myrow-(nrows*3)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
753 std::vector< std::vector<std::unique_ptr<jFEXTOB>>> sjTOBs;
769 std::vector< std::vector<std::unique_ptr<jFEXTOB>> > ljTOBs;
784 std::vector< std::vector<std::unique_ptr<jFEXTOB>> > tauTOBs;
806 std::vector<std::unique_ptr<jFEXTOB>> sumetTOBs;
821 std::vector<std::unique_ptr<jFEXTOB>> metTOBs;
844 int tmp_jTowersIDs_subset_FPGA[nrows][ncols];
847 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
848 for (
int myrow = 0; myrow<nrows; myrow++){
849 for (
int mycol = 0; mycol<ncols; mycol++){
850 tmp_jTowersIDs_subset_FPGA[myrow][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
857 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
858 for (
int myrow = nrows; myrow<nrows*2; myrow++){
859 for (
int mycol = 0; mycol<ncols; mycol++){
860 tmp_jTowersIDs_subset_FPGA[myrow-nrows][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
868 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
869 for (
int myrow = nrows*2; myrow<nrows*3; myrow++){
870 for (
int mycol = 0; mycol<ncols; mycol++){
871 tmp_jTowersIDs_subset_FPGA[myrow-(nrows*2)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];
878 memset(tmp_jTowersIDs_subset_FPGA, 0,
sizeof tmp_jTowersIDs_subset_FPGA);
879 for (
int myrow = nrows*3; myrow<nrows*4; myrow++){
880 for (
int mycol = 0; mycol<ncols; mycol++){
881 tmp_jTowersIDs_subset_FPGA[myrow-(nrows*3)][mycol] = tmp_jTowersIDs_subset[myrow][mycol];