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LVL1::eFakeTower Class Reference

Load Et of the test vector. More...

#include <eFakeTower.h>

Inheritance diagram for LVL1::eFakeTower:
Collaboration diagram for LVL1::eFakeTower:

Public Member Functions

 eFakeTower (const std::string &type, const std::string &name, const IInterface *parent)
 Constructor.
virtual StatusCode init (const std::string &)
 initiate with the path to the test vector directory
 ~eFakeTower ()
 Destructor.
virtual int getET (int FPGAid, int eta, int phi, int layer, int cell) const
 obtain the Et of a tower slot
virtual StatusCode loadnext ()
 Load the test vector of the next event.
virtual StatusCode execute ()
 replace the Tower Et with the ones stored in the test vector.
virtual StatusCode seteTowers (eTowerContainer *)
 Define the eTowerContainer object for which the Et will be replaced.
ServiceHandle< StoreGateSvc > & evtStore ()
 The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.
const ServiceHandle< StoreGateSvc > & detStore () const
 The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.
virtual StatusCode sysInitialize () override
 Perform system initialization for an algorithm.
virtual StatusCode sysStart () override
 Handle START transition.
virtual std::vector< Gaudi::DataHandle * > inputHandles () const override
 Return this algorithm's input handles.
virtual std::vector< Gaudi::DataHandle * > outputHandles () const override
 Return this algorithm's output handles.
Gaudi::Details::PropertyBase & declareProperty (Gaudi::Property< T, V, H > &t)
void updateVHKA (Gaudi::Details::PropertyBase &)
MsgStream & msg () const
bool msgLvl (const MSG::Level lvl) const

Static Public Member Functions

static const InterfaceID & interfaceID ()

Protected Member Functions

void renounceArray (SG::VarHandleKeyArray &handlesArray)
 remove all handles from I/O resolution
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > renounce (T &h)
void extraDeps_update_handler (Gaudi::Details::PropertyBase &ExtraDeps)
 Add StoreName to extra input/output deps as needed.

Private Types

typedef ServiceHandle< StoreGateSvcStoreGateSvc_t

Private Member Functions

StatusCode changeFPGAET (int tmp_eTowersIDs_subset[][6], int FPGAnumber, int eFEXnumber)
 Replace the Et in an FOGA by the ones in the test vector.
StatusCode loadFPGA (int)
 load the Et in an FPGA
StatusCode loaddic (int)
 load index of Et
StatusCode changeTowerET (LVL1::eTower *inputtower, int eta, int phi, int FPGAid) const
 Replace the Et in a tower by the ones in the test vector.
int getFPGAnumber (int iefex, int ifpga) const
 determine the index of an FPGA
std::vector< int > * loadBlock (const std::string &, int) const
 Load the Et or index in a block.
Gaudi::Details::PropertyBase & declareGaudiProperty (Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyType &)
 specialization for handling Gaudi::Property<SG::VarHandleKey>

Private Attributes

eTowerContainerm_eTowerContainer {}
int m_numberofevents {}
 number of events
ToolHandle< eFEXFPGATowerIdProviderm_eFEXFPGATowerIdProviderTool {this, "eFEXFPGATowerIdProviderTool", "LVL1::eFEXFPGATowerIdProvider", "Tool that provides tower-FPGA mapping"}
 tool needed for tower-FPGA mapping
std::string m_inputfile
 path to the input directory
std::unordered_map< int, std::unordered_map< int, unsigned int > * > m_alltowers
 map of all supercell ETs of FPGAs m_alltowers[FPGAid] = (supercell id,ET) supercell id = eta * 1000 + phi * 100 + layer * 10 + cell
std::unordered_map< int, std::vector< int > * > m_dict
 map for mapping infomation. m_dict[FPGAid] = [ list of supercell id in order ]
StoreGateSvc_t m_evtStore
 Pointer to StoreGate (event store by default)
StoreGateSvc_t m_detStore
 Pointer to StoreGate (detector store by default)
std::vector< SG::VarHandleKeyArray * > m_vhka
bool m_varHandleArraysDeclared

Detailed Description

Load Et of the test vector.

Replace the Et in all towers with the ones store in test vector files for the validation of the L1Calo simulation.

The test vector files should be keep in one single directory. The Et of each FPGA should be stored in separate files. The file name should be ***.csv where The first two digits are the index of the eFEX (0-23) while the third digit is the index of the FPGA (0-3).

The Et will be set to zero if the file of an FPGA cannot be found.

The index of the Et should be defined in the first block of the test vector and the other blocks define Et of each event. An example of the test vector can be found in /athena/Trigger/TrigT1/L1CaloFEX/L1CaloFEXSim/share/testvectorexample.txt.

Definition at line 51 of file eFakeTower.h.

Member Typedef Documentation

◆ StoreGateSvc_t

typedef ServiceHandle<StoreGateSvc> AthCommonDataStore< AthCommonMsg< AlgTool > >::StoreGateSvc_t
privateinherited

Definition at line 388 of file AthCommonDataStore.h.

Constructor & Destructor Documentation

◆ eFakeTower()

LVL1::eFakeTower::eFakeTower ( const std::string & type,
const std::string & name,
const IInterface * parent )

Constructor.

Definition at line 15 of file eFakeTower.cxx.

15 :
16 AthAlgTool(type, name, parent)
17{
18 declareInterface<eFakeTower>(this);
19}
AthAlgTool()
Default constructor:

◆ ~eFakeTower()

LVL1::eFakeTower::~eFakeTower ( )

Destructor.

Definition at line 21 of file eFakeTower.cxx.

21 {
22 for (auto& allfpga : m_alltowers) {
23 delete allfpga.second;
24 }
25 for (auto& allfpga : m_dict) {
26 delete allfpga.second;
27 }
28 m_alltowers.clear();
29}
std::unordered_map< int, std::unordered_map< int, unsigned int > * > m_alltowers
map of all supercell ETs of FPGAs m_alltowers[FPGAid] = (supercell id,ET) supercell id = eta * 1000 +...
Definition eFakeTower.h:146
std::unordered_map< int, std::vector< int > * > m_dict
map for mapping infomation. m_dict[FPGAid] = [ list of supercell id in order ]
Definition eFakeTower.h:149

Member Function Documentation

◆ changeFPGAET()

StatusCode LVL1::eFakeTower::changeFPGAET ( int tmp_eTowersIDs_subset[][6],
int FPGAnumber,
int eFEXnumber )
private

Replace the Et in an FOGA by the ones in the test vector.

Parameters
tmp_eTowersIDs_subsetArray of tower IDs in the FPGA
FPGAnumberFPGA index to locate the FPGA
eFEXnumbereFEX index to locate the FPGA
Returns
status code

Definition at line 136 of file eFakeTower.cxx.

136 {
137 // replace all supercell energies in the FPGA using the test vector.
138 for (int myrow = 0; myrow<10; myrow++){
139 for (int mycol = 0; mycol<6; mycol++){
140 LVL1::eTower* thistower = m_eTowerContainer->findTower(tmp_eTowersIDs_subset[myrow][mycol]);
141
142 // ignore umpty FPGA
143 bool nothaveFPGA = m_dict.find(getFPGAnumber(eFEXnumber, FPGAnumber)) == m_dict.end();
144 if (nothaveFPGA) {
145 continue;
146 }
147
148 ATH_CHECK( changeTowerET(thistower, mycol, myrow, getFPGAnumber(eFEXnumber, FPGAnumber)) );
149 }
150 }
151 return StatusCode::SUCCESS;
152}
#define ATH_CHECK
Evaluate an expression and check for errors.
StatusCode changeTowerET(LVL1::eTower *inputtower, int eta, int phi, int FPGAid) const
Replace the Et in a tower by the ones in the test vector.
eTowerContainer * m_eTowerContainer
Definition eFakeTower.h:129
int getFPGAnumber(int iefex, int ifpga) const
determine the index of an FPGA

◆ changeTowerET()

StatusCode LVL1::eFakeTower::changeTowerET ( LVL1::eTower * inputtower,
int eta,
int phi,
int FPGAid ) const
private

Replace the Et in a tower by the ones in the test vector.

Parameters
inputtowereTower object to be processed
etaeta index to locate the SuperCell
phiphi index to locate the SuperCell
FPGAidFPGA Id to locate the SuperCell
Returns
status code

Definition at line 154 of file eFakeTower.cxx.

154 {
155 // update the ETs of the eTower using the values of test vector.
156 inputtower->clearET();
157
158 inputtower->setET(0 ,getET(FPGAid, eta, phi, 0, 0), 0);
159
160 inputtower->setET(1, getET(FPGAid, eta, phi, 1, 0), 1);
161 inputtower->setET(2, getET(FPGAid, eta, phi, 1, 1), 1);
162 inputtower->setET(3, getET(FPGAid, eta, phi, 1, 2), 1);
163 inputtower->setET(4, getET(FPGAid, eta, phi, 1, 3), 1);
164
165 inputtower->setET(5, getET(FPGAid, eta, phi, 2, 0), 2);
166 inputtower->setET(6, getET(FPGAid, eta, phi, 2, 1), 2);
167 inputtower->setET(7, getET(FPGAid, eta, phi, 2, 2), 2);
168 inputtower->setET(8, getET(FPGAid, eta, phi, 2, 3), 2);
169
170 inputtower->setET(9, getET(FPGAid, eta, phi, 3, 0), 3);
171
172 inputtower->setET(10, getET(FPGAid, eta, phi, 4, 0), 4);
173 return StatusCode::SUCCESS;
174}
Scalar eta() const
pseudorapidity method
Scalar phi() const
phi method
virtual int getET(int FPGAid, int eta, int phi, int layer, int cell) const
obtain the Et of a tower slot
void clearET()
Clear supercell ET values.
Definition eTower.cxx:47
void setET(int cell, float et, int layer, bool ignoreDisable=false)
Definition eTower.cxx:99

◆ declareGaudiProperty()

Gaudi::Details::PropertyBase & AthCommonDataStore< AthCommonMsg< AlgTool > >::declareGaudiProperty ( Gaudi::Property< T, V, H > & hndl,
const SG::VarHandleKeyType &  )
inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKey>

Definition at line 156 of file AthCommonDataStore.h.

158 {
160 hndl.value(),
161 hndl.documentation());
162
163 }
Gaudi::Details::PropertyBase & declareProperty(Gaudi::Property< T, V, H > &t)

◆ declareProperty()

Gaudi::Details::PropertyBase & AthCommonDataStore< AthCommonMsg< AlgTool > >::declareProperty ( Gaudi::Property< T, V, H > & t)
inlineinherited

Definition at line 145 of file AthCommonDataStore.h.

145 {
146 typedef typename SG::HandleClassifier<T>::type htype;
148 }
Gaudi::Details::PropertyBase & declareGaudiProperty(Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyType &)
specialization for handling Gaudi::Property<SG::VarHandleKey>

◆ detStore()

const ServiceHandle< StoreGateSvc > & AthCommonDataStore< AthCommonMsg< AlgTool > >::detStore ( ) const
inlineinherited

The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 95 of file AthCommonDataStore.h.

◆ evtStore()

ServiceHandle< StoreGateSvc > & AthCommonDataStore< AthCommonMsg< AlgTool > >::evtStore ( )
inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 85 of file AthCommonDataStore.h.

◆ execute()

StatusCode LVL1::eFakeTower::execute ( )
virtual

replace the Tower Et with the ones stored in the test vector.

Definition at line 99 of file eFakeTower.cxx.

99 {
100 int FPGAtowerids[10][6];
101
102 // set the Et of all towers to zero first
103 for (int efex{ 0 }; efex < 24; efex++) {
104 for (int fpga{ 0 }; fpga < 4; fpga++) {
105 StatusCode sc = m_eFEXFPGATowerIdProviderTool->getRankedTowerIDinFPGA(efex, fpga, FPGAtowerids);
106 if (sc == StatusCode::FAILURE) {
107 return StatusCode::FAILURE;
108 }
109 for (int myrow = 0; myrow<10; myrow++){
110 for (int mycol = 0; mycol<6; mycol++){
111 LVL1::eTower* thistower = m_eTowerContainer->findTower(FPGAtowerids[myrow][mycol]);
112 thistower->clearET();
113 }
114 }
115 }
116 }
117
118 // replace all supercell energies in the eTowerContainer using the test vector.
119 for (int efex{ 0 }; efex < 24; efex++) {
120 for (int fpga{ 0 }; fpga < 4; fpga++) {
121 StatusCode sc = m_eFEXFPGATowerIdProviderTool->getRankedTowerIDinFPGA(efex, fpga, FPGAtowerids);
122 if (sc == StatusCode::FAILURE) {
123 return StatusCode::FAILURE;
124 }
125 ATH_CHECK( changeFPGAET(FPGAtowerids, fpga, efex) );
126 }
127 }
128 return StatusCode::SUCCESS;
129}
static Double_t sc
ToolHandle< eFEXFPGATowerIdProvider > m_eFEXFPGATowerIdProviderTool
tool needed for tower-FPGA mapping
Definition eFakeTower.h:137
StatusCode changeFPGAET(int tmp_eTowersIDs_subset[][6], int FPGAnumber, int eFEXnumber)
Replace the Et in an FOGA by the ones in the test vector.
::StatusCode StatusCode
StatusCode definition for legacy code.

◆ extraDeps_update_handler()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::extraDeps_update_handler ( Gaudi::Details::PropertyBase & ExtraDeps)
protectedinherited

Add StoreName to extra input/output deps as needed.

use the logic of the VarHandleKey to parse the DataObjID keys supplied via the ExtraInputs and ExtraOuputs Properties to add the StoreName if it's not explicitly given

◆ getET()

int LVL1::eFakeTower::getET ( int FPGAid,
int eta,
int phi,
int layer,
int cell ) const
virtual

obtain the Et of a tower slot

Parameters
FPGAidFPGA id
etaeta index of the tower (0-5)
phiphi index of the tower (0-9)
layerlayer (0-4)
celltower slot. (pre-sample, layer-4 and had: 0, layer-2 and layer-3: 0-3)
Returns
Et

Definition at line 49 of file eFakeTower.cxx.

49 {
50 // find the ET of a supercell.
51 if (eta > 5 || eta < 0) {
52 ATH_MSG_ERROR( "Requested Supercell does not exist.");
53 return 0;
54 }
55 if (phi > 9 || phi < 0) {
56 ATH_MSG_ERROR( "Requested Supercell does not exist.");
57 return 0;
58 }
59 if (layer > 4 || layer < 0) {
60 ATH_MSG_ERROR( "Requested Supercell does not exist.");
61 return 0;
62 }
63 if (cell > 3 || cell < 0) {
64 ATH_MSG_ERROR( "Requested Supercell does not exist.");
65 return 0;
66 }
67 if (m_dict.find(FPGAid) == m_dict.end()) {
68 return 0;
69 }
70 int id = eta * 1000 + phi * 100 + layer * 10 + cell;
71 if (m_alltowers.at(FPGAid)->find(id) == m_alltowers.at(FPGAid)->end()) {
72 ATH_MSG_ERROR( "Trying to access uninitiated supercell.");
73 return 0;
74 }
75 return m_alltowers.at(FPGAid)->at(id);
76}
#define ATH_MSG_ERROR(x)
@ layer
Definition HitInfo.h:79

◆ getFPGAnumber()

int LVL1::eFakeTower::getFPGAnumber ( int iefex,
int ifpga ) const
private

determine the index of an FPGA

Parameters
iefexId of the eFEX module (0-23)
ifpgaId of the FPGA (0-3)
Returns
FPGA index

Definition at line 244 of file eFakeTower.cxx.

244 {
245 return iefex * 10 + ifpga;
246}

◆ init()

StatusCode LVL1::eFakeTower::init ( const std::string & input_fileadress)
virtual

initiate with the path to the test vector directory

Definition at line 31 of file eFakeTower.cxx.

31 {
34 m_inputfile = input_fileadress;
35 std::string txt = ".txt";
36 for (int efex{ 0 }; efex < 24; efex++) {
37 for (int fpga{ 0 }; fpga < 4; fpga++) {
38 std::fstream fileStream;
39 fileStream.open(m_inputfile + std::to_string(getFPGAnumber(efex, fpga)) + txt);
40 if (fileStream.fail()) {
41 continue;
42 }
43 ATH_CHECK( loaddic(getFPGAnumber(efex, fpga)) );
44 }
45 }
46 return StatusCode::SUCCESS;
47}
std::string m_inputfile
path to the input directory
Definition eFakeTower.h:139
StatusCode loaddic(int)
load index of Et
int m_numberofevents
number of events
Definition eFakeTower.h:134

◆ inputHandles()

virtual std::vector< Gaudi::DataHandle * > AthCommonDataStore< AthCommonMsg< AlgTool > >::inputHandles ( ) const
overridevirtualinherited

Return this algorithm's input handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ interfaceID()

const InterfaceID & LVL1::eFakeTower::interfaceID ( )
inlinestatic

Definition at line 56 of file eFakeTower.h.

56{ return IID_IeFakeTower; };
static const InterfaceID IID_IeFakeTower("LVL1::eFakeTower", 1, 0)

◆ loadBlock()

std::vector< int > * LVL1::eFakeTower::loadBlock ( const std::string & inputfile,
int eventnumber ) const
private

Load the Et or index in a block.

Definition at line 209 of file eFakeTower.cxx.

209 {
210 // load the eventnumber_th block of the input file.
211 std::string eachline;
212 std::ifstream myfile(inputfile);
213 std::vector<int>* output = new std::vector<int>;
214 if (myfile.is_open()) {
215 int nblock = 0;
216 while (std::getline(myfile, eachline)) {
217 // The blocks are separated by empty lines.
218 if (eachline.length() < 3) {
219 nblock++;
220 }
221 if (nblock < eventnumber) {
222 continue;
223 }
224 else if (nblock > eventnumber) {
225 break;
226 }
227 std::string temvalue;
228 std::stringstream ss(eachline);
229 while (ss >> temvalue) {
230 // the first block is always the dic
231 if (eventnumber == 0) {
232 output->push_back(std::stoi(temvalue));
233 } else {
234 int et = eFEXCompression::expand(int(strtoull(temvalue.c_str(), nullptr, 16)));
235 output->push_back(et);
236 }
237 }
238 }
239 myfile.close();
240 }
241 return output;
242}
float et(const xAOD::jFexSRJetRoI *j)
static Double_t ss
static int expand(unsigned int code)
Uncompress data.
output
Definition merge.py:16

◆ loaddic()

StatusCode LVL1::eFakeTower::loaddic ( int FPGAid)
private

load index of Et

Definition at line 201 of file eFakeTower.cxx.

201 {
202 // load mapping information and store it in the m_dict object.
203 std::string txt = ".txt";
204 std::vector<int>* dic0 = loadBlock(m_inputfile + std::to_string(FPGAid) + txt, 0);
205 m_dict.insert(std::make_pair(FPGAid, dic0));
206 return StatusCode::SUCCESS;
207}
std::vector< int > * loadBlock(const std::string &, int) const
Load the Et or index in a block.

◆ loadFPGA()

StatusCode LVL1::eFakeTower::loadFPGA ( int FPGAid)
private

load the Et in an FPGA

Definition at line 176 of file eFakeTower.cxx.

176 {
177 std::string txt = ".txt";
178 // load ETs of an FPGA and store them in m_alltowers.
179
180 // Check if the mapping exists.
181 if (m_dict.find(FPGAid) == m_dict.end()) {
182 ATH_MSG_ERROR( "Mapping for FPGA "<< FPGAid << " does not exist!");
183 return StatusCode::FAILURE;
184 }
185 std::unique_ptr<std::vector<int>> Ets{loadBlock(m_inputfile + std::to_string(FPGAid) + txt, m_numberofevents)};
186
187 // check if the vector ETs have the same size as the mapping vector.
188 if (Ets->size() != (*m_dict[FPGAid]).size()) {
189 ATH_MSG_ERROR( "Unable to finish the tower mapping!" );
190 return StatusCode::FAILURE;
191 }
192 std::unordered_map<int, unsigned int>* ETmap = new std::unordered_map<int, unsigned int>;
193 for (size_t i{};const auto &thisEt : *Ets){
194 ETmap->emplace((*m_dict[FPGAid])[i++], thisEt);
195 }
196 m_alltowers[FPGAid] = ETmap;
197 return StatusCode::SUCCESS;
198}

◆ loadnext()

StatusCode LVL1::eFakeTower::loadnext ( )
virtual

Load the test vector of the next event.

Definition at line 78 of file eFakeTower.cxx.

79{
81 // load the next events.
82 for (auto& allfpga : m_alltowers) {
83 delete allfpga.second;
84 }
85 std::string txt = ".txt";
86 for (int efex{ 0 }; efex < 24; efex++) {
87 for (int fpga{ 0 }; fpga < 4; fpga++) {
88 std::fstream fileStream;
89 fileStream.open(m_inputfile + std::to_string(getFPGAnumber(efex, fpga)) + txt);
90 if (fileStream.fail()) {
91 continue;
92 }
93 ATH_CHECK( loadFPGA(getFPGAnumber(efex, fpga)) );
94 }
95 }
96 return StatusCode::SUCCESS;
97}
StatusCode loadFPGA(int)
load the Et in an FPGA

◆ msg()

MsgStream & AthCommonMsg< AlgTool >::msg ( ) const
inlineinherited

Definition at line 24 of file AthCommonMsg.h.

24 {
25 return this->msgStream();
26 }

◆ msgLvl()

bool AthCommonMsg< AlgTool >::msgLvl ( const MSG::Level lvl) const
inlineinherited

Definition at line 30 of file AthCommonMsg.h.

30 {
31 return this->msgLevel(lvl);
32 }

◆ outputHandles()

virtual std::vector< Gaudi::DataHandle * > AthCommonDataStore< AthCommonMsg< AlgTool > >::outputHandles ( ) const
overridevirtualinherited

Return this algorithm's output handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ renounce()

std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > AthCommonDataStore< AthCommonMsg< AlgTool > >::renounce ( T & h)
inlineprotectedinherited

Definition at line 380 of file AthCommonDataStore.h.

381 {
382 h.renounce();
384 }
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > renounce(T &h)

◆ renounceArray()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::renounceArray ( SG::VarHandleKeyArray & handlesArray)
inlineprotectedinherited

remove all handles from I/O resolution

Definition at line 364 of file AthCommonDataStore.h.

364 {
366 }

◆ seteTowers()

StatusCode LVL1::eFakeTower::seteTowers ( eTowerContainer * input)
virtual

Define the eTowerContainer object for which the Et will be replaced.

Definition at line 131 of file eFakeTower.cxx.

131 {
133 return StatusCode::SUCCESS;
134}

◆ sysInitialize()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysInitialize ( )
overridevirtualinherited

Perform system initialization for an algorithm.

We override this to declare all the elements of handle key arrays at the end of initialization. See comments on updateVHKA.

Reimplemented in asg::AsgMetadataTool, AthCheckedComponent< AthAlgTool >, AthCheckedComponent<::AthAlgTool >, and DerivationFramework::CfAthAlgTool.

◆ sysStart()

virtual StatusCode AthCommonDataStore< AthCommonMsg< AlgTool > >::sysStart ( )
overridevirtualinherited

Handle START transition.

We override this in order to make sure that conditions handle keys can cache a pointer to the conditions container.

◆ updateVHKA()

void AthCommonDataStore< AthCommonMsg< AlgTool > >::updateVHKA ( Gaudi::Details::PropertyBase & )
inlineinherited

Definition at line 308 of file AthCommonDataStore.h.

308 {
309 // debug() << "updateVHKA for property " << p.name() << " " << p.toString()
310 // << " size: " << m_vhka.size() << endmsg;
311 for (auto &a : m_vhka) {
313 for (auto k : keys) {
314 k->setOwner(this);
315 }
316 }
317 }
std::vector< SG::VarHandleKeyArray * > m_vhka

Member Data Documentation

◆ m_alltowers

std::unordered_map<int, std::unordered_map<int, unsigned int>*> LVL1::eFakeTower::m_alltowers
private

map of all supercell ETs of FPGAs m_alltowers[FPGAid] = (supercell id,ET) supercell id = eta * 1000 + phi * 100 + layer * 10 + cell

Definition at line 146 of file eFakeTower.h.

◆ m_detStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_detStore
privateinherited

Pointer to StoreGate (detector store by default)

Definition at line 393 of file AthCommonDataStore.h.

◆ m_dict

std::unordered_map<int, std::vector<int>*> LVL1::eFakeTower::m_dict
private

map for mapping infomation. m_dict[FPGAid] = [ list of supercell id in order ]

Definition at line 149 of file eFakeTower.h.

◆ m_eFEXFPGATowerIdProviderTool

ToolHandle<eFEXFPGATowerIdProvider> LVL1::eFakeTower::m_eFEXFPGATowerIdProviderTool {this, "eFEXFPGATowerIdProviderTool", "LVL1::eFEXFPGATowerIdProvider", "Tool that provides tower-FPGA mapping"}
private

tool needed for tower-FPGA mapping

Definition at line 137 of file eFakeTower.h.

137{this, "eFEXFPGATowerIdProviderTool", "LVL1::eFEXFPGATowerIdProvider", "Tool that provides tower-FPGA mapping"};

◆ m_eTowerContainer

eTowerContainer* LVL1::eFakeTower::m_eTowerContainer {}
private

Definition at line 129 of file eFakeTower.h.

129{}; //the eTowerContainer object for which the Et will be replaced

◆ m_evtStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< AlgTool > >::m_evtStore
privateinherited

Pointer to StoreGate (event store by default)

Definition at line 390 of file AthCommonDataStore.h.

◆ m_inputfile

std::string LVL1::eFakeTower::m_inputfile
private

path to the input directory

Definition at line 139 of file eFakeTower.h.

◆ m_numberofevents

int LVL1::eFakeTower::m_numberofevents {}
private

number of events

Definition at line 134 of file eFakeTower.h.

134{};

◆ m_varHandleArraysDeclared

bool AthCommonDataStore< AthCommonMsg< AlgTool > >::m_varHandleArraysDeclared
privateinherited

Definition at line 399 of file AthCommonDataStore.h.

◆ m_vhka

std::vector<SG::VarHandleKeyArray*> AthCommonDataStore< AthCommonMsg< AlgTool > >::m_vhka
privateinherited

Definition at line 398 of file AthCommonDataStore.h.


The documentation for this class was generated from the following files: