#include <FPGATrackSimLogicalHitsProcessAlg.h>

Inheritance diagram for FPGATrackSimLogicalHitsProcessAlg:

Public Member Functions
	FPGATrackSimLogicalHitsProcessAlg (const std::string &name, ISvcLocator *pSvcLocator)
virtual	~FPGATrackSimLogicalHitsProcessAlg ()=default
virtual StatusCode	initialize () override
virtual StatusCode	execute () override
virtual StatusCode	finalize () override
virtual StatusCode	sysInitialize () override
	Override sysInitialize.
virtual const DataObjIDColl &	extraOutputDeps () const override
	Return the list of extra output dependencies.
ServiceHandle< StoreGateSvc > &	evtStore ()
	The standard `StoreGateSvc` (event store) Returns (kind of) a pointer to the `StoreGateSvc`.
const ServiceHandle< StoreGateSvc > &	detStore () const
	The standard `StoreGateSvc/DetectorStore` Returns (kind of) a pointer to the `StoreGateSvc`.
virtual StatusCode	sysStart () override
	Handle START transition.
virtual std::vector< Gaudi::DataHandle * >	inputHandles () const override
	Return this algorithm's input handles.
virtual std::vector< Gaudi::DataHandle * >	outputHandles () const override
	Return this algorithm's output handles.
Gaudi::Details::PropertyBase &	declareProperty (Gaudi::Property< T, V, H > &t)
void	updateVHKA (Gaudi::Details::PropertyBase &)
MsgStream &	msg () const
bool	msgLvl (const MSG::Level lvl) const

Protected Member Functions
void	renounceArray (SG::VarHandleKeyArray &handlesArray)
	remove all handles from I/O resolution
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void >	renounce (T &h)
void	extraDeps_update_handler (Gaudi::Details::PropertyBase &ExtraDeps)
	Add StoreName to extra input/output deps as needed.

Private Types
typedef ServiceHandle< StoreGateSvc >	StoreGateSvc_t

Private Member Functions
StatusCode	writeOutputData (const std::vector< FPGATrackSimRoad > &roads_1st, std::vector< FPGATrackSimTrack > const &tracks_1st, FPGATrackSimDataFlowInfo const *dataFlowInfo)
void	printHitSubregions (std::vector< FPGATrackSimHit > const &hits)
bool	passesChi2Cut (const FPGATrackSimTrack &track)
std::vector< unsigned >	PickHitsToUse (layer_bitmask_t) const
void	MakeSeedTracks (std::vector< FPGATrackSimTrack > &tracks)
Gaudi::Details::PropertyBase &	declareGaudiProperty (Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyType &)
	specialization for handling Gaudi::Property<SG::VarHandleKey>

Private Attributes
std::string	m_description
ToolHandle< FPGATrackSimSpacePointsToolI >	m_spacepointsTool {this, "SpacePointTool", "FPGATrackSimSpacePointsTool/FPGATrackSimSpacePointsTool", "Space Points Tool"}
ToolHandle< FPGATrackSimRoadUnionTool >	m_roadFinderTool {this, "RoadFinder", "FPGATrackSimPatternMatchTool", "Road Finder Tool"}
ToolHandle< FPGATrackSimLLPRoadFilterTool >	m_LRTRoadFilterTool {this, "LRTRoadFilter", "FPGATrackSimLLPRoadFilterTool/FPGATrackSimLLPRoadFilterTool", "LRT Road Filter Tool"}
ToolHandle< IFPGATrackSimRoadFinderTool >	m_LRTRoadFinderTool {this, "LRTRoadFinder", "FPGATrackSimHoughTransform_d0phi0_Tool/FPGATrackSimHoughTransform_d0phi0_Tool", "LRT Road Finder Tool"}
ToolHandle< IFPGATrackSimRoadFilterTool >	m_roadFilterTool {this, "RoadFilter", "FPGATrackSimEtaPatternFilterTool", "Road Filter Tool"}
ToolHandle< IFPGATrackSimRoadFilterTool >	m_roadFilterTool2 {this, "RoadFilter2", "FPGATrackSimPhiRoadFilterTool", "Road Filter2 Tool"}
ToolHandle< FPGATrackSimNNTrackTool >	m_NNTrackTool {this, "NNTrackTool", "FPGATrackSimNNTrackTool/FPGATrackSimNNTrackTool", "NN Track Tool"}
ToolHandle< FPGATrackSimHoughRootOutputTool >	m_houghRootOutputTool {this, "HoughRootOutputTool", "FPGATrackSimHoughRootOutputTool/FPGATrackSimHoughRootOutputTool", "Hough ROOT Output Tool"}
ToolHandle< FPGATrackSimTrackFitterTool >	m_trackFitterTool_1st {this, "TrackFitter_1st", "FPGATrackSimTrackFitterTool/FPGATrackSimTrackFitterTool_1st", "1st stage track fit tool"}
ToolHandle< FPGATrackSimOverlapRemovalTool >	m_overlapRemovalTool_1st {this, "OverlapRemoval_1st", "FPGATrackSimOverlapRemovalTool/FPGATrackSimOverlapRemovalTool_1st", "1st stage overlap removal tool"}
ToolHandle< FPGATrackSimOutputHeaderTool >	m_writeOutputTool {this, "OutputTool", "FPGATrackSimOutputHeaderTool/FPGATrackSimOutputHeaderTool", "Output tool"}
ToolHandle< FPGATrackSimSlicingEngineTool >	m_slicingEngineTool {this, "SlicingEngineTool", "FPGATrackSimSlicingEngineTool/FPGATrackSimSlicingEngineTool", "Slicing engine tool"}
ServiceHandle< IFPGATrackSimMappingSvc >	m_FPGATrackSimMapping {this, "FPGATrackSimMapping", "FPGATrackSimMappingSvc", "FPGATrackSimMappingSvc"}
ServiceHandle< IFPGATrackSimEventSelectionSvc >	m_evtSel {this, "eventSelector", "", "Event selection Svc"}
ToolHandle< GenericMonitoringTool >	m_monTool {this,"MonTool", "", "Monitoring tool"}
ToolHandle< FPGATrackSimTrackMonitor >	m_1st_stage_road_monitor {this, "FirstStageRoadMonitor", "FPGATrackSimTrackMonitor", "First Stage Road Monitor"}
ToolHandle< FPGATrackSimTrackMonitor >	m_1st_stage_road_post_filter_1_monitor {this, "FirstStageRoadPostFilter1Monitor", "FPGATrackSimTrackMonitor", "First Stage Road Post Filter1 Monitor"}
ToolHandle< FPGATrackSimTrackMonitor >	m_1st_stage_road_post_OLR_monitor {this, "FirstStageRoadPostOverlapRemovalMonitor", "FPGATrackSimTrackMonitor", "First Stage Road Post Overlap Removal Monitor"}
ToolHandle< FPGATrackSimTrackMonitor >	m_1st_stage_road_post_filter_2_monitor {this, "FirstStageRoadPostFilter2Monitor", "FPGATrackSimTrackMonitor", "First Stage Road Post Filter2 Monitor"}
ToolHandle< FPGATrackSimTrackMonitor >	m_1st_stage_track_monitor {this, "FirstStageTrackMonitor", "FPGATrackSimTrackMonitor", "First Stage Track Monitor"}
ToolHandle< FPGATrackSimTrackMonitor >	m_1st_stage_track_post_setTruth_monitor {this, "FirstStageTrackPostSetTruthMonitor", "FPGATrackSimTrackMonitor", "First Stage Track Post Set to TruthTracks Monitor"}
ToolHandle< FPGATrackSimTrackMonitor >	m_1st_stage_track_post_chi2_monitor {this, "FirstStageTrackPostChi2Monitor", "FPGATrackSimTrackMonitor", "First Stage Track Post Chi2 Monitor"}
ToolHandle< FPGATrackSimTrackMonitor >	m_1st_stage_track_post_OLR_monitor {this, "FirstStageTrackPostOverlapRemovalTrackMonitor", "FPGATrackSimTrackMonitor", "First Stage Track Post Overlap Removal Monitor"}
ServiceHandle< IChronoStatSvc >	m_chrono {this,"ChronoStatSvc","ChronoStatSvc"}
Gaudi::Property< int >	m_SetTruthParametersForTracks {this, "SetTruthParametersForTracks", -1, "flag to override track parameters and set them to the truth values"}
Gaudi::Property< bool >	m_doSpacepoints {this, "Spacepoints", false, "flag to enable the spacepoint formation"}
Gaudi::Property< bool >	m_doTracking {this, "tracking", false, "flag to enable the tracking"}
Gaudi::Property< bool >	m_doMultiTruth {this, "doMultiTruth", true, "flag to enable the use of multi-truth information for hits"}
Gaudi::Property< bool >	m_doOverlapRemoval {this, "doOverlapRemoval", true , "flag to enable the overlap removal"}
Gaudi::Property< bool >	m_doMissingHitsChecks {this, "DoMissingHitsChecks", false}
Gaudi::Property< bool >	m_filterRoads {this, "FilterRoads", false, "enable first road filter"}
Gaudi::Property< bool >	m_filterRoads2 {this, "FilterRoads2", false, "enable second road filter"}
Gaudi::Property< bool >	m_doHoughRootOutput1st {this, "DoHoughRootOutput1st", false, "Dump output from the Hough Transform to flat ntuples"}
Gaudi::Property< bool >	m_doNNTrack {this, "DoNNTrack_1st", false, "Run NN track filtering for 1st stage"}
Gaudi::Property< bool >	m_doGNNTrack {this, "DoGNNTrack", false, "Run tracking algorithm for GNN" }
Gaudi::Property< bool >	m_doGNNPixelSeeding {this, "DoGNNPixelSeeding", false, "Flag to configure for GNN Pixel Seeding" }
Gaudi::Property< bool >	m_doLRT {this, "doLRT", false, "Enable Large Radius Tracking"}
Gaudi::Property< bool >	m_doLRTHitFiltering {this, "LRTHitFiltering", false, "flag to enable hit/cluster filtering for LRT"}
Gaudi::Property< bool >	m_writeOutputData {this, "writeOutputData", true,"write the output TTree"}
Gaudi::Property< float >	m_trackScoreCut {this, "TrackScoreCut", 25.0, "Minimum track score (e.g. chi2 or NN)." }
Gaudi::Property< std::vector< float > >	m_track_Chi2PhiCut {this, "Chi2PhiCut", {-1.0,-1.0}, "Minimum Phi specific Chi2 cuts for vector starting with zero missed hits and counting up, negative is not active" }
Gaudi::Property< std::vector< float > >	m_track_Chi2EtaCut {this, "Chi2EtaCut", {-1.0,-1.0}, "Minimum Eta specific Chi2 cuts for vector starting with zero missed hits and counting up, negative is not active" }
Gaudi::Property< int >	m_keepHitsStrategy {this, "keepHitsStrategy", -1, "If this is less than 0, do nothing. If 1, pick 3 hits furthest apart. If 2, pick 3 inner hits. If 3, pick 3 outer hits. If 4, drop only middle hit for 5/5 otherwise keep all 4 hits for 4/5"}
Gaudi::Property< bool >	m_writeOutNonSPStripHits {this, "writeOutNonSPStripHits", true, "Write tracks to RootOutput if they have strip hits which are not SPs"}
Gaudi::Property< int >	m_NumOfHitPerGrouping { this, "NumOfHitPerGrouping", 5, "Number of minimum overlapping hits for a track candidate to be removed in the HoughRootOutputTool"}
Gaudi::Property< bool >	m_passLowestChi2TrackOnly {this,"passLowestChi2TrackOnly", false, "case when passing only lowest chi2 track per road"}
Gaudi::Property< bool >	m_secondStageStrips {this, "secondStageStrips", true, "If set to true, strip hits/SPs go to the second stage. Otherwise they go to the first." }
Gaudi::Property< bool >	m_outputRoadUnionTool {this, "outputRoadUnionTool", false, "If set to true, create LogicalEventInputHeader in output ROOT file using road union tool."}
Gaudi::Property< int >	m_region {this, "Region", 0, "Region ID to assign to tracks"}
Gaudi::Property< bool >	m_writeInputBranches {this, "writeInputBranches", true, "If set to false, never write input branches"}
Gaudi::Property< int >	m_writeRegion {this,"writeRegion", -1, "Only output selected region, default is -1 which means not requirement"}
Gaudi::Property< std::string >	m_sliceBranch {this, "SliceBranchName", "LogicalEventSlicedHeader", "Name of the branch for sliced hits in output ROOT file." }
Gaudi::Property< std::string >	m_outputBranch {this, "outputBranchName", "LogicalEventOutputHeader", "Name of the branch for output data in output ROOT file." }
Gaudi::Property< std::string >	m_sliceFirstPixelBranch {this, "FirstPixelBranchName", "LogicalEventFirstPixelHeader", "Name of the branch for first stage pixel hits in output ROOT file"}
Gaudi::Property< std::string >	m_sliceSecondPixelBranch {this, "SecondPixelBranchName", "LogicalEventSecondPixelHeader", "Name of the branch for second stage pixel hits in output ROOT file"}
Gaudi::Property< std::string >	m_sliceStripBranch {this, "StripBranchName", "LogicalEventSpacepointHeader", "Name of the branch for (post-SP) strip hits in output ROOT file"}
Gaudi::Property< std::string >	m_sliceStripBranchPreSP {this, "StripPreSPBranchName", "LogicalEventStripHeader", "Name of the branch for (pre-SP) strip hits in output ROOT file"}
FPGATrackSimLogicalEventInputHeader *	m_slicedHitHeader = nullptr
FPGATrackSimLogicalEventInputHeader *	m_slicedFirstPixelHeader = nullptr
FPGATrackSimLogicalEventInputHeader *	m_slicedSecondPixelHeader = nullptr
FPGATrackSimLogicalEventInputHeader *	m_slicedStripHeader = nullptr
FPGATrackSimLogicalEventInputHeader *	m_slicedStripHeaderPreSP = nullptr
FPGATrackSimLogicalEventOutputHeader *	m_logicEventOutputHeader = nullptr
std::vector< FPGATrackSimTrack >	m_tracks_1st_guessedcheck
std::vector< FPGATrackSimTrack >	m_tracks_1st_nomiss
std::vector< FPGATrackSimTrack >	m_tracks_2nd_guessedcheck
std::vector< FPGATrackSimTrack >	m_tracks_2nd_nomiss
double	m_evt = 0
long	m_nRoadsTot = 0
long	m_nTracksTot = 0
long	m_nTracksChi2Tot = 0
long	m_nTracksChi2OLRTot = 0
double	m_evt_truth = 0
long	m_nRoadsFound = 0
long	m_nTracksFound = 0
long	m_nTracksChi2Found = 0
long	m_nTracksChi2OLRFound = 0
unsigned long	m_maxNRoadsFound = 0
unsigned long	m_maxNTracksTot = 0
unsigned long	m_maxNTracksChi2Tot = 0
unsigned long	m_maxNTracksChi2OLRTot = 0
SG::ReadHandleKey< FPGATrackSimHitCollection >	m_FPGAHitKey {this, "FPGATrackSimHitKey","FPGAHits", "FPGATrackSim hits key"}
SG::WriteHandleKey< FPGATrackSimClusterCollection >	m_FPGASpacePointsKey {this, "FPGATrackSimSpacePoints1stKey","FPGASpacePoints_1st","FPGATrackSim SpacePoints key"}
SG::WriteHandleKey< ConstDataVector< FPGATrackSimHitCollection > >	m_FPGAHitKey_1st {this, "FPGATrackSimHitKey_1st","FPGAHits_1st","FPGATrackSim 1st stage hits key"}
SG::WriteHandleKey< ConstDataVector< FPGATrackSimHitCollection > >	m_FPGAHitKey_2nd {this, "FPGATrackSimHitKey_2nd","FPGAHits_2nd","FPGATrackSim 2nd stage hits key"}
SG::WriteHandleKey< FPGATrackSimHitCollection >	m_FPGAHitFilteredKey {this, "FPGATrackSimHitFiltered1stKey","FPGAHitsFiltered_1st","FPGATrackSim Filtered Hits 1st stage key"}
SG::WriteHandleKey< FPGATrackSimRoadCollection >	m_FPGARoadKey {this, "FPGATrackSimRoad1stKey","FPGARoads_1st","FPGATrackSim Roads 1st stage key"}
SG::WriteHandleKey< FPGATrackSimTrackCollection >	m_FPGATrackKey {this, "FPGATrackSimTrack1stKey","FPGATracks_1st","FPGATrackSim Tracks 1st stage key"}
SG::ReadHandleKey< FPGATrackSimTruthTrackCollection >	m_FPGATruthTrackKey {this, "FPGATrackSimTruthTrackKey", "FPGATruthTracks", "FPGATrackSim truth tracks"}
SG::ReadHandleKey< FPGATrackSimOfflineTrackCollection >	m_FPGAOfflineTrackKey {this, "FPGATrackSimOfflineTrackKey", "FPGAOfflineTracks", "FPGATrackSim offline tracks"}
SG::ReadHandleKey< FPGATrackSimEventInfo >	m_FPGAEventInfoKey {this, "FPGATrackSimEventInfoKey", "FPGAEventInfo", "FPGATrackSim event info"}
DataObjIDColl	m_extendedExtraObjects
StoreGateSvc_t	m_evtStore
	Pointer to StoreGate (event store by default)
StoreGateSvc_t	m_detStore
	Pointer to StoreGate (detector store by default)
std::vector< SG::VarHandleKeyArray * >	m_vhka
bool	m_varHandleArraysDeclared

Detailed Description

Definition at line 69 of file FPGATrackSimLogicalHitsProcessAlg.h.

Member Typedef Documentation

◆ StoreGateSvc_t

typedef ServiceHandle<StoreGateSvc> AthCommonDataStore< AthCommonMsg< Algorithm > >::StoreGateSvc_t

privateinherited

Definition at line 388 of file AthCommonDataStore.h.

Constructor & Destructor Documentation

◆ FPGATrackSimLogicalHitsProcessAlg()

FPGATrackSimLogicalHitsProcessAlg::FPGATrackSimLogicalHitsProcessAlg	(	const std::string &	name,
		ISvcLocator *	pSvcLocator )

Definition at line 45 of file FPGATrackSimLogicalHitsProcessAlg.cxx.

                                                                                                                     :
    AthAlgorithm(name, pSvcLocator)
{
}

◆ ~FPGATrackSimLogicalHitsProcessAlg()

virtual FPGATrackSimLogicalHitsProcessAlg::~FPGATrackSimLogicalHitsProcessAlg ( )

virtualdefault

Member Function Documentation

◆ declareGaudiProperty()

Gaudi::Details::PropertyBase & AthCommonDataStore< AthCommonMsg< Algorithm > >::declareGaudiProperty	(	Gaudi::Property< T, V, H > &	hndl,
		const SG::VarHandleKeyType &	)

inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKey>

Definition at line 156 of file AthCommonDataStore.h.

  {
    return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
                                                       hndl.value(), 
                                                       hndl.documentation());
 
  }

◆ declareProperty()

Gaudi::Details::PropertyBase & AthCommonDataStore< AthCommonMsg< Algorithm > >::declareProperty ( Gaudi::Property< T, V, H > & t )

inlineinherited

Definition at line 145 of file AthCommonDataStore.h.

                                                                     {
    typedef typename SG::HandleClassifier<T>::type htype;
    return AthCommonDataStore<PBASE>::declareGaudiProperty(t, htype());
  }

◆ detStore()

const ServiceHandle< StoreGateSvc > & AthCommonDataStore< AthCommonMsg< Algorithm > >::detStore ( ) const

inlineinherited

The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 95 of file AthCommonDataStore.h.

95{ return m_detStore; }

AthCommonDataStore< AthCommonMsg< Algorithm > >::m_detStore

StoreGateSvc_t m_detStore

Definition AthCommonDataStore.h:393

◆ evtStore()

ServiceHandle< StoreGateSvc > & AthCommonDataStore< AthCommonMsg< Algorithm > >::evtStore ( )

inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 85 of file AthCommonDataStore.h.

85{ return m_evtStore; }

AthCommonDataStore< AthCommonMsg< Algorithm > >::m_evtStore

StoreGateSvc_t m_evtStore

Definition AthCommonDataStore.h:390

◆ execute()

StatusCode FPGATrackSimLogicalHitsProcessAlg::execute ( )

overridevirtual

(first track monitor, after getting tracks) create a vector of references from a vector of instances

(second track monitor, after set track parameters to truth) create a vector of references from a vector of instances

Definition at line 148 of file FPGATrackSimLogicalHitsProcessAlg.cxx.

{
    const EventContext& ctx = getContext();
 
    // Get reference to hits from StoreGate.
    SG::ReadHandle<FPGATrackSimHitCollection> FPGAHits(m_FPGAHitKey, ctx);
    if (!FPGAHits.isValid()) {
        if (m_evt == 0) {
            ATH_MSG_WARNING("Didn't receive " << FPGAHits.key() << " on first event; assuming no input events.");
        }
        SmartIF<IEventProcessor> appMgr{service("ApplicationMgr")};
        if (!appMgr) {
            ATH_MSG_ERROR("Failed to retrieve ApplicationMgr as IEventProcessor");
            return StatusCode::FAILURE;
        }
        return appMgr->stopRun();
    }
 
    // Set up write handles.
    SG::WriteHandle<ConstDataVector<FPGATrackSimHitCollection>> FPGAHits_1st (m_FPGAHitKey_1st,ctx);
    SG::WriteHandle<ConstDataVector<FPGATrackSimHitCollection>> FPGAHits_2nd (m_FPGAHitKey_2nd,ctx);
    SG::WriteHandle<FPGATrackSimRoadCollection> FPGARoads_1st (m_FPGARoadKey, ctx);
 
    // Use ConstDataVector with VIEW_ELEMENTS for non-owning const pointer storage
    ATH_CHECK( FPGAHits_1st.record (std::make_unique<ConstDataVector<FPGATrackSimHitCollection>>(SG::VIEW_ELEMENTS)) );
    ATH_CHECK( FPGAHits_2nd.record (std::make_unique<ConstDataVector<FPGATrackSimHitCollection>>(SG::VIEW_ELEMENTS)) );
    auto* FPGAHits_1st_cdv = FPGAHits_1st.ptr();
    auto* FPGAHits_2nd_cdv = FPGAHits_2nd.ptr();
 
    ATH_CHECK( FPGARoads_1st.record (std::make_unique<FPGATrackSimRoadCollection>()));
 
    SG::WriteHandle<FPGATrackSimTrackCollection> FPGATracks_1stHandle (m_FPGATrackKey, ctx);
    ATH_CHECK(FPGATracks_1stHandle.record (std::make_unique<FPGATrackSimTrackCollection>()));
 
    SG::WriteHandle<FPGATrackSimHitCollection> FPGAHitsFiltered_1st (m_FPGAHitFilteredKey, ctx);
    ATH_CHECK( FPGAHitsFiltered_1st.record (std::make_unique<FPGATrackSimHitCollection>()));
 
    SG::WriteHandle<FPGATrackSimClusterCollection> FPGASpacePoints (m_FPGASpacePointsKey, ctx);
    ATH_CHECK( FPGASpacePoints.record (std::make_unique<FPGATrackSimClusterCollection>()));
 
    // Query the event selection service to make sure this event passed cuts.
    if (!m_evtSel->getSelectedEvent()) {
 
      // Potentially write the output data, now it's empty and reset, but this keeps things synchronized over trees
      if (m_writeOutputData)  {
       std::vector<FPGATrackSimRoad> roads_1st;
       std::vector<FPGATrackSimTrack> tracks_1st;
       auto dataFlowInfo = std::make_unique<FPGATrackSimDataFlowInfo>();
       ATH_CHECK(writeOutputData(roads_1st, tracks_1st, dataFlowInfo.get()));
      }      
 
      return StatusCode::SUCCESS;
    }
    ATH_MSG_INFO("Event accepted by: " << m_evtSel->name());
    if ((m_writeRegion>=0)&&(m_writeRegion==m_evtSel->getRegionID())) {
        m_writeOutputTool->activateEventOutput();
    }
 
    // Event passes cuts, count it. technically, DataPrep does this now.
    m_evt++;
    // Read event info structure. all we need this for is to propagate to our event info structures.
    SG::ReadHandle<FPGATrackSimEventInfo> FPGAEventInfo(m_FPGAEventInfoKey, ctx);
    if (!FPGAEventInfo.isValid()) {
        ATH_MSG_ERROR("Could not find FPGA Event Info with key " << FPGAEventInfo.key());
        return StatusCode::FAILURE;
    }
    FPGATrackSimEventInfo eventInfo = *FPGAEventInfo.cptr();
    m_slicedFirstPixelHeader->newEvent(eventInfo);
    m_slicedSecondPixelHeader->newEvent(eventInfo);
    m_slicedStripHeader->newEvent(eventInfo);
    m_slicedStripHeaderPreSP->newEvent(eventInfo);
 
    std::vector<std::shared_ptr<const FPGATrackSimHit>> phits_output, phits_all, phits_1st, phits_2nd;
    std::vector<const FPGATrackSimHit*> phits_strips; // this should store pointers to strip hits for this region
 
    {
        std::optional<Athena::Chrono> chronoSplitHits;
        if constexpr (enableBenchmark) chronoSplitHits.emplace("1st Stage: Split hits to 1st and 2nd stage", m_chrono.get());
 
        phits_1st.reserve(FPGAHits->size());
        phits_2nd.reserve(FPGAHits->size());
        ATH_MSG_DEBUG("Incoming Hits: " << FPGAHits->size());
        for (const FPGATrackSimHit* hit : *(FPGAHits.cptr())) {
            phits_all.emplace_back(hit, [](const FPGATrackSimHit*) {});
        }
 
        // Use the slicing engine tool to do the stage-based separation. Does not use the pmap.
        m_slicingEngineTool->sliceHits(phits_all, phits_1st, phits_2nd, phits_strips);
    }
 
    // record 1st stage hits in SG (VIEW_ELEMENTS - no copy, just store pointers)
    for (auto& hit : phits_1st) {
        FPGAHits_1st_cdv->push_back(hit.get());
    }
 
    if(m_writeOutputData) *m_slicedStripHeaderPreSP = *m_slicedStripHeader;
    // The slicing engine puts strip hits into a logical event input header. That header now needs to go
    // to the spacepoint tool if it's turned on. Those hits then get added to phits_1st or phits_2nd as appropriate.
    if (m_doSpacepoints) {
        std::vector<FPGATrackSimCluster> spacepoints;
        std::optional<Athena::Chrono> chronoSPFormation;
        if constexpr (enableBenchmark) chronoSPFormation.emplace("1st Stage: SP formation", m_chrono.get());
        ATH_CHECK(m_spacepointsTool->DoSpacePoints(*m_slicedStripHeader, spacepoints));
        // Move spacepoints into the output container to avoid unnecessary copies
        for (FPGATrackSimCluster& cluster : spacepoints) {
            FPGASpacePoints->push_back(std::move(cluster));
        }
        
        // Add spacepoint hits to appropriate stage (using FPGASpacePoints directly from StoreGate)
        for (const auto& cluster : *FPGASpacePoints) {
            // Keep the exact constituent hits of the spacepoint (not just the cluster-equivalent summary)
            for (const auto& hit : cluster.getHitList()) {
                (m_secondStageStrips ? phits_2nd : phits_1st).emplace_back(&hit, [](const FPGATrackSimHit*){});
            }
        }
    } else {
        // If spacepoints are disabled, add strip hits from phits_strips (filled by slicing engine)
        // These pointers point to hits in FPGAHits, which has stable lifetime in StoreGate
        for (const FPGATrackSimHit* hit : phits_strips) {
            (m_secondStageStrips ? phits_2nd : phits_1st).emplace_back(hit, [](const FPGATrackSimHit*){});
        }
    }
 
    // VIEW_ELEMENTS - no copy, just store pointers
    for (auto& hit : phits_2nd) {
        FPGAHits_2nd_cdv->push_back(hit.get());
    }
 
    // Add all hits including SPs to this for the HoughRootOutputTool
    for (const FPGATrackSimHit* hit : *(FPGAHits_2nd.cptr())) {
        phits_output.emplace_back(hit, [](const FPGATrackSimHit*){});
    }
    ATH_MSG_DEBUG("1st stage hits: " << phits_1st.size() << "          2nd stage hits: " << phits_2nd.size() );
    if (phits_1st.empty()) {
      // Potentially write the output data, now it's empty and reset, but this keeps things synchronized over trees
      if (m_writeOutputData)  {
    std::vector<FPGATrackSimRoad> roads_1st;
    std::vector<FPGATrackSimTrack> tracks_1st;
    auto dataFlowInfo = std::make_unique<FPGATrackSimDataFlowInfo>();
    ATH_CHECK(writeOutputData(roads_1st, tracks_1st, dataFlowInfo.get()));
      }
      return StatusCode::SUCCESS;
    }
    
    // Get truth tracks from DataPrep as well.
    SG::ReadHandle<FPGATrackSimTruthTrackCollection> FPGATruthTracks(m_FPGATruthTrackKey, ctx);
    if (!FPGATruthTracks.isValid()) {
        ATH_MSG_ERROR("Could not find FPGA Truth Track Collection with key " << FPGATruthTracks.key());
        return StatusCode::FAILURE;
    }
    // Same for offline tracks.
    SG::ReadHandle<FPGATrackSimOfflineTrackCollection> FPGAOfflineTracks(m_FPGAOfflineTrackKey, ctx);
    if (!FPGAOfflineTracks.isValid()) {
        ATH_MSG_ERROR("Could not find FPGA Offline Track Collection with key " << FPGAOfflineTracks.key());
        return StatusCode::FAILURE;
    }
 
    //                      roads                     //
    const std::vector<FPGATrackSimTruthTrack>& truthtracks = *FPGATruthTracks;
    auto nLogicalLayers = m_FPGATrackSimMapping->PlaneMap_1st(0)->getNLogiLayers();
    auto monitorRoads = [&](auto& monitor, const auto& roads) {
        if (!monitor.empty()) {
            monitor->fillRoad(roads, truthtracks, nLogicalLayers);
        }
    };
 
    std::vector<FPGATrackSimRoad> roads_1st;
    {
        std::optional<Athena::Chrono> chronoGetRoads;
        if constexpr (enableBenchmark) chronoGetRoads.emplace("1st Stage: GetRoads", m_chrono.get());
        // get roads
        ATH_CHECK(m_roadFinderTool->getRoads(phits_1st, roads_1st, *(FPGATruthTracks.cptr())));
        monitorRoads(m_1st_stage_road_monitor, roads_1st);
    }
    
 
    {
        // Standard road Filter
        std::optional<Athena::Chrono> chronoRoadFiltering;
        if constexpr (enableBenchmark) chronoRoadFiltering.emplace("1st Stage: RoadFiltering", m_chrono.get());
        std::vector<FPGATrackSimRoad> postfilter_roads;
        if (m_filterRoads) {
            ATH_CHECK(m_roadFilterTool->filterRoads(roads_1st, postfilter_roads));
            roads_1st = std::move(postfilter_roads);
        }
        monitorRoads(m_1st_stage_road_post_filter_1_monitor, roads_1st);
    }
        
 
    {
    // overlap removal
    std::optional<Athena::Chrono> chronoOverlapRemoval;
    if constexpr (enableBenchmark) chronoOverlapRemoval.emplace("1st Stage: OverlapRemoval", m_chrono.get());
    if (m_doOverlapRemoval) ATH_CHECK(m_overlapRemovalTool_1st->runOverlapRemoval(roads_1st));
    monitorRoads(m_1st_stage_road_post_OLR_monitor, roads_1st);
    }
 
 
    {
        // Road Filter2
        std::optional<Athena::Chrono> chronoRoadFiltering2;
        if constexpr (enableBenchmark) chronoRoadFiltering2.emplace("1st Stage: RoadFiltering2", m_chrono.get());
        std::vector<FPGATrackSimRoad> postfilter2_roads;
        if (m_filterRoads2) {
            ATH_CHECK(m_roadFilterTool2->filterRoads(roads_1st, postfilter2_roads));
            roads_1st = std::move(postfilter2_roads);
        }
        monitorRoads(m_1st_stage_road_post_filter_2_monitor, roads_1st);
    }
    //                     tracks                     //
    auto monitorTracks = [&](auto& monitor, const auto& tracks) {
        if (monitor.empty()) return;
        // prepare vector<const FPGATrackSimTrack*> regardless of input type
        std::vector<const FPGATrackSimTrack*> track_ptrs;
        track_ptrs.reserve(tracks.size());
        // transform tracks into a vector of pointers
        if constexpr (std::is_pointer_v<typename std::decay_t<decltype(tracks)>::value_type>) {
            // tracks is std::vector<const FPGATrackSimTrack*>
            track_ptrs.insert(track_ptrs.end(), tracks.begin(), tracks.end());
        } else {
            // tracks is std::vector<FPGATrackSimTrack>
            std::transform(tracks.begin(), tracks.end(), std::back_inserter(track_ptrs), [](const auto& t) { return &t; });
        }
        // monitor using track pointers
        monitor->fillTrack(track_ptrs, truthtracks, 1.e15);
    };
 
    std::vector<FPGATrackSimTrack> tracks_1st;
    {
    // Get tracks
    std::optional<Athena::Chrono> chronoGettingTracks;
    if constexpr (enableBenchmark) chronoGettingTracks.emplace("1st Stage: Getting Tracks", m_chrono.get());
    if (m_doTracking) {
        if (m_doNNTrack) {
            ATH_MSG_DEBUG("Performing NN tracking");
            ATH_CHECK(m_NNTrackTool->getTracks_1st(roads_1st, tracks_1st));
            if (m_doGNNTrack) {
                ATH_MSG_DEBUG("Performing track parameter estimation");
                ATH_CHECK(m_NNTrackTool->setTrackParameters(tracks_1st,true,m_evtSel->getMin(), m_evtSel->getMax()));
            }
        } else {
            ATH_MSG_DEBUG("Performing Linear tracking");
            if (m_passLowestChi2TrackOnly) { // Pass only the lowest chi2 track per road
                // Loop over roads and keep only the best track for each road
                for (const auto& road : roads_1st) {
                    std::vector<FPGATrackSimTrack> tracksForCurrentRoad;
 
                    // Collect tracks for this road
                    std::vector<FPGATrackSimRoad> roadVec = {road};
                    ATH_CHECK(m_trackFitterTool_1st->getTracks(roadVec, tracksForCurrentRoad, m_evtSel->getMin(), m_evtSel->getMax()));
 
                    // Find the best track for this road
                    if (!tracksForCurrentRoad.empty()) {
                        auto bestTrackIter = std::min_element(
                            tracksForCurrentRoad.begin(), tracksForCurrentRoad.end(),
                            [](const FPGATrackSimTrack& a, const FPGATrackSimTrack& b) {
                                return a.getChi2ndof() < b.getChi2ndof();
                            });
 
                        if (bestTrackIter != tracksForCurrentRoad.end() && bestTrackIter->getChi2ndof() < 1.e15) {
                            tracks_1st.push_back(*bestTrackIter);
                        }
                    }
                }
            } else { // Pass all tracks with chi2 < 1e15
                ATH_CHECK(m_trackFitterTool_1st->getTracks(roads_1st, tracks_1st, m_evtSel->getMin(), m_evtSel->getMax()));
            }
        }
    } else { // No tracking; 
      ATH_MSG_DEBUG("No tracking. Just running dummy road2track algorith");
      if(m_doGNNPixelSeeding) { //For GNNPixelSeeding, convert the roads to a track in the simplest form
        for (const auto& road : roads_1st) {
            std::vector<std::shared_ptr<const FPGATrackSimHit>> track_hits;
            for (unsigned layer = 0; layer < road.getNLayers(); ++layer) {
                track_hits.insert(track_hits.end(), road.getHitPtrs(layer).begin(), road.getHitPtrs(layer).end());
            }
 
            FPGATrackSimTrack track_cand;
            track_cand.setNLayers(track_hits.size());
            for (size_t ihit = 0; ihit < track_hits.size(); ++ihit) {
                track_cand.setFPGATrackSimHit(ihit, track_hits[ihit]);
            }
            tracks_1st.push_back(track_cand); 
        }
      }
      else { roadsToTrack(roads_1st, tracks_1st, m_FPGATrackSimMapping->PlaneMap_1st(0)); }
    }
    
    // calculateTruth() before any monitors
    // this explicitly calculates barcode, barcodeFrac and eventIndex
    ATH_MSG_DEBUG("doMultiTruth = " << m_doMultiTruth);
    if (m_doMultiTruth)
        for (auto &track : tracks_1st)
            track.calculateTruth();
     
    monitorTracks(m_1st_stage_track_monitor, tracks_1st);
    }
    
 
    {
    // set track parameters to truth
    std::optional<Athena::Chrono> chronoSetTruthParams;
    if constexpr (enableBenchmark) chronoSetTruthParams.emplace("1st Stage: Set Track Parameters to Truth", m_chrono.get());
    //Loop over tracks and set the region for all of them, also optionally set track parameters to truth
    for (FPGATrackSimTrack& track : tracks_1st) {
        track.setRegion(m_region);
        if (m_SetTruthParametersForTracks >= 0 && truthtracks.size() > 0) {
            if (m_SetTruthParametersForTracks != 0)
            track.setQOverPt(truthtracks.front().getQOverPt());
            else if (m_SetTruthParametersForTracks != 1)
            track.setD0(truthtracks.front().getD0());
            else if (m_SetTruthParametersForTracks != 2)
            track.setPhi(truthtracks.front().getPhi());
            else if (m_SetTruthParametersForTracks != 3)
            track.setZ0(truthtracks.front().getZ0());
            else if (m_SetTruthParametersForTracks != 4)
            track.setEta(truthtracks.front().getEta());
        }
    }
    monitorTracks(m_1st_stage_track_post_setTruth_monitor, tracks_1st);
    }
 
    // Loop over roads and store them in SG (after track finding to also copy the sector information)
    for (auto const& road : roads_1st) {
        FPGARoads_1st->push_back(road);
    }
 
    // Do some simple monitoring of efficiencies for truth before anything else
    if (truthtracks.size() > 0) {
        m_evt_truth++;
        if (roads_1st.size() > 0) m_nRoadsFound++;
        if (roads_1st.size() > m_maxNRoadsFound) m_maxNRoadsFound = roads_1st.size();
        if (tracks_1st.size() > 0) {
            m_nTracksFound++;
            if (tracks_1st.size() > m_maxNTracksTot) m_maxNTracksTot = tracks_1st.size();
    }
    }
 
    
    // Apply OLR but remove tracks that failed chi2 first
    for (auto itrack = tracks_1st.begin(); itrack != tracks_1st.end();) {
      if (!passesChi2Cut(*itrack)) itrack = tracks_1st.erase(itrack);
      else ++itrack;
    }
    // do monitoring of chi2
    m_nTracksChi2Tot += tracks_1st.size();
    monitorTracks(m_1st_stage_track_post_chi2_monitor, tracks_1st);
 
    {
    // overlap removal
    std::optional<Athena::Chrono> chronoOverlapRemoval2;
    if constexpr (enableBenchmark) chronoOverlapRemoval2.emplace("1st Stage: OverlapRemoval", m_chrono.get());
    if (m_doOverlapRemoval)  ATH_CHECK(m_overlapRemovalTool_1st->runOverlapRemoval(tracks_1st));
    // monitor variables (vectors of pointers)
    std::vector<const FPGATrackSimTrack*> tracks_1st_after_chi2;
    std::vector<const FPGATrackSimTrack*> tracks_1st_after_overlap;
    for (const FPGATrackSimTrack& track : tracks_1st) {
      if (track.passedOR()) {
    tracks_1st_after_overlap.push_back(&track);
    m_nTracksChi2OLRTot++;
      }
    }
    monitorTracks(m_1st_stage_track_post_OLR_monitor, tracks_1st_after_overlap);
    }
 
    m_nRoadsTot += roads_1st.size();
    m_nTracksTot += tracks_1st.size();
    // Do some simple monitoring of efficiencies now for tracks passing chi2 and potentially OLR
    if (truthtracks.size() > 0) {
 
        unsigned npasschi2(0);
        unsigned npasschi2OLR(0);
        if (tracks_1st.size() > 0) {
      for (const auto& track : tracks_1st) { // these passed the chi2
        npasschi2++;
        if (track.passedOR()) {
          npasschi2OLR++;
        }
      }
    }
        if (npasschi2 > m_maxNTracksChi2Tot) m_maxNTracksChi2Tot = npasschi2;
        if (npasschi2OLR > m_maxNTracksChi2OLRTot) m_maxNTracksChi2OLRTot = npasschi2OLR;
        if (npasschi2 > 0) m_nTracksChi2Found++;
        if (npasschi2OLR > 0) m_nTracksChi2OLRFound++;
    }
 
    // Now pick hits for seeding, this changes the tracks to have fewer hits
    if (m_keepHitsStrategy > 0)  MakeSeedTracks(tracks_1st);
 
    for (const FPGATrackSimTrack& track : tracks_1st) {
      FPGATracks_1stHandle->push_back(track);
    }
 
    // Now, we may want to do large-radius tracking on the hits not used by the first stage tracking.
    // This follows overlap removal.
    std::vector<FPGATrackSimRoad> roadsLRT;
    std::vector<FPGATrackSimTrack> tracksLRT; // currently empty
    if (m_doLRT) {
        // Filter out hits that are on successful first-stage tracks
        std::vector<std::shared_ptr<const FPGATrackSimHit>> remainingHits;
 
        if (m_doLRTHitFiltering) {
            ATH_MSG_DEBUG("Doing hit filtering based on prompt tracks.");
            ATH_CHECK(m_LRTRoadFilterTool->filterUsedHits(tracks_1st, phits_1st, remainingHits));
 
            for (const auto &Hit : remainingHits) FPGAHitsFiltered_1st->push_back(new FPGATrackSimHit(*Hit));
 
        } else {
            ATH_MSG_DEBUG("No hit filtering requested; using all hits for LRT.");
            remainingHits = std::move(phits_1st);
        }
 
        // Get LRT roads with remaining hits
        ATH_MSG_DEBUG("Finding LRT roads");
        ATH_CHECK(m_LRTRoadFinderTool->getRoads( remainingHits, roadsLRT ));
    }
 
    auto dataFlowInfo = std::make_unique<FPGATrackSimDataFlowInfo>();
 
    // Write the output and reset
    if (m_writeOutputData)  {
        ATH_CHECK(writeOutputData(roads_1st, tracks_1st, dataFlowInfo.get()));
    }
 
    // This one we can do-- by passing in truth and offline tracks via storegate above (*FPGAOfflineTracks).
    if (m_doHoughRootOutput1st) {
        ATH_MSG_DEBUG("Running HoughRootOutputTool in 1st stage.");
 
        SmartIF<IEventProcessor> appMgr{service("ApplicationMgr")};
        if (!appMgr) {
            ATH_MSG_ERROR("Failed to retrieve ApplicationMgr as IEventProcessor");
            return StatusCode::FAILURE;
        }
 
        // Create output ROOT file
        ATH_CHECK(m_houghRootOutputTool->fillTree(tracks_1st, truthtracks, *FPGAOfflineTracks, phits_output, m_writeOutNonSPStripHits, false));
    }
 
    // Reset data pointers
    if (m_outputRoadUnionTool) m_slicedHitHeader->reset();
    m_logicEventOutputHeader->reset();
 
    return StatusCode::SUCCESS;
}

◆ extraDeps_update_handler()

void AthCommonDataStore< AthCommonMsg< Algorithm > >::extraDeps_update_handler ( Gaudi::Details::PropertyBase & ExtraDeps )

protectedinherited

Add StoreName to extra input/output deps as needed.

use the logic of the VarHandleKey to parse the DataObjID keys supplied via the ExtraInputs and ExtraOuputs Properties to add the StoreName if it's not explicitly given

◆ extraOutputDeps()

const DataObjIDColl & AthAlgorithm::extraOutputDeps ( ) const

overridevirtualinherited

Return the list of extra output dependencies.

This list is extended to include symlinks implied by inheritance relations.

Definition at line 50 of file AthAlgorithm.cxx.

{
  // If we didn't find any symlinks to add, just return the collection
  // from the base class.  Otherwise, return the extended collection.
  if (!m_extendedExtraObjects.empty()) {
    return m_extendedExtraObjects;
  }
  return Algorithm::extraOutputDeps();
}

◆ finalize()

StatusCode FPGATrackSimLogicalHitsProcessAlg::finalize ( )

overridevirtual

Definition at line 651 of file FPGATrackSimLogicalHitsProcessAlg.cxx.

{
    ATH_MSG_INFO("PRINTING FPGATRACKSIM SIMPLE STATS");
    ATH_MSG_INFO("========================================================================================");
    ATH_MSG_INFO("Ran on events = " << m_evt);
    ATH_MSG_INFO("Inclusive efficiency to find a road = " << (m_evt_truth == 0 ? "NAN" : std::to_string(m_nRoadsFound/(float)m_evt_truth)));
    ATH_MSG_INFO("New Inclusive efficiency to find a road = " << (m_evt_truth == 0 ? "NAN" : std::to_string(m_1st_stage_road_monitor->getNElements()/(float)m_evt_truth)));
    ATH_MSG_INFO("New Inclusive efficiency to find a road passing filter1 = " << (m_evt_truth == 0 ? "NAN" : std::to_string(m_1st_stage_road_post_filter_1_monitor->getNElements()/(float)m_evt_truth))); 
    ATH_MSG_INFO("New Inclusive efficiency to find a road passing OLR = " << (m_evt_truth == 0 ? "NAN" : std::to_string(m_1st_stage_road_post_OLR_monitor->getNElements()/(float)m_evt_truth)));
    ATH_MSG_INFO("New Inclusive efficiency to find a road passing filter2 = " << (m_evt_truth == 0 ? "NAN" : std::to_string(m_1st_stage_road_post_filter_2_monitor->getNElements()/(float)m_evt_truth)));
    ATH_MSG_INFO("Inclusive efficiency to find a track = " << (m_evt_truth == 0 ? "NAN" : std::to_string(m_nTracksFound/(float)m_evt_truth)));
    ATH_MSG_INFO("New Inclusive efficiency to find a track = " << (m_evt_truth == 0 ? "NAN" : std::to_string(m_1st_stage_track_monitor->getNElements()/(float)m_evt_truth)));
    ATH_MSG_INFO("New Inclusive efficiency to find a track after set truth= " << (m_evt_truth == 0 ? "NAN" : std::to_string(m_1st_stage_track_post_setTruth_monitor->getNElements()/(float)m_evt_truth)));
    ATH_MSG_INFO("Inclusive efficiency to find a track passing chi2 = " << (m_evt_truth == 0 ? "NAN" : std::to_string(m_nTracksChi2Found/(float)m_evt_truth)));
    ATH_MSG_INFO("New Inclusive efficiency to find a track passing chi2 = " << (m_evt_truth == 0 ? "NAN" : std::to_string(m_1st_stage_track_post_chi2_monitor->getNElements()/(float)m_evt_truth)));
    ATH_MSG_INFO("Inclusive efficiency to find a track passing chi2 and OLR = " << (m_evt_truth == 0 ? "NAN" : std::to_string(m_nTracksChi2OLRFound/(float)m_evt_truth)));
    ATH_MSG_INFO("New Inclusive efficiency to find a track passing chi2 and OLR = " << (m_evt_truth == 0 ? "NAN" : std::to_string(m_1st_stage_track_post_OLR_monitor->getNElements()/(float)m_evt_truth)));
    
 
    ATH_MSG_INFO("Number of 1st stage roads/event = " << (m_evt == 0 ? "NAN" : std::to_string(m_nRoadsTot/(float)m_evt)));
    ATH_MSG_INFO("New Number of 1st stage roads/event = " << (m_evt == 0 ? "NAN" : std::to_string(m_1st_stage_road_monitor->getTotNElements()/(float)m_evt)));
    ATH_MSG_INFO("New Number of 1st stage roads passing filter1/event = " << (m_evt == 0 ? "NAN" : std::to_string(m_1st_stage_road_post_filter_1_monitor->getTotNElements()/(float)m_evt))); 
    ATH_MSG_INFO("New Number of 1st stage roads passing OLR/event = " << (m_evt == 0 ? "NAN" : std::to_string(m_1st_stage_road_post_OLR_monitor->getTotNElements()/(float)m_evt)));
    ATH_MSG_INFO("New Number of 1st stage roads passing filter2/event = " << (m_evt == 0 ? "NAN" : std::to_string(m_1st_stage_road_post_filter_2_monitor->getTotNElements()/(float)m_evt)));
    
    ATH_MSG_INFO("Number of 1st stage track combinations/event = " << (m_evt == 0 ? "NAN" : std::to_string(m_nTracksTot/(float)m_evt)));
    ATH_MSG_INFO("New Number of 1st stage track combinations/event = " << (m_evt == 0 ? "NAN" : std::to_string(m_1st_stage_track_monitor->getTotNElements()/(float)m_evt)));
    ATH_MSG_INFO("New Number of 1st stage track after set truth/event= " << (m_evt == 0 ? "NAN" : std::to_string(m_1st_stage_track_post_setTruth_monitor->getTotNElements()/(float)m_evt)));
    ATH_MSG_INFO("Number of 1st stage tracks passing chi2/event = " << (m_evt == 0 ? "NAN" : std::to_string(m_nTracksChi2Tot/(float)m_evt)));
    ATH_MSG_INFO("New Number of 1st stage track passing chi2/event = " << (m_evt == 0 ? "NAN" : std::to_string(m_1st_stage_track_post_chi2_monitor->getTotNElements()/(float)m_evt)));
    ATH_MSG_INFO("Number of 1st stage tracks passing chi2 and OLR/event = " << (m_evt == 0 ? "NAN" : std::to_string(m_nTracksChi2OLRTot/(float)m_evt)));
    ATH_MSG_INFO("New Number of 1st stage track passing chi2 and OLR/event = " << (m_evt == 0 ? "NAN" : std::to_string(m_1st_stage_track_post_OLR_monitor->getTotNElements()/(float)m_evt)));
    ATH_MSG_INFO("========================================================================================");
 
    ATH_MSG_INFO("Max number of 1st stage roads in an event = " << m_maxNRoadsFound);
    ATH_MSG_INFO("New Max number of 1st stage roads in an event = " << m_1st_stage_road_monitor->getMaxNElements());
    ATH_MSG_INFO("New Max number of 1st stage roads passing filter1 in an event = " << m_1st_stage_road_post_filter_1_monitor->getMaxNElements());
    ATH_MSG_INFO("New Max number of 1st stage roads passing OLR in an event = " << m_1st_stage_road_post_OLR_monitor->getMaxNElements());
    ATH_MSG_INFO("New Max number of 1st stage roads passing filter2 in an event = " << m_1st_stage_road_post_filter_2_monitor->getMaxNElements());
    ATH_MSG_INFO("Max number of 1st stage track combinations in an event = " << m_maxNTracksTot);
    ATH_MSG_INFO("New Max number of 1st stage track combinations in an event = " << m_1st_stage_track_monitor->getMaxNElements());
    ATH_MSG_INFO("New Max number of 1st stage tracks after set truth in an event = " << m_1st_stage_track_post_setTruth_monitor->getMaxNElements());
    ATH_MSG_INFO("Max number of 1st stage tracks passing chi2 in an event = " << m_maxNTracksChi2Tot);
    ATH_MSG_INFO("New Max number of 1st stage tracks passing chi2 in an event = " << m_1st_stage_track_post_chi2_monitor->getMaxNElements());
    ATH_MSG_INFO("Max number of 1st stage tracks passing chi2 and OLR in an event = " << m_maxNTracksChi2OLRTot);
    ATH_MSG_INFO("New Max number of 1st stage tracks passing chi2 and OLR in an event = " << m_1st_stage_track_post_OLR_monitor->getMaxNElements());
    ATH_MSG_INFO("========================================================================================");
 
    return StatusCode::SUCCESS;
}

◆ initialize()

StatusCode FPGATrackSimLogicalHitsProcessAlg::initialize ( )

overridevirtual

Definition at line 51 of file FPGATrackSimLogicalHitsProcessAlg.cxx.

{
    // Dump the configuration to make sure it propagated through right
    const std::vector<Gaudi::Details::PropertyBase*> props = this->getProperties();
    for( Gaudi::Details::PropertyBase* prop : props ) {
        if (prop->ownerTypeName()==this->type()) {      
        ATH_MSG_DEBUG("Property:\t" << prop->name() << "\t : \t" << prop->toString());
        }
    }
  
    std::stringstream ss(m_description);
    std::string line;
    ATH_MSG_INFO("Tag config:");
    if (!m_description.empty()) {
        while (std::getline(ss, line, '\n')) {
            ATH_MSG_INFO('\t' << line);
        }
    }
    ATH_CHECK(m_roadFinderTool.retrieve());
    ATH_CHECK(m_LRTRoadFilterTool.retrieve(EnableTool{m_doLRT}));
    ATH_CHECK(m_LRTRoadFinderTool.retrieve(EnableTool{m_doLRT}));
    ATH_CHECK(m_houghRootOutputTool.retrieve(EnableTool{m_doHoughRootOutput1st}));
    ATH_CHECK(m_NNTrackTool.retrieve(EnableTool{m_doNNTrack}));
    ATH_CHECK(m_roadFilterTool.retrieve(EnableTool{m_filterRoads}));
    ATH_CHECK(m_roadFilterTool2.retrieve(EnableTool{m_filterRoads2}));
 
    ATH_CHECK(m_spacepointsTool.retrieve(EnableTool{m_doSpacepoints}));
 
    ATH_CHECK(m_trackFitterTool_1st.retrieve(EnableTool{m_doTracking}));
    ATH_CHECK(m_overlapRemovalTool_1st.retrieve());
    ATH_CHECK(m_writeOutputTool.retrieve());
    ATH_CHECK(m_FPGATrackSimMapping.retrieve());
    ATH_CHECK(m_slicingEngineTool.retrieve());
 
    ATH_CHECK(m_1st_stage_road_monitor.retrieve());
    ATH_CHECK(m_1st_stage_road_post_filter_1_monitor.retrieve());
    ATH_CHECK(m_1st_stage_road_post_OLR_monitor.retrieve());
    ATH_CHECK(m_1st_stage_road_post_filter_2_monitor.retrieve());
    ATH_CHECK(m_1st_stage_track_monitor.retrieve());
    ATH_CHECK(m_1st_stage_track_post_setTruth_monitor.retrieve());
    ATH_CHECK(m_1st_stage_track_post_chi2_monitor.retrieve());
    ATH_CHECK(m_1st_stage_track_post_OLR_monitor.retrieve());
 
 
 
    ATH_MSG_DEBUG("initialize() Instantiating root objects");
 
    // ROOT branches created for test vectors.
    m_logicEventOutputHeader = m_writeOutputTool->addOutputBranch(m_outputBranch.value(), true);
 
    if (m_outputRoadUnionTool) m_slicedHitHeader = m_writeOutputTool->addInputBranch(m_sliceBranch.value(), m_writeInputBranches);
      
    // Updated slicing engine test vectors will have three streams.
    m_slicedFirstPixelHeader = m_writeOutputTool->addInputBranch(m_sliceFirstPixelBranch.value(), m_writeInputBranches);
    m_slicedSecondPixelHeader = m_writeOutputTool->addInputBranch(m_sliceSecondPixelBranch.value(), m_writeInputBranches);
    m_slicedStripHeader = m_writeOutputTool->addInputBranch(m_sliceStripBranch.value(), m_writeInputBranches);
    
    // We also need a pre- and post- SP copy of the SPs.
    m_slicedStripHeaderPreSP = m_writeOutputTool->addInputBranch(m_sliceStripBranchPreSP.value(), m_writeInputBranches);
    
    // Connect the slicing tools accordingly. We probably no longer need to hook up the roadfinder here.
    if (m_outputRoadUnionTool) m_roadFinderTool->setupSlices(m_slicedHitHeader);
    m_slicingEngineTool->setupSlices(m_slicedFirstPixelHeader, m_slicedSecondPixelHeader, m_slicedStripHeader);
 
    ATH_MSG_DEBUG("initialize() Setting branch");
 
    if (!m_monTool.empty())
        ATH_CHECK(m_monTool.retrieve());
 
    ATH_CHECK( m_FPGASpacePointsKey.initialize() );
    ATH_CHECK( m_FPGAHitFilteredKey.initialize() );
    ATH_CHECK( m_FPGARoadKey.initialize() );
    ATH_CHECK( m_FPGATrackKey.initialize() );
    ATH_CHECK( m_FPGAHitKey.initialize() );
    ATH_CHECK( m_FPGAHitKey_1st.initialize() );
    ATH_CHECK( m_FPGAHitKey_2nd.initialize() );
    ATH_CHECK( m_FPGATruthTrackKey.initialize() );
    ATH_CHECK( m_FPGAOfflineTrackKey.initialize() );
    ATH_CHECK( m_FPGAEventInfoKey.initialize() );
 
    ATH_CHECK( m_chrono.retrieve() );
    ATH_MSG_DEBUG("initialize() Finished");
 
    return StatusCode::SUCCESS;
}

◆ inputHandles()

virtual std::vector< Gaudi::DataHandle * > AthCommonDataStore< AthCommonMsg< Algorithm > >::inputHandles ( ) const

overridevirtualinherited

Return this algorithm's input handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ MakeSeedTracks()

void FPGATrackSimLogicalHitsProcessAlg::MakeSeedTracks ( std::vector< FPGATrackSimTrack > & tracks )

private

Definition at line 771 of file FPGATrackSimLogicalHitsProcessAlg.cxx.

{
    for (auto &track : tracks) {        
      const auto& hitptrs = track.getFPGATrackSimHitPtrs();
      layer_bitmask_t hitmask = 0x0;
      for (unsigned ihit = 0; ihit < hitptrs.size(); ihit++) { // can't just use hit mask directly from track because that is for coordinates
    if (hitptrs[ihit] && hitptrs[ihit]->isReal()) hitmask |= (0x1 << ihit);
      }
      std::vector<unsigned> toUse = PickHitsToUse(hitmask);
      track.setNLayers(hitptrs.size()); //clears old hits
      for (unsigned lyrToUse : toUse) {
        track.setFPGATrackSimHit(lyrToUse, hitptrs.at(lyrToUse));
      }
    }  
}

◆ msg()

MsgStream & AthCommonMsg< Algorithm >::msg ( ) const

inlineinherited

Definition at line 24 of file AthCommonMsg.h.

                                {
    return this->msgStream();
  }

◆ msgLvl()

bool AthCommonMsg< Algorithm >::msgLvl ( const MSG::Level lvl ) const

inlineinherited

Definition at line 30 of file AthCommonMsg.h.

                                               {
    return this->msgLevel(lvl);
  }

◆ outputHandles()

virtual std::vector< Gaudi::DataHandle * > AthCommonDataStore< AthCommonMsg< Algorithm > >::outputHandles ( ) const

overridevirtualinherited

Return this algorithm's output handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

◆ passesChi2Cut()

bool FPGATrackSimLogicalHitsProcessAlg::passesChi2Cut ( const FPGATrackSimTrack & track )

private

Definition at line 747 of file FPGATrackSimLogicalHitsProcessAlg.cxx.

                                                                                   {
    bool retv = track.getChi2ndof() < m_trackScoreCut.value();
    
    if (int(track.getFPGATrackSimHitPtrs().size()) < track.getNHits()) 
        ATH_MSG_FATAL("More hits than layers on track");
 
    unsigned  missedhits = track.getFPGATrackSimHitPtrs().size() - track.getNHits();
    if ((missedhits>=m_track_Chi2PhiCut.value().size()) || 
        (missedhits>=m_track_Chi2EtaCut.value().size())) {
            ATH_MSG_ERROR("More missed hits than entries in Chi2 cut " <<missedhits << " " << m_track_Chi2PhiCut.value().size() << " " <<m_track_Chi2EtaCut.value().size() 
                   << track.getFPGATrackSimHitPtrs().size() << " " << track.getNHits());
        }
 
    if (m_track_Chi2PhiCut.value().at(missedhits) > 0) {
        retv &= track.getChi2Phi() < m_track_Chi2PhiCut.value().at(missedhits);
    }
    if (m_track_Chi2EtaCut.value().at(missedhits) > 0) {
        retv &= track.getChi2Eta() < m_track_Chi2EtaCut.value().at(missedhits);
    }
 
 
    return retv;
}

◆ PickHitsToUse()

std::vector< unsigned > FPGATrackSimLogicalHitsProcessAlg::PickHitsToUse ( layer_bitmask_t hitmask ) const

private

Definition at line 788 of file FPGATrackSimLogicalHitsProcessAlg.cxx.

{
  std::vector<unsigned> toUse;
  switch (m_keepHitsStrategy) {
    case 1: // try and pick hits furthest apart, use only 3
      {
        if (hitmask == 0x1f) { // miss no hits
          toUse = {0,2,4};
        }
        else if (hitmask == 0x1e) { // miss inner layer, ie layer 0
          toUse = {1,3,4};
        }
        else if (hitmask == 0x1d) { // miss layer 1
          toUse = {0,2,4};
        }
        else if (hitmask == 0x1b) { // miss layer 2
          toUse = {0,3,4};
        }
        else if (hitmask == 0x17) { // miss layer 3
          toUse = {0,2,4};
        }
        else if (hitmask == 0x0f) { // miss layer 4
          toUse = {0,2,3};
        }
      }
      break;
    case 2: // pick inner hits, use only 3
      {
        if (hitmask == 0x1f) { // miss no hits
          toUse = {0,1,2};
        }
        else if (hitmask == 0x1e) { // miss inner layer, ie layer 0
          toUse = {1,2,3};
        }
        else if (hitmask == 0x1d) { // miss layer 1
          toUse = {0,2,3};
        }
        else if (hitmask == 0x1b) { // miss layer 2
          toUse = {0,1,3};
        }
        else if (hitmask == 0x17) { // miss layer 3
          toUse = {0,1,2};
        }
        else if (hitmask == 0x0f) { // miss layer 4
          toUse = {0,1,2};
        }
      }
      break;
    case 3: // pick outer hits, use only 3
      {
        if (hitmask == 0x1f) { // miss no hits
          toUse = {2,3,4};
        }
        else if (hitmask == 0x1e) { // miss inner layer, ie layer 0
          toUse = {2,3,4};
        }
        else if (hitmask == 0x1d) { // miss layer 1
          toUse = {2,3,4};
        }
        else if (hitmask == 0x1b) { // miss layer 2
          toUse = {1,3,4};
        }
        else if (hitmask == 0x17) { // miss layer 3
          toUse = {1,2,4};
        }
        else if (hitmask == 0x0f) { // miss layer 4
          toUse = {1,2,3};
        }
      }
      break;
    case 4: // keep 4 hits, choose middle one to drop if necessary
      {
        if (hitmask == 0x1f) { // miss no hits
          toUse = {0,1,2,3};
        }
        else if (hitmask == 0x1e) { // miss inner layer, ie layer 0
          toUse = {1,2,3,4};
        }
        else if (hitmask == 0x1d) { // miss layer 1
          toUse = {0,2,3,4};
        }
        else if (hitmask == 0x1b) { // miss layer 2
          toUse = {0,1,3,4};
        }
        else if (hitmask == 0x17) { // miss layer 3
          toUse = {0,1,2,4};
        }
        else if (hitmask == 0x0f) { // miss layer 4
          toUse = {0,1,2,3};
        }
      }
      break;
  }
  return toUse;
}

◆ printHitSubregions()

void FPGATrackSimLogicalHitsProcessAlg::printHitSubregions ( std::vector< FPGATrackSimHit > const & hits )

private

Definition at line 732 of file FPGATrackSimLogicalHitsProcessAlg.cxx.

{
    ATH_MSG_WARNING("Hit regions:");
    for (const auto& hit : hits)
    {
        std::vector<uint32_t> regions = m_FPGATrackSimMapping->SubRegionMap()->getRegions(hit);
        std::stringstream ss;
        for (auto r : regions)
            ss << r << ",";
        ATH_MSG_WARNING("\t[" << ss.str() << "]");
    }
}

◆ renounce()

std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > AthCommonDataStore< AthCommonMsg< Algorithm > >::renounce ( T & h )

inlineprotectedinherited

Definition at line 380 of file AthCommonDataStore.h.

  {
    h.renounce();
    PBASE::renounce (h);
  }

◆ renounceArray()

void AthCommonDataStore< AthCommonMsg< Algorithm > >::renounceArray ( SG::VarHandleKeyArray & handlesArray )

inlineprotectedinherited

remove all handles from I/O resolution

Definition at line 364 of file AthCommonDataStore.h.

                                                          {
    handlesArray.renounce();
  }

◆ sysInitialize()

StatusCode AthAlgorithm::sysInitialize ( )

overridevirtualinherited

Override sysInitialize.

Override sysInitialize from the base class.

Loop through all output handles, and if they're WriteCondHandles, automatically register them and this Algorithm with the CondSvc

Scan through all outputHandles, and if they're WriteCondHandles, register them with the CondSvc

Reimplemented from AthCommonDataStore< AthCommonMsg< Algorithm > >.

Reimplemented in AthAnalysisAlgorithm, AthFilterAlgorithm, AthHistogramAlgorithm, and PyAthena::Alg.

Definition at line 66 of file AthAlgorithm.cxx.

                                       {
  StatusCode sc=AthCommonDataStore<AthCommonMsg<Algorithm>>::sysInitialize();
 
  if (sc.isFailure()) {
    return sc;
  }
  ServiceHandle<ICondSvc> cs("CondSvc",name());
  for (auto h : outputHandles()) {
    if (h->isCondition() && h->mode() == Gaudi::DataHandle::Writer) {
      // do this inside the loop so we don't create the CondSvc until needed
      if ( cs.retrieve().isFailure() ) {
        ATH_MSG_WARNING("no CondSvc found: won't autoreg WriteCondHandles");
        return StatusCode::SUCCESS;
      }
      if (cs->regHandle(this,*h).isFailure()) {
        sc = StatusCode::FAILURE;
        ATH_MSG_ERROR("unable to register WriteCondHandle " << h->fullKey()
                      << " with CondSvc");
      }
    }
  }
  return sc;
}

◆ sysStart()

virtual StatusCode AthCommonDataStore< AthCommonMsg< Algorithm > >::sysStart ( )

overridevirtualinherited

Handle START transition.

We override this in order to make sure that conditions handle keys can cache a pointer to the conditions container.

◆ updateVHKA()

void AthCommonDataStore< AthCommonMsg< Algorithm > >::updateVHKA ( Gaudi::Details::PropertyBase & )

inlineinherited

Definition at line 308 of file AthCommonDataStore.h.

                                               {
    // debug() << "updateVHKA for property " << p.name() << " " << p.toString() 
    //         << "  size: " << m_vhka.size() << endmsg;
    for (auto &a : m_vhka) {
      std::vector<SG::VarHandleKey*> keys = a->keys();
      for (auto k : keys) {
        k->setOwner(this);
      }
    }
  }

◆ writeOutputData()

StatusCode FPGATrackSimLogicalHitsProcessAlg::writeOutputData	(	const std::vector< FPGATrackSimRoad > &	roads_1st,
		std::vector< FPGATrackSimTrack > const &	tracks_1st,
		FPGATrackSimDataFlowInfo const *	dataFlowInfo )

private

Definition at line 620 of file FPGATrackSimLogicalHitsProcessAlg.cxx.

{
    m_logicEventOutputHeader->reset();
 
    ATH_MSG_DEBUG("NFPGATrackSimRoads_1st = " << roads_1st.size() << ", NFPGATrackSimTracks_1st = " << tracks_1st.size());
 
    if (!m_writeOutputData) return StatusCode::SUCCESS;
    m_logicEventOutputHeader->reserveFPGATrackSimRoads_1st(roads_1st.size());
    m_logicEventOutputHeader->addFPGATrackSimRoads_1st(roads_1st);   
 
    m_logicEventOutputHeader->reserveFPGATrackSimTracks_1st(tracks_1st.size());
    m_logicEventOutputHeader->addFPGATrackSimTracks_1st(tracks_1st);
 
    m_logicEventOutputHeader->setDataFlowInfo(*dataFlowInfo);
    ATH_MSG_DEBUG(m_logicEventOutputHeader->getDataFlowInfo());
 
    // It would be nice to rearrange this so both algorithms use one instance of this tool, I think.
    // Which means that dataprep can't call writeData because that does Fill().
    ATH_CHECK(m_writeOutputTool->writeData());
 
 
 
    return StatusCode::SUCCESS;
}

Member Data Documentation

◆ m_1st_stage_road_monitor

ToolHandle<FPGATrackSimTrackMonitor> FPGATrackSimLogicalHitsProcessAlg::m_1st_stage_road_monitor {this, "FirstStageRoadMonitor", "FPGATrackSimTrackMonitor", "First Stage Road Monitor"}

private

Definition at line 106 of file FPGATrackSimLogicalHitsProcessAlg.h.

106{this, "FirstStageRoadMonitor", "FPGATrackSimTrackMonitor", "First Stage Road Monitor"};

◆ m_1st_stage_road_post_filter_1_monitor

ToolHandle<FPGATrackSimTrackMonitor> FPGATrackSimLogicalHitsProcessAlg::m_1st_stage_road_post_filter_1_monitor {this, "FirstStageRoadPostFilter1Monitor", "FPGATrackSimTrackMonitor", "First Stage Road Post Filter1 Monitor"}

private

Definition at line 108 of file FPGATrackSimLogicalHitsProcessAlg.h.

108{this, "FirstStageRoadPostFilter1Monitor", "FPGATrackSimTrackMonitor", "First Stage Road Post Filter1 Monitor"};

◆ m_1st_stage_road_post_filter_2_monitor

ToolHandle<FPGATrackSimTrackMonitor> FPGATrackSimLogicalHitsProcessAlg::m_1st_stage_road_post_filter_2_monitor {this, "FirstStageRoadPostFilter2Monitor", "FPGATrackSimTrackMonitor", "First Stage Road Post Filter2 Monitor"}

private

Definition at line 112 of file FPGATrackSimLogicalHitsProcessAlg.h.

112{this, "FirstStageRoadPostFilter2Monitor", "FPGATrackSimTrackMonitor", "First Stage Road Post Filter2 Monitor"};

◆ m_1st_stage_road_post_OLR_monitor

ToolHandle<FPGATrackSimTrackMonitor> FPGATrackSimLogicalHitsProcessAlg::m_1st_stage_road_post_OLR_monitor {this, "FirstStageRoadPostOverlapRemovalMonitor", "FPGATrackSimTrackMonitor", "First Stage Road Post Overlap Removal Monitor"}

private

Definition at line 110 of file FPGATrackSimLogicalHitsProcessAlg.h.

110{this, "FirstStageRoadPostOverlapRemovalMonitor", "FPGATrackSimTrackMonitor", "First Stage Road Post Overlap Removal Monitor"};

◆ m_1st_stage_track_monitor

ToolHandle<FPGATrackSimTrackMonitor> FPGATrackSimLogicalHitsProcessAlg::m_1st_stage_track_monitor {this, "FirstStageTrackMonitor", "FPGATrackSimTrackMonitor", "First Stage Track Monitor"}

private

Definition at line 115 of file FPGATrackSimLogicalHitsProcessAlg.h.

115{this, "FirstStageTrackMonitor", "FPGATrackSimTrackMonitor", "First Stage Track Monitor"};

◆ m_1st_stage_track_post_chi2_monitor

ToolHandle<FPGATrackSimTrackMonitor> FPGATrackSimLogicalHitsProcessAlg::m_1st_stage_track_post_chi2_monitor {this, "FirstStageTrackPostChi2Monitor", "FPGATrackSimTrackMonitor", "First Stage Track Post Chi2 Monitor"}

private

Definition at line 119 of file FPGATrackSimLogicalHitsProcessAlg.h.

119{this, "FirstStageTrackPostChi2Monitor", "FPGATrackSimTrackMonitor", "First Stage Track Post Chi2 Monitor"};

◆ m_1st_stage_track_post_OLR_monitor

ToolHandle<FPGATrackSimTrackMonitor> FPGATrackSimLogicalHitsProcessAlg::m_1st_stage_track_post_OLR_monitor {this, "FirstStageTrackPostOverlapRemovalTrackMonitor", "FPGATrackSimTrackMonitor", "First Stage Track Post Overlap Removal Monitor"}

private

Definition at line 121 of file FPGATrackSimLogicalHitsProcessAlg.h.

121{this, "FirstStageTrackPostOverlapRemovalTrackMonitor", "FPGATrackSimTrackMonitor", "First Stage Track Post Overlap Removal Monitor"};

◆ m_1st_stage_track_post_setTruth_monitor

ToolHandle<FPGATrackSimTrackMonitor> FPGATrackSimLogicalHitsProcessAlg::m_1st_stage_track_post_setTruth_monitor {this, "FirstStageTrackPostSetTruthMonitor", "FPGATrackSimTrackMonitor", "First Stage Track Post Set to TruthTracks Monitor"}

private

Definition at line 117 of file FPGATrackSimLogicalHitsProcessAlg.h.

117{this, "FirstStageTrackPostSetTruthMonitor", "FPGATrackSimTrackMonitor", "First Stage Track Post Set to TruthTracks Monitor"};

◆ m_chrono

ServiceHandle<IChronoStatSvc> FPGATrackSimLogicalHitsProcessAlg::m_chrono {this,"ChronoStatSvc","ChronoStatSvc"}

private

Definition at line 125 of file FPGATrackSimLogicalHitsProcessAlg.h.

125{this,"ChronoStatSvc","ChronoStatSvc"};

◆ m_description

std::string FPGATrackSimLogicalHitsProcessAlg::m_description

private

Definition at line 81 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_detStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< Algorithm > >::m_detStore

privateinherited

Pointer to StoreGate (detector store by default)

Definition at line 393 of file AthCommonDataStore.h.

◆ m_doGNNPixelSeeding

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_doGNNPixelSeeding {this, "DoGNNPixelSeeding", false, "Flag to configure for GNN Pixel Seeding" }

private

Definition at line 139 of file FPGATrackSimLogicalHitsProcessAlg.h.

139{this, "DoGNNPixelSeeding", false, "Flag to configure for GNN Pixel Seeding" };

◆ m_doGNNTrack

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_doGNNTrack {this, "DoGNNTrack", false, "Run tracking algorithm for GNN" }

private

Definition at line 138 of file FPGATrackSimLogicalHitsProcessAlg.h.

138{this, "DoGNNTrack", false, "Run tracking algorithm for GNN" };

◆ m_doHoughRootOutput1st

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_doHoughRootOutput1st {this, "DoHoughRootOutput1st", false, "Dump output from the Hough Transform to flat ntuples"}

private

Definition at line 136 of file FPGATrackSimLogicalHitsProcessAlg.h.

136{this, "DoHoughRootOutput1st", false, "Dump output from the Hough Transform to flat ntuples"};

◆ m_doLRT

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_doLRT {this, "doLRT", false, "Enable Large Radius Tracking"}

private

Definition at line 140 of file FPGATrackSimLogicalHitsProcessAlg.h.

140{this, "doLRT", false, "Enable Large Radius Tracking"};

◆ m_doLRTHitFiltering

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_doLRTHitFiltering {this, "LRTHitFiltering", false, "flag to enable hit/cluster filtering for LRT"}

private

Definition at line 141 of file FPGATrackSimLogicalHitsProcessAlg.h.

141{this, "LRTHitFiltering", false, "flag to enable hit/cluster filtering for LRT"};

◆ m_doMissingHitsChecks

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_doMissingHitsChecks {this, "DoMissingHitsChecks", false}

private

Definition at line 133 of file FPGATrackSimLogicalHitsProcessAlg.h.

133{this, "DoMissingHitsChecks", false};

◆ m_doMultiTruth

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_doMultiTruth {this, "doMultiTruth", true, "flag to enable the use of multi-truth information for hits"}

private

Definition at line 131 of file FPGATrackSimLogicalHitsProcessAlg.h.

131{this, "doMultiTruth", true, "flag to enable the use of multi-truth information for hits"};

◆ m_doNNTrack

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_doNNTrack {this, "DoNNTrack_1st", false, "Run NN track filtering for 1st stage"}

private

Definition at line 137 of file FPGATrackSimLogicalHitsProcessAlg.h.

137{this, "DoNNTrack_1st", false, "Run NN track filtering for 1st stage"};

◆ m_doOverlapRemoval

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_doOverlapRemoval {this, "doOverlapRemoval", true , "flag to enable the overlap removal"}

private

Definition at line 132 of file FPGATrackSimLogicalHitsProcessAlg.h.

132{this, "doOverlapRemoval", true , "flag to enable the overlap removal"}; // defaul true to not change functionality

◆ m_doSpacepoints

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_doSpacepoints {this, "Spacepoints", false, "flag to enable the spacepoint formation"}

private

Definition at line 129 of file FPGATrackSimLogicalHitsProcessAlg.h.

129{this, "Spacepoints", false, "flag to enable the spacepoint formation"};

◆ m_doTracking

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_doTracking {this, "tracking", false, "flag to enable the tracking"}

private

Definition at line 130 of file FPGATrackSimLogicalHitsProcessAlg.h.

130{this, "tracking", false, "flag to enable the tracking"};

◆ m_evt

double FPGATrackSimLogicalHitsProcessAlg::m_evt = 0

private

Definition at line 178 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_evt_truth

double FPGATrackSimLogicalHitsProcessAlg::m_evt_truth = 0

private

Definition at line 184 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_evtSel

ServiceHandle<IFPGATrackSimEventSelectionSvc> FPGATrackSimLogicalHitsProcessAlg::m_evtSel {this, "eventSelector", "", "Event selection Svc"}

private

Definition at line 97 of file FPGATrackSimLogicalHitsProcessAlg.h.

97{this, "eventSelector", "", "Event selection Svc"};

◆ m_evtStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< Algorithm > >::m_evtStore

privateinherited

Pointer to StoreGate (event store by default)

Definition at line 390 of file AthCommonDataStore.h.

◆ m_extendedExtraObjects

DataObjIDColl AthAlgorithm::m_extendedExtraObjects

privateinherited

Definition at line 79 of file AthAlgorithm.h.

◆ m_filterRoads

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_filterRoads {this, "FilterRoads", false, "enable first road filter"}

private

Definition at line 134 of file FPGATrackSimLogicalHitsProcessAlg.h.

134{this, "FilterRoads", false, "enable first road filter"};

◆ m_filterRoads2

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_filterRoads2 {this, "FilterRoads2", false, "enable second road filter"}

private

Definition at line 135 of file FPGATrackSimLogicalHitsProcessAlg.h.

135{this, "FilterRoads2", false, "enable second road filter"};

◆ m_FPGAEventInfoKey

SG::ReadHandleKey<FPGATrackSimEventInfo> FPGATrackSimLogicalHitsProcessAlg::m_FPGAEventInfoKey {this, "FPGATrackSimEventInfoKey", "FPGAEventInfo", "FPGATrackSim event info"}

private

Definition at line 220 of file FPGATrackSimLogicalHitsProcessAlg.h.

220{this, "FPGATrackSimEventInfoKey", "FPGAEventInfo", "FPGATrackSim event info"};

◆ m_FPGAHitFilteredKey

SG::WriteHandleKey<FPGATrackSimHitCollection> FPGATrackSimLogicalHitsProcessAlg::m_FPGAHitFilteredKey {this, "FPGATrackSimHitFiltered1stKey","FPGAHitsFiltered_1st","FPGATrackSim Filtered Hits 1st stage key"}

private

Definition at line 214 of file FPGATrackSimLogicalHitsProcessAlg.h.

214{this, "FPGATrackSimHitFiltered1stKey","FPGAHitsFiltered_1st","FPGATrackSim Filtered Hits 1st stage key"};

◆ m_FPGAHitKey

SG::ReadHandleKey<FPGATrackSimHitCollection> FPGATrackSimLogicalHitsProcessAlg::m_FPGAHitKey {this, "FPGATrackSimHitKey","FPGAHits", "FPGATrackSim hits key"}

private

Definition at line 206 of file FPGATrackSimLogicalHitsProcessAlg.h.

206{this, "FPGATrackSimHitKey","FPGAHits", "FPGATrackSim hits key"};

◆ m_FPGAHitKey_1st

SG::WriteHandleKey<ConstDataVector<FPGATrackSimHitCollection> > FPGATrackSimLogicalHitsProcessAlg::m_FPGAHitKey_1st {this, "FPGATrackSimHitKey_1st","FPGAHits_1st","FPGATrackSim 1st stage hits key"}

private

Definition at line 212 of file FPGATrackSimLogicalHitsProcessAlg.h.

212{this, "FPGATrackSimHitKey_1st","FPGAHits_1st","FPGATrackSim 1st stage hits key"};

◆ m_FPGAHitKey_2nd

SG::WriteHandleKey<ConstDataVector<FPGATrackSimHitCollection> > FPGATrackSimLogicalHitsProcessAlg::m_FPGAHitKey_2nd {this, "FPGATrackSimHitKey_2nd","FPGAHits_2nd","FPGATrackSim 2nd stage hits key"}

private

Definition at line 213 of file FPGATrackSimLogicalHitsProcessAlg.h.

213{this, "FPGATrackSimHitKey_2nd","FPGAHits_2nd","FPGATrackSim 2nd stage hits key"};

◆ m_FPGAOfflineTrackKey

SG::ReadHandleKey<FPGATrackSimOfflineTrackCollection> FPGATrackSimLogicalHitsProcessAlg::m_FPGAOfflineTrackKey {this, "FPGATrackSimOfflineTrackKey", "FPGAOfflineTracks", "FPGATrackSim offline tracks"}

private

Definition at line 219 of file FPGATrackSimLogicalHitsProcessAlg.h.

219{this, "FPGATrackSimOfflineTrackKey", "FPGAOfflineTracks", "FPGATrackSim offline tracks"};

◆ m_FPGARoadKey

SG::WriteHandleKey<FPGATrackSimRoadCollection> FPGATrackSimLogicalHitsProcessAlg::m_FPGARoadKey {this, "FPGATrackSimRoad1stKey","FPGARoads_1st","FPGATrackSim Roads 1st stage key"}

private

Definition at line 215 of file FPGATrackSimLogicalHitsProcessAlg.h.

215{this, "FPGATrackSimRoad1stKey","FPGARoads_1st","FPGATrackSim Roads 1st stage key"};

◆ m_FPGASpacePointsKey

SG::WriteHandleKey<FPGATrackSimClusterCollection> FPGATrackSimLogicalHitsProcessAlg::m_FPGASpacePointsKey {this, "FPGATrackSimSpacePoints1stKey","FPGASpacePoints_1st","FPGATrackSim SpacePoints key"}

private

Definition at line 209 of file FPGATrackSimLogicalHitsProcessAlg.h.

209{this, "FPGATrackSimSpacePoints1stKey","FPGASpacePoints_1st","FPGATrackSim SpacePoints key"};

◆ m_FPGATrackKey

SG::WriteHandleKey<FPGATrackSimTrackCollection> FPGATrackSimLogicalHitsProcessAlg::m_FPGATrackKey {this, "FPGATrackSimTrack1stKey","FPGATracks_1st","FPGATrackSim Tracks 1st stage key"}

private

Definition at line 216 of file FPGATrackSimLogicalHitsProcessAlg.h.

216{this, "FPGATrackSimTrack1stKey","FPGATracks_1st","FPGATrackSim Tracks 1st stage key"};

◆ m_FPGATrackSimMapping

ServiceHandle<IFPGATrackSimMappingSvc> FPGATrackSimLogicalHitsProcessAlg::m_FPGATrackSimMapping {this, "FPGATrackSimMapping", "FPGATrackSimMappingSvc", "FPGATrackSimMappingSvc"}

private

Definition at line 96 of file FPGATrackSimLogicalHitsProcessAlg.h.

96{this, "FPGATrackSimMapping", "FPGATrackSimMappingSvc", "FPGATrackSimMappingSvc"};

◆ m_FPGATruthTrackKey

SG::ReadHandleKey<FPGATrackSimTruthTrackCollection> FPGATrackSimLogicalHitsProcessAlg::m_FPGATruthTrackKey {this, "FPGATrackSimTruthTrackKey", "FPGATruthTracks", "FPGATrackSim truth tracks"}

private

Definition at line 218 of file FPGATrackSimLogicalHitsProcessAlg.h.

218{this, "FPGATrackSimTruthTrackKey", "FPGATruthTracks", "FPGATrackSim truth tracks"};

◆ m_houghRootOutputTool

ToolHandle<FPGATrackSimHoughRootOutputTool> FPGATrackSimLogicalHitsProcessAlg::m_houghRootOutputTool {this, "HoughRootOutputTool", "FPGATrackSimHoughRootOutputTool/FPGATrackSimHoughRootOutputTool", "Hough ROOT Output Tool"}

private

Definition at line 91 of file FPGATrackSimLogicalHitsProcessAlg.h.

91{this, "HoughRootOutputTool", "FPGATrackSimHoughRootOutputTool/FPGATrackSimHoughRootOutputTool", "Hough ROOT Output Tool"};

◆ m_keepHitsStrategy

Gaudi::Property<int> FPGATrackSimLogicalHitsProcessAlg::m_keepHitsStrategy {this, "keepHitsStrategy", -1, "If this is less than 0, do nothing. If 1, pick 3 hits furthest apart. If 2, pick 3 inner hits. If 3, pick 3 outer hits. If 4, drop only middle hit for 5/5 otherwise keep all 4 hits for 4/5"}

private

Definition at line 146 of file FPGATrackSimLogicalHitsProcessAlg.h.

146{this, "keepHitsStrategy", -1, "If this is less than 0, do nothing. If 1, pick 3 hits furthest apart. If 2, pick 3 inner hits. If 3, pick 3 outer hits. If 4, drop only middle hit for 5/5 otherwise keep all 4 hits for 4/5"};

◆ m_logicEventOutputHeader

FPGATrackSimLogicalEventOutputHeader* FPGATrackSimLogicalHitsProcessAlg::m_logicEventOutputHeader = nullptr

private

Definition at line 172 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_LRTRoadFilterTool

ToolHandle<FPGATrackSimLLPRoadFilterTool> FPGATrackSimLogicalHitsProcessAlg::m_LRTRoadFilterTool {this, "LRTRoadFilter", "FPGATrackSimLLPRoadFilterTool/FPGATrackSimLLPRoadFilterTool", "LRT Road Filter Tool"}

private

Definition at line 86 of file FPGATrackSimLogicalHitsProcessAlg.h.

86{this, "LRTRoadFilter", "FPGATrackSimLLPRoadFilterTool/FPGATrackSimLLPRoadFilterTool", "LRT Road Filter Tool"};

◆ m_LRTRoadFinderTool

ToolHandle<IFPGATrackSimRoadFinderTool> FPGATrackSimLogicalHitsProcessAlg::m_LRTRoadFinderTool {this, "LRTRoadFinder", "FPGATrackSimHoughTransform_d0phi0_Tool/FPGATrackSimHoughTransform_d0phi0_Tool", "LRT Road Finder Tool"}

private

Definition at line 87 of file FPGATrackSimLogicalHitsProcessAlg.h.

87{this, "LRTRoadFinder", "FPGATrackSimHoughTransform_d0phi0_Tool/FPGATrackSimHoughTransform_d0phi0_Tool", "LRT Road Finder Tool"};

◆ m_maxNRoadsFound

unsigned long FPGATrackSimLogicalHitsProcessAlg::m_maxNRoadsFound = 0

private

Definition at line 190 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_maxNTracksChi2OLRTot

unsigned long FPGATrackSimLogicalHitsProcessAlg::m_maxNTracksChi2OLRTot = 0

private

Definition at line 193 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_maxNTracksChi2Tot

unsigned long FPGATrackSimLogicalHitsProcessAlg::m_maxNTracksChi2Tot = 0

private

Definition at line 192 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_maxNTracksTot

unsigned long FPGATrackSimLogicalHitsProcessAlg::m_maxNTracksTot = 0

private

Definition at line 191 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_monTool

ToolHandle<GenericMonitoringTool> FPGATrackSimLogicalHitsProcessAlg::m_monTool {this,"MonTool", "", "Monitoring tool"}

private

Definition at line 101 of file FPGATrackSimLogicalHitsProcessAlg.h.

101{this,"MonTool", "", "Monitoring tool"};

◆ m_NNTrackTool

ToolHandle<FPGATrackSimNNTrackTool> FPGATrackSimLogicalHitsProcessAlg::m_NNTrackTool {this, "NNTrackTool", "FPGATrackSimNNTrackTool/FPGATrackSimNNTrackTool", "NN Track Tool"}

private

Definition at line 90 of file FPGATrackSimLogicalHitsProcessAlg.h.

90{this, "NNTrackTool", "FPGATrackSimNNTrackTool/FPGATrackSimNNTrackTool", "NN Track Tool"};

◆ m_nRoadsFound

long FPGATrackSimLogicalHitsProcessAlg::m_nRoadsFound = 0

private

Definition at line 185 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_nRoadsTot

long FPGATrackSimLogicalHitsProcessAlg::m_nRoadsTot = 0

private

Definition at line 179 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_nTracksChi2Found

long FPGATrackSimLogicalHitsProcessAlg::m_nTracksChi2Found = 0

private

Definition at line 187 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_nTracksChi2OLRFound

long FPGATrackSimLogicalHitsProcessAlg::m_nTracksChi2OLRFound = 0

private

Definition at line 188 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_nTracksChi2OLRTot

long FPGATrackSimLogicalHitsProcessAlg::m_nTracksChi2OLRTot = 0

private

Definition at line 182 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_nTracksChi2Tot

long FPGATrackSimLogicalHitsProcessAlg::m_nTracksChi2Tot = 0

private

Definition at line 181 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_nTracksFound

long FPGATrackSimLogicalHitsProcessAlg::m_nTracksFound = 0

private

Definition at line 186 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_nTracksTot

long FPGATrackSimLogicalHitsProcessAlg::m_nTracksTot = 0

private

Definition at line 180 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_NumOfHitPerGrouping

Gaudi::Property<int> FPGATrackSimLogicalHitsProcessAlg::m_NumOfHitPerGrouping { this, "NumOfHitPerGrouping", 5, "Number of minimum overlapping hits for a track candidate to be removed in the HoughRootOutputTool"}

private

Definition at line 149 of file FPGATrackSimLogicalHitsProcessAlg.h.

149{ this, "NumOfHitPerGrouping", 5, "Number of minimum overlapping hits for a track candidate to be removed in the HoughRootOutputTool"};

◆ m_outputBranch

Gaudi::Property<std::string> FPGATrackSimLogicalHitsProcessAlg::m_outputBranch {this, "outputBranchName", "LogicalEventOutputHeader", "Name of the branch for output data in output ROOT file." }

private

Definition at line 159 of file FPGATrackSimLogicalHitsProcessAlg.h.

159{this, "outputBranchName", "LogicalEventOutputHeader", "Name of the branch for output data in output ROOT file." };

◆ m_outputRoadUnionTool

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_outputRoadUnionTool {this, "outputRoadUnionTool", false, "If set to true, create LogicalEventInputHeader in output ROOT file using road union tool."}

private

Definition at line 152 of file FPGATrackSimLogicalHitsProcessAlg.h.

152{this, "outputRoadUnionTool", false, "If set to true, create LogicalEventInputHeader in output ROOT file using road union tool."};

◆ m_overlapRemovalTool_1st

ToolHandle<FPGATrackSimOverlapRemovalTool> FPGATrackSimLogicalHitsProcessAlg::m_overlapRemovalTool_1st {this, "OverlapRemoval_1st", "FPGATrackSimOverlapRemovalTool/FPGATrackSimOverlapRemovalTool_1st", "1st stage overlap removal tool"}

private

Definition at line 93 of file FPGATrackSimLogicalHitsProcessAlg.h.

93{this, "OverlapRemoval_1st", "FPGATrackSimOverlapRemovalTool/FPGATrackSimOverlapRemovalTool_1st", "1st stage overlap removal tool"};

◆ m_passLowestChi2TrackOnly

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_passLowestChi2TrackOnly {this,"passLowestChi2TrackOnly", false, "case when passing only lowest chi2 track per road"}

private

Definition at line 150 of file FPGATrackSimLogicalHitsProcessAlg.h.

150{this,"passLowestChi2TrackOnly", false, "case when passing only lowest chi2 track per road"};

◆ m_region

Gaudi::Property<int> FPGATrackSimLogicalHitsProcessAlg::m_region {this, "Region", 0, "Region ID to assign to tracks"}

private

Definition at line 153 of file FPGATrackSimLogicalHitsProcessAlg.h.

153{this, "Region", 0, "Region ID to assign to tracks"};

◆ m_roadFilterTool

ToolHandle<IFPGATrackSimRoadFilterTool> FPGATrackSimLogicalHitsProcessAlg::m_roadFilterTool {this, "RoadFilter", "FPGATrackSimEtaPatternFilterTool", "Road Filter Tool"}

private

Definition at line 88 of file FPGATrackSimLogicalHitsProcessAlg.h.

88{this, "RoadFilter", "FPGATrackSimEtaPatternFilterTool", "Road Filter Tool"};

◆ m_roadFilterTool2

ToolHandle<IFPGATrackSimRoadFilterTool> FPGATrackSimLogicalHitsProcessAlg::m_roadFilterTool2 {this, "RoadFilter2", "FPGATrackSimPhiRoadFilterTool", "Road Filter2 Tool"}

private

Definition at line 89 of file FPGATrackSimLogicalHitsProcessAlg.h.

89{this, "RoadFilter2", "FPGATrackSimPhiRoadFilterTool", "Road Filter2 Tool"};

◆ m_roadFinderTool

ToolHandle<FPGATrackSimRoadUnionTool> FPGATrackSimLogicalHitsProcessAlg::m_roadFinderTool {this, "RoadFinder", "FPGATrackSimPatternMatchTool", "Road Finder Tool"}

private

Definition at line 85 of file FPGATrackSimLogicalHitsProcessAlg.h.

85{this, "RoadFinder", "FPGATrackSimPatternMatchTool", "Road Finder Tool"};

◆ m_secondStageStrips

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_secondStageStrips {this, "secondStageStrips", true, "If set to true, strip hits/SPs go to the second stage. Otherwise they go to the first." }

private

Definition at line 151 of file FPGATrackSimLogicalHitsProcessAlg.h.

151{this, "secondStageStrips", true, "If set to true, strip hits/SPs go to the second stage. Otherwise they go to the first." };

◆ m_SetTruthParametersForTracks

Gaudi::Property<int> FPGATrackSimLogicalHitsProcessAlg::m_SetTruthParametersForTracks {this, "SetTruthParametersForTracks", -1, "flag to override track parameters and set them to the truth values"}

private

Definition at line 128 of file FPGATrackSimLogicalHitsProcessAlg.h.

128{this, "SetTruthParametersForTracks", -1, "flag to override track parameters and set them to the truth values"};

◆ m_sliceBranch

Gaudi::Property<std::string> FPGATrackSimLogicalHitsProcessAlg::m_sliceBranch {this, "SliceBranchName", "LogicalEventSlicedHeader", "Name of the branch for sliced hits in output ROOT file." }

private

Definition at line 158 of file FPGATrackSimLogicalHitsProcessAlg.h.

158{this, "SliceBranchName", "LogicalEventSlicedHeader", "Name of the branch for sliced hits in output ROOT file." };

◆ m_slicedFirstPixelHeader

FPGATrackSimLogicalEventInputHeader* FPGATrackSimLogicalHitsProcessAlg::m_slicedFirstPixelHeader = nullptr

private

Definition at line 168 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_slicedHitHeader

FPGATrackSimLogicalEventInputHeader* FPGATrackSimLogicalHitsProcessAlg::m_slicedHitHeader = nullptr

private

Definition at line 167 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_slicedSecondPixelHeader

FPGATrackSimLogicalEventInputHeader* FPGATrackSimLogicalHitsProcessAlg::m_slicedSecondPixelHeader = nullptr

private

Definition at line 169 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_slicedStripHeader

FPGATrackSimLogicalEventInputHeader* FPGATrackSimLogicalHitsProcessAlg::m_slicedStripHeader = nullptr

private

Definition at line 170 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_slicedStripHeaderPreSP

FPGATrackSimLogicalEventInputHeader* FPGATrackSimLogicalHitsProcessAlg::m_slicedStripHeaderPreSP = nullptr

private

Definition at line 171 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_sliceFirstPixelBranch

Gaudi::Property<std::string> FPGATrackSimLogicalHitsProcessAlg::m_sliceFirstPixelBranch {this, "FirstPixelBranchName", "LogicalEventFirstPixelHeader", "Name of the branch for first stage pixel hits in output ROOT file"}

private

Definition at line 160 of file FPGATrackSimLogicalHitsProcessAlg.h.

160{this, "FirstPixelBranchName", "LogicalEventFirstPixelHeader", "Name of the branch for first stage pixel hits in output ROOT file"};

◆ m_sliceSecondPixelBranch

Gaudi::Property<std::string> FPGATrackSimLogicalHitsProcessAlg::m_sliceSecondPixelBranch {this, "SecondPixelBranchName", "LogicalEventSecondPixelHeader", "Name of the branch for second stage pixel hits in output ROOT file"}

private

Definition at line 161 of file FPGATrackSimLogicalHitsProcessAlg.h.

161{this, "SecondPixelBranchName", "LogicalEventSecondPixelHeader", "Name of the branch for second stage pixel hits in output ROOT file"};

◆ m_sliceStripBranch

Gaudi::Property<std::string> FPGATrackSimLogicalHitsProcessAlg::m_sliceStripBranch {this, "StripBranchName", "LogicalEventSpacepointHeader", "Name of the branch for (post-SP) strip hits in output ROOT file"}

private

Definition at line 162 of file FPGATrackSimLogicalHitsProcessAlg.h.

162{this, "StripBranchName", "LogicalEventSpacepointHeader", "Name of the branch for (post-SP) strip hits in output ROOT file"};

◆ m_sliceStripBranchPreSP

Gaudi::Property<std::string> FPGATrackSimLogicalHitsProcessAlg::m_sliceStripBranchPreSP {this, "StripPreSPBranchName", "LogicalEventStripHeader", "Name of the branch for (pre-SP) strip hits in output ROOT file"}

private

Definition at line 163 of file FPGATrackSimLogicalHitsProcessAlg.h.

163{this, "StripPreSPBranchName", "LogicalEventStripHeader", "Name of the branch for (pre-SP) strip hits in output ROOT file"};

◆ m_slicingEngineTool

ToolHandle<FPGATrackSimSlicingEngineTool> FPGATrackSimLogicalHitsProcessAlg::m_slicingEngineTool {this, "SlicingEngineTool", "FPGATrackSimSlicingEngineTool/FPGATrackSimSlicingEngineTool", "Slicing engine tool"}

private

Definition at line 95 of file FPGATrackSimLogicalHitsProcessAlg.h.

95{this, "SlicingEngineTool", "FPGATrackSimSlicingEngineTool/FPGATrackSimSlicingEngineTool", "Slicing engine tool"};

◆ m_spacepointsTool

ToolHandle<FPGATrackSimSpacePointsToolI> FPGATrackSimLogicalHitsProcessAlg::m_spacepointsTool {this, "SpacePointTool", "FPGATrackSimSpacePointsTool/FPGATrackSimSpacePointsTool", "Space Points Tool"}

private

Definition at line 84 of file FPGATrackSimLogicalHitsProcessAlg.h.

84{this, "SpacePointTool", "FPGATrackSimSpacePointsTool/FPGATrackSimSpacePointsTool", "Space Points Tool"};

◆ m_track_Chi2EtaCut

Gaudi::Property<std::vector<float> > FPGATrackSimLogicalHitsProcessAlg::m_track_Chi2EtaCut {this, "Chi2EtaCut", {-1.0,-1.0}, "Minimum Eta specific Chi2 cuts for vector starting with zero missed hits and counting up, negative is not active" }

private

Definition at line 145 of file FPGATrackSimLogicalHitsProcessAlg.h.

145{this, "Chi2EtaCut", {-1.0,-1.0}, "Minimum Eta specific Chi2 cuts for vector starting with zero missed hits and counting up, negative is not active" };

◆ m_track_Chi2PhiCut

Gaudi::Property<std::vector<float> > FPGATrackSimLogicalHitsProcessAlg::m_track_Chi2PhiCut {this, "Chi2PhiCut", {-1.0,-1.0}, "Minimum Phi specific Chi2 cuts for vector starting with zero missed hits and counting up, negative is not active" }

private

Definition at line 144 of file FPGATrackSimLogicalHitsProcessAlg.h.

144{this, "Chi2PhiCut", {-1.0,-1.0}, "Minimum Phi specific Chi2 cuts for vector starting with zero missed hits and counting up, negative is not active" };

◆ m_trackFitterTool_1st

ToolHandle<FPGATrackSimTrackFitterTool> FPGATrackSimLogicalHitsProcessAlg::m_trackFitterTool_1st {this, "TrackFitter_1st", "FPGATrackSimTrackFitterTool/FPGATrackSimTrackFitterTool_1st", "1st stage track fit tool"}

private

Definition at line 92 of file FPGATrackSimLogicalHitsProcessAlg.h.

92{this, "TrackFitter_1st", "FPGATrackSimTrackFitterTool/FPGATrackSimTrackFitterTool_1st", "1st stage track fit tool"};

◆ m_tracks_1st_guessedcheck

std::vector<FPGATrackSimTrack> FPGATrackSimLogicalHitsProcessAlg::m_tracks_1st_guessedcheck

private

Definition at line 175 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_tracks_1st_nomiss

std::vector<FPGATrackSimTrack> FPGATrackSimLogicalHitsProcessAlg::m_tracks_1st_nomiss

private

Definition at line 175 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_tracks_2nd_guessedcheck

std::vector<FPGATrackSimTrack> FPGATrackSimLogicalHitsProcessAlg::m_tracks_2nd_guessedcheck

private

Definition at line 175 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_tracks_2nd_nomiss

std::vector<FPGATrackSimTrack> FPGATrackSimLogicalHitsProcessAlg::m_tracks_2nd_nomiss

private

Definition at line 175 of file FPGATrackSimLogicalHitsProcessAlg.h.

◆ m_trackScoreCut

Gaudi::Property<float> FPGATrackSimLogicalHitsProcessAlg::m_trackScoreCut {this, "TrackScoreCut", 25.0, "Minimum track score (e.g. chi2 or NN)." }

private

Definition at line 143 of file FPGATrackSimLogicalHitsProcessAlg.h.

143{this, "TrackScoreCut", 25.0, "Minimum track score (e.g. chi2 or NN)." };

◆ m_varHandleArraysDeclared

bool AthCommonDataStore< AthCommonMsg< Algorithm > >::m_varHandleArraysDeclared

privateinherited

Definition at line 399 of file AthCommonDataStore.h.

◆ m_vhka

std::vector<SG::VarHandleKeyArray*> AthCommonDataStore< AthCommonMsg< Algorithm > >::m_vhka

privateinherited

Definition at line 398 of file AthCommonDataStore.h.

◆ m_writeInputBranches

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_writeInputBranches {this, "writeInputBranches", true, "If set to false, never write input branches"}

private

Definition at line 154 of file FPGATrackSimLogicalHitsProcessAlg.h.

154{this, "writeInputBranches", true, "If set to false, never write input branches"};

◆ m_writeOutNonSPStripHits

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_writeOutNonSPStripHits {this, "writeOutNonSPStripHits", true, "Write tracks to RootOutput if they have strip hits which are not SPs"}

private

Definition at line 148 of file FPGATrackSimLogicalHitsProcessAlg.h.

148{this, "writeOutNonSPStripHits", true, "Write tracks to RootOutput if they have strip hits which are not SPs"};

◆ m_writeOutputData

Gaudi::Property<bool> FPGATrackSimLogicalHitsProcessAlg::m_writeOutputData {this, "writeOutputData", true,"write the output TTree"}

private

Definition at line 142 of file FPGATrackSimLogicalHitsProcessAlg.h.

142{this, "writeOutputData", true,"write the output TTree"};

◆ m_writeOutputTool

ToolHandle<FPGATrackSimOutputHeaderTool> FPGATrackSimLogicalHitsProcessAlg::m_writeOutputTool {this, "OutputTool", "FPGATrackSimOutputHeaderTool/FPGATrackSimOutputHeaderTool", "Output tool"}

private

Definition at line 94 of file FPGATrackSimLogicalHitsProcessAlg.h.

94{this, "OutputTool", "FPGATrackSimOutputHeaderTool/FPGATrackSimOutputHeaderTool", "Output tool"};

◆ m_writeRegion

Gaudi::Property<int> FPGATrackSimLogicalHitsProcessAlg::m_writeRegion {this,"writeRegion", -1, "Only output selected region, default is -1 which means not requirement"}

private

Definition at line 155 of file FPGATrackSimLogicalHitsProcessAlg.h.

155{this,"writeRegion", -1, "Only output selected region, default is -1 which means not requirement"};

The documentation for this class was generated from the following files:

Public Member Functions

Protected Member Functions

Private Types

Private Member Functions

Private Attributes

Detailed Description

Member Typedef Documentation

◆ StoreGateSvc_t

Constructor & Destructor Documentation

◆ FPGATrackSimLogicalHitsProcessAlg()

◆ ~FPGATrackSimLogicalHitsProcessAlg()

Member Function Documentation

◆ declareGaudiProperty()

◆ declareProperty()

◆ detStore()

◆ evtStore()

◆ execute()

◆ extraDeps_update_handler()

◆ extraOutputDeps()

◆ finalize()

◆ initialize()

◆ inputHandles()

◆ MakeSeedTracks()

◆ msg()

◆ msgLvl()

◆ outputHandles()

◆ passesChi2Cut()

◆ PickHitsToUse()

◆ printHitSubregions()

◆ renounce()

◆ renounceArray()

◆ sysInitialize()

◆ sysStart()

◆ updateVHKA()

◆ writeOutputData()

Member Data Documentation

◆ m_1st_stage_road_monitor

◆ m_1st_stage_road_post_filter_1_monitor

◆ m_1st_stage_road_post_filter_2_monitor

◆ m_1st_stage_road_post_OLR_monitor

◆ m_1st_stage_track_monitor

◆ m_1st_stage_track_post_chi2_monitor

◆ m_1st_stage_track_post_OLR_monitor

◆ m_1st_stage_track_post_setTruth_monitor

◆ m_chrono

◆ m_description

◆ m_detStore

◆ m_doGNNPixelSeeding

◆ m_doGNNTrack

◆ m_doHoughRootOutput1st

◆ m_doLRT

◆ m_doLRTHitFiltering

◆ m_doMissingHitsChecks

◆ m_doMultiTruth

◆ m_doNNTrack

◆ m_doOverlapRemoval

◆ m_doSpacepoints

◆ m_doTracking

◆ m_evt

◆ m_evt_truth

◆ m_evtSel

◆ m_evtStore

◆ m_extendedExtraObjects

◆ m_filterRoads

◆ m_filterRoads2

◆ m_FPGAEventInfoKey

◆ m_FPGAHitFilteredKey

◆ m_FPGAHitKey

◆ m_FPGAHitKey_1st

◆ m_FPGAHitKey_2nd

◆ m_FPGAOfflineTrackKey

◆ m_FPGARoadKey

◆ m_FPGASpacePointsKey

◆ m_FPGATrackKey

◆ m_FPGATrackSimMapping

◆ m_FPGATruthTrackKey

◆ m_houghRootOutputTool

◆ m_keepHitsStrategy

◆ m_logicEventOutputHeader

◆ m_LRTRoadFilterTool