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LVL1TGCTrigger::TGCSectorLogic Class Reference

#include <TGCSectorLogic.h>

Collaboration diagram for LVL1TGCTrigger::TGCSectorLogic:

Public Member Functions

 TGCSectorLogic (TGCArguments *, const TGCDatabaseManager *db, TGCRegionType regionIn, int id)
 
virtual ~TGCSectorLogic ()
 
 TGCSectorLogic (const TGCSectorLogic &right)
 
void getTrackSelectorOutput (std::shared_ptr< TGCTrackSelectorOut > &trackSelectorOut) const
 
int getTileMuonWord () const
 
int getInnerStationWord () const
 
void clockIn (const SG::ReadCondHandleKey< TGCTriggerData > &readCondKey, int bidIn, bool process=true)
 
int getId () const
 
int getModuleID () const
 
int getOctantID () const
 
int getSideID () const
 
TGCRegionType getRegion () const
 
void setWireHighPtBoard (int port, TGCHighPtBoard *highPtBoard)
 
void setStripHighPtBoard (TGCHighPtBoard *highPtBoard)
 
int getNumberOfWireHighPtBoard () const
 
void deleteHPBOut ()
 
TGCSSCController * getSSCController ()
 
void setTMDB (std::shared_ptr< const LVL1TGC::TGCTMDB > tmdb)
 
void setNSW (std::shared_ptr< const LVL1TGC::TGCNSW > nsw)
 
void setBIS78 (std::shared_ptr< const LVL1TGC::TGCBIS78 > bis78)
 
void showResult ()
 
int getNumberOfSubSectorCluster () const
 
int getNumberOfSubSector () const
 
void dec2bin (int dec, char *binstr, int length)
 
int getBid () const
 
void setInnerTrackletSlots (const TGCInnerTrackletSlot *innerTrackletSlots[])
 
TGCArguments * tgcArgs ()
 
const TGCArguments * tgcArgs () const
 

Protected Types

enum  { MaxNumberOfWireHighPtBoard =2 }
 

Protected Member Functions

void collectInput ()
 
void doInnerCoincidence (const SG::ReadCondHandleKey< TGCTriggerData > &readCondKey, int SSCId, TGCRPhiCoincidenceOut *coincidenceOut)
 
void doInnerCoincidence (int SSCId, TGCRPhiCoincidenceOut *coincidenceOut)
 
void doTGCNSWCoincidence (TGCRPhiCoincidenceOut *coincidenceOut)
 
bool doTGCBIS78Coincidence (TGCRPhiCoincidenceOut *coincidenceOut)
 
bool doTILECoincidence (TGCRPhiCoincidenceOut *coincidenceOut)
 
bool doTGCEICoincidence (TGCRPhiCoincidenceOut *coincidenceOut)
 
bool doTGCFICoincidence (TGCRPhiCoincidenceOut *coincidenceOut)
 

Private Member Functions

TGCSectorLogic & operator= (const TGCSectorLogic &right)
 
bool hitTileMu (const uint8_t &mask, const uint8_t &hit6, const uint8_t &hit56) const
 

Private Attributes

int m_bid
 
int m_id
 
LVL1TGC::TGCSide m_sideId
 
int m_sectorId
 
int m_moduleId
 
int m_octantId
 
TGCRegionType m_region
 
int m_NumberOfWireHighPtBoard
 
bool m_useEIFI {false}
 
bool m_useTileMu {false}
 
bool m_useGoodMF {false}
 
bool m_nswSide {false}
 
TGCSSCController m_SSCController
 
TGCRPhiCoincidenceMatrix m_matrix
 
const LVL1TGC::TGCEIFICoincidenceMap * m_mapEIFI
 
std::shared_ptr< const LVL1TGC::TGCTileMuCoincidenceLUT > m_tileMuLUT
 
std::shared_ptr< const LVL1TGC::TGCTMDB > m_pTMDB
 
std::shared_ptr< const LVL1TGC::TGCNSW > m_nsw
 
std::shared_ptr< const TGCNSWCoincidenceMap > m_mapNSW
 
std::shared_ptr< const LVL1TGC::TGCBIS78 > m_bis78
 
std::shared_ptr< const LVL1TGC::TGCBIS78CoincidenceMap > m_mapBIS78
 
std::shared_ptr< const LVL1TGC::TGCGoodMF > m_mapGoodMF
 
TGCTrackSelector m_trackSelector
 
std::shared_ptr< TGCTrackSelectorOut > m_trackSelectorOut
 
int m_wordTileMuon
 
int m_wordInnerStation
 
TGCHighPtBoard * m_wireHighPtBoard [MaxNumberOfWireHighPtBoard]
 
TGCHighPtChipOut * m_wireHighPtChipOut [MaxNumberOfWireHighPtBoard]
 
TGCHighPtBoard * m_stripHighPtBoard
 
TGCHighPtChipOut * m_stripHighPtChipOut
 
const TGCInnerTrackletSlot * m_innerTrackletSlots [TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR]
 
TGCArguments * m_tgcArgs
 

Detailed Description

Definition at line 41 of file TGCSectorLogic.h.

Member Enumeration Documentation

◆ anonymous enum

anonymous enum
protected
Enumerator
MaxNumberOfWireHighPtBoard 

Definition at line 89 of file TGCSectorLogic.h.

89 {MaxNumberOfWireHighPtBoard =2};

Constructor & Destructor Documentation

◆ TGCSectorLogic() [1/2]

LVL1TGCTrigger::TGCSectorLogic::TGCSectorLogic ( TGCArguments *  tgcargs,
const TGCDatabaseManager *  db,
TGCRegionType  regionIn,
int  id 
)

Definition at line 31 of file TGCSectorLogic.cxx.

33  : m_bid(0),
34  m_id(idIn),
35  m_region(regionIn),
36  m_NumberOfWireHighPtBoard(0),
37  m_SSCController(tgcargs,this),
38  m_matrix(tgcargs,this),
39  m_pTMDB(0),
40  m_trackSelector(this),
41  m_wordTileMuon(0),
42  m_wordInnerStation(0),
43  m_stripHighPtBoard(0),
44  m_stripHighPtChipOut(0),
45  m_tgcArgs(tgcargs)
46 {
47  m_sideId = static_cast<LVL1TGC::TGCSide>((idIn / NumberOfModule) / NumberOfOctant);
48  m_octantId = (idIn / NumberOfModule) % NumberOfOctant;
49  m_moduleId = idIn % NumberOfModule;
50 
51  if (m_region==TGCRegionType::ENDCAP) {
52  m_sectorId = m_moduleId%3 + 2*(m_moduleId/3);
53  m_sectorId += 6*m_octantId;
54  } else {
55  m_sectorId = m_moduleId/3;
56  m_sectorId += 3*m_octantId;
57  }
58 
59  m_nswSide = (tgcArgs()->NSWSideInfo().find('A')!=std::string::npos && m_sideId == LVL1TGC::TGCSide::ASIDE)
60  || (tgcArgs()->NSWSideInfo().find('C')!=std::string::npos && m_sideId == LVL1TGC::TGCSide::CSIDE);
61 
62  m_SSCController.setRegion(regionIn);
63 
64  m_matrix.setSideId(m_sideId);
65  m_mapEIFI = db->getEIFICoincidenceMap(m_sideId);
66 
67  m_useTileMu = tgcArgs()->TILE_MU() && (m_region==TGCRegionType::ENDCAP);
68 
69  m_matrix.setCoincidenceLUT(db->getBigWheelCoincidenceLUT());
70  m_tileMuLUT = db->getTileMuCoincidenceLUT();
71  m_useTileMu = (m_tileMuLUT != nullptr) && m_useTileMu;
72 
73  m_mapGoodMF = db->getGoodMFMap();
74  m_mapNSW = db->getNSWCoincidenceMap(m_sideId, m_octantId, m_moduleId);
75  if(tgcArgs()->USE_BIS78()) m_mapBIS78 = db->getBIS78CoincidenceMap();
76 
77  m_trackSelectorOut.reset(new TGCTrackSelectorOut());
78 
79  for(int i=0; i<MaxNumberOfWireHighPtBoard; i++){
80  m_wireHighPtBoard[i] = 0;
81  m_wireHighPtChipOut[i] = 0;
82  }
83 
84  for(unsigned int iSlot=0; iSlot<TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR; iSlot++) {
85  m_innerTrackletSlots[iSlot] = 0;
86  }
87 
88  m_useEIFI = tgcArgs()->USE_INNER() && (m_region==TGCRegionType::ENDCAP);
89  if(m_mapEIFI == 0) m_useEIFI = false;
90  m_useGoodMF = (m_mapGoodMF != nullptr);
91  if(m_mapNSW == 0) tgcArgs()->set_USE_NSW(false);
92  if(m_mapBIS78 == 0) tgcArgs()->set_USE_BIS78(false);
93 }

◆ ~TGCSectorLogic()

LVL1TGCTrigger::TGCSectorLogic::~TGCSectorLogic ( )
virtual

Definition at line 95 of file TGCSectorLogic.cxx.

96 {}

◆ TGCSectorLogic() [2/2]

LVL1TGCTrigger::TGCSectorLogic::TGCSectorLogic ( const TGCSectorLogic &  right)

Definition at line 246 of file TGCSectorLogic.cxx.

247  : m_bid(right.m_bid), m_id(right.m_id),
248  m_sideId(right.m_sideId),
249  m_sectorId(right.m_sectorId), m_moduleId(right.m_moduleId),
250  m_octantId(right.m_octantId),
251  m_region(right.m_region),
252  m_NumberOfWireHighPtBoard(right.m_NumberOfWireHighPtBoard),
253  m_useEIFI(right.m_useEIFI), m_useTileMu(right.m_useTileMu),
254  m_useGoodMF(right.m_useGoodMF), m_nswSide(right.m_nswSide),
255  m_SSCController(right.tgcArgs(),this),
256  m_matrix(right.tgcArgs(),this),
257  m_mapEIFI(right.m_mapEIFI),
258  m_pTMDB(right.m_pTMDB),
259  m_wordTileMuon(0), m_wordInnerStation(0),
260  m_stripHighPtBoard(right.m_stripHighPtBoard),
261  m_stripHighPtChipOut(0),
262  m_tgcArgs(right.m_tgcArgs)
263 {
264  for(int i=0; i<MaxNumberOfWireHighPtBoard; i++){
265  m_wireHighPtBoard[i] = 0;
266  m_wireHighPtChipOut[i] = 0;
267  }
268 
269  for( int i = 0; i < m_SSCController.getNumberOfWireHighPtBoard(); i += 1) {
270  m_wireHighPtBoard[i] = right.m_wireHighPtBoard[i];
271  m_wireHighPtChipOut[i] = right.m_wireHighPtChipOut[i];
272  }
273 
274  for (unsigned int iSlot=0; iSlot<TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR; iSlot++) {
275  m_innerTrackletSlots[iSlot] = right.m_innerTrackletSlots[iSlot];
276  }
277 }

Member Function Documentation

◆ clockIn()

void LVL1TGCTrigger::TGCSectorLogic::clockIn ( const SG::ReadCondHandleKey< TGCTriggerData > &  readCondKey,
int  bidIn,
bool  process = true 
)

Definition at line 132 of file TGCSectorLogic.cxx.

134 {
135  // skip to process if want. (e.g. no hit in TGC)
136  if(!process) return;
137 
138  m_bid=bidIn;
139 
140  collectInput();
141 
142  TGCSSCControllerOut* SSCCOut =
143  m_SSCController.distribute(m_wireHighPtChipOut,m_stripHighPtChipOut);
144 #ifdef TGCDEBUG
145  SSCCOut->print();
146 #endif
147  deleteHPBOut();
148 
149  for(int SSCid=0; SSCid<getNumberOfSubSectorCluster(); SSCid+=1){
150  TGCRPhiCoincidenceOut* coincidenceOut = 0;
151  if(SSCCOut->hasHit(SSCid)){
152  m_matrix.clear();
153  m_matrix.setSSCId(SSCid);
154  m_matrix.inputR(SSCCOut->getR(SSCid),SSCCOut->getDR(SSCid),SSCCOut->getPtR(SSCid));
155  for(int phiposInSSC = 0 ;phiposInSSC < TGCSSCControllerOut::MaxNumberOfPhiInSSC; phiposInSSC++){
156  if(SSCCOut->hasHit(SSCid, phiposInSSC)){
157  m_matrix.inputPhi(SSCCOut->getPhi(SSCid,phiposInSSC),
158  SSCCOut->getDPhi(SSCid,phiposInSSC),
159  SSCCOut->getPtPhi(SSCid,phiposInSSC));
160  }
161  }
162  coincidenceOut = m_matrix.doCoincidence();
163  }
165  if(SSCCOut->hasHit(SSCid,true)){
166  m_matrix.clear();
167  m_matrix.setSSCId(SSCid);
168  m_matrix.inputR(SSCCOut->getR(SSCid),SSCCOut->getDR(SSCid),SSCCOut->getPtR(SSCid));
169  for(int phiposInSSC = 0 ;phiposInSSC < TGCSSCControllerOut::MaxNumberOfPhiInSSC; phiposInSSC++){
170  if(SSCCOut->hasHit(SSCid, phiposInSSC, true)){
171  m_matrix.inputPhi(SSCCOut->getPhi(SSCid,phiposInSSC,true),
172  SSCCOut->getDPhi(SSCid,phiposInSSC,true),
173  SSCCOut->getPtPhi(SSCid,phiposInSSC,true));
174  }
175  }
176 
177  TGCRPhiCoincidenceOut* oredCoincidenceOut = m_matrix.doCoincidence();
178  if (oredCoincidenceOut) {
179  if(coincidenceOut) {
180  if (coincidenceOut->isSuperior(oredCoincidenceOut)) {
181  delete oredCoincidenceOut;
182  } else {
183  delete coincidenceOut;
184  coincidenceOut = oredCoincidenceOut;
185  }
186  } else {
187  coincidenceOut = oredCoincidenceOut;
188  }
189  }
190  }
191 
192  if (coincidenceOut) {
193  if (m_useGoodMF) {
194  bool isgoodMF = m_mapGoodMF->test_GoodMF(m_moduleId,SSCid,coincidenceOut->getRoI());
195  coincidenceOut->setGoodMFFlag(isgoodMF);
196  }
197  }
198 
200  // do coincidence with Inner Tracklet of EI, NSW, Tile, and/or RPC-BIS78
201  doInnerCoincidence(SSCid, coincidenceOut);
202 
203  if (coincidenceOut) {
204  m_trackSelector.input(coincidenceOut);
205  }
206  }
207  if(SSCCOut!=0) delete SSCCOut;
208  SSCCOut=0;
209 
210  // Track selector chooses up to 4 track candidates to be sent to MUCTPI.
211  m_trackSelector.select(m_trackSelectorOut);
212 }

◆ collectInput()

void LVL1TGCTrigger::TGCSectorLogic::collectInput ( )
protected

Definition at line 214 of file TGCSectorLogic.cxx.

215 {
216  for(int i = 0; i < m_SSCController.getNumberOfWireHighPtBoard(); i += 1) {
217  m_wireHighPtChipOut[i] = m_wireHighPtBoard[i]->getOutput();
218  m_wireHighPtBoard[i]->eraseOutput();
219  }
220 
221  m_stripHighPtChipOut = m_stripHighPtBoard->getOutput();
222  m_stripHighPtBoard->eraseOutput();
223 }

◆ dec2bin()

void LVL1TGCTrigger::TGCSectorLogic::dec2bin ( int  dec,
char *  binstr,
int  length 
)

Definition at line 313 of file TGCSectorLogic.cxx.

314 {
315  for (int i=0; i<length; i++){
316  if((dec>>i) & 1)
317  binstr[length-1-i] = '1';
318  else
319  binstr[length-1-i] = '0';
320  }
321  binstr[length] ='\0';
322 }

◆ deleteHPBOut()

void LVL1TGCTrigger::TGCSectorLogic::deleteHPBOut ( )

Definition at line 225 of file TGCSectorLogic.cxx.

226 {
227  if(m_stripHighPtChipOut!=0) delete m_stripHighPtChipOut;
228  m_stripHighPtChipOut=0;
229 
230  int i;
231  for( i = 0; i < m_SSCController.getNumberOfWireHighPtBoard(); i += 1) {
232  if(m_wireHighPtChipOut[i]!=0) delete m_wireHighPtChipOut[i];
233  m_wireHighPtChipOut[i]=0;
234  }
235 }

◆ doInnerCoincidence() [1/2]

void LVL1TGCTrigger::TGCSectorLogic::doInnerCoincidence ( const SG::ReadCondHandleKey< TGCTriggerData > &  readCondKey,
int  SSCId,
TGCRPhiCoincidenceOut *  coincidenceOut 
)
protected

◆ doInnerCoincidence() [2/2]

void LVL1TGCTrigger::TGCSectorLogic::doInnerCoincidence ( int  SSCId,
TGCRPhiCoincidenceOut *  coincidenceOut 
)
protected

Definition at line 332 of file TGCSectorLogic.cxx.

332  {
333  if (coincidenceOut == 0) return;
334 
335  int pt = coincidenceOut->getpT();
336  if (pt==0) return;
337 
338  if(SSCId <= 4 && m_region == TGCRegionType::ENDCAP){ //3 detectors are used to inner coincidnece in SSC#0~4 in Endcap;
339 
340  // WHICH INNER COINCIDENCE
341  // select a inner station detector which is used in inner coincidence algorithm.
342  //Defenation of innerDetectorNumber :: enum{EI=0,TILE,BIS78};
343 
344  /*int innerDetectorNumber = which_InnerCoincidence();*/ //this function will be implemented.
345 
346  // The below section is a tmporary method. It will be replaced with WICHINNER COINCIDENCE.
347  int pos = 4*coincidenceOut->getR() + coincidenceOut->getPhi();
348  // check if inner is used for the roi
349  bool validEI = (m_mapEIFI->getFlagROI(pos, coincidenceOut->getIdSSC(), m_sectorId) == 1);
350  // check if TileMu is used for the roi
351  bool validTileMu = (m_tileMuLUT->getFlagROI(pos, coincidenceOut->getIdSSC(), m_sectorId, m_sideId) == 1);
352  bool validBIS78 = false;
353  if(tgcArgs()->USE_BIS78()) validBIS78=(m_mapBIS78->getFlagROI(pos, coincidenceOut->getIdSSC(), m_sectorId, m_sideId) == 1);
354 
355  bool isEI=false;
356  bool isTILE=false;
357  bool isBIS78=false;
358  if(m_useEIFI && validEI){isEI=doTGCEICoincidence(coincidenceOut);}
359  if(m_useTileMu && validTileMu){isTILE=doTILECoincidence(coincidenceOut); }
360  if(validBIS78){isBIS78=doTGCBIS78Coincidence(coincidenceOut); }
361 
362  coincidenceOut->setInnerCoincidenceFlag(isEI || isTILE || isBIS78 || (!m_useEIFI && !validEI && !m_useTileMu && !validTileMu && !tgcArgs()->USE_BIS78() && !validBIS78));
363  } else {
364  // NSW or FI are used to inner coincidnece in SSC#5~18 in Endcap and Forward region
365  int pos = 4*coincidenceOut->getR() + coincidenceOut->getPhi();
366  bool validFI = (m_mapEIFI->getFlagROI(pos, coincidenceOut->getIdSSC(), m_sectorId) == 1) && m_region == TGCRegionType::ENDCAP;
367 
368  if(tgcArgs()->USE_NSW() && m_nswSide){
369  if(tgcArgs()->FORCE_NSW_COIN()){
370  coincidenceOut->setInnerCoincidenceFlag(true);
371  }
372  else{
373  doTGCNSWCoincidence(coincidenceOut);
374  }
375  }
376  else if(!m_nswSide && validFI){
377  if(m_useEIFI){
378  coincidenceOut->setInnerCoincidenceFlag( doTGCFICoincidence(coincidenceOut) );
379  }
380  } else {
381  coincidenceOut->setInnerCoincidenceFlag(true); // TBD
382  }
383  }
384 }

◆ doTGCBIS78Coincidence()

bool LVL1TGCTrigger::TGCSectorLogic::doTGCBIS78Coincidence ( TGCRPhiCoincidenceOut *  coincidenceOut)
protected

Definition at line 397 of file TGCSectorLogic.cxx.

397  {
398  std::shared_ptr<const LVL1TGC::BIS78TrigOut> pBIS78Out = m_bis78->getOutput(m_sectorId);
399  if ( pBIS78Out.get() == 0 ) return false;
400  int pt=0;
401 
402  pt = m_mapBIS78->TGCBIS78_pt(pBIS78Out.get(),
403  coincidenceOut->getRoI());
404 
405  return (pt > 0);
406 }

◆ doTGCEICoincidence()

bool LVL1TGCTrigger::TGCSectorLogic::doTGCEICoincidence ( TGCRPhiCoincidenceOut *  coincidenceOut)
protected

Definition at line 426 of file TGCSectorLogic.cxx.

426  {
427 
428  bool isHitInner=false;
429  for(unsigned int iSlot=0;iSlot<TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR; iSlot++) {
430  const TGCInnerTrackletSlot* hit = m_innerTrackletSlots[iSlot];
431 
432  for (size_t reg=0;reg< TGCInnerTrackletSlot::NUMBER_OF_REGIONS; reg++){
433 
434  // Wire
435  bool isHitWire = false;
436  for (size_t bit=0; bit< TGCInnerTrackletSlot::NUMBER_OF_TRIGGER_BITS; bit++){
437  isHitWire = m_mapEIFI->getTriggerBit(iSlot, coincidenceOut->getIdSSC(), m_sectorId, reg, TGCInnerTrackletSlot::WIRE, bit)
438  && hit->getTriggerBit(reg,TGCInnerTrackletSlot::WIRE,bit) ;
439  if(isHitWire){break;}
440  }
441 
442  // Strip
443  bool isHitStrip = false;
444  for (size_t bit=0;bit< TGCInnerTrackletSlot::NUMBER_OF_TRIGGER_BITS; bit++){
445  isHitStrip = m_mapEIFI->getTriggerBit(iSlot, coincidenceOut->getIdSSC(), m_sectorId, reg, TGCInnerTrackletSlot::STRIP, bit)
446  && hit->getTriggerBit(reg,TGCInnerTrackletSlot::STRIP,bit);
447  if(isHitStrip){break;}
448  }
449 
450  isHitInner = isHitWire && isHitStrip;
451  if(isHitInner){
452  return true;
453  }
454  }
455 
456  }
457 
458  return false;
459 }

◆ doTGCFICoincidence()

bool LVL1TGCTrigger::TGCSectorLogic::doTGCFICoincidence ( TGCRPhiCoincidenceOut *  coincidenceOut)
protected

Definition at line 462 of file TGCSectorLogic.cxx.

462  {
463  return doTGCEICoincidence(coincidenceOut);
464 }

◆ doTGCNSWCoincidence()

void LVL1TGCTrigger::TGCSectorLogic::doTGCNSWCoincidence ( TGCRPhiCoincidenceOut *  coincidenceOut)
protected

Definition at line 387 of file TGCSectorLogic.cxx.

387  {
388  std::shared_ptr<const LVL1TGC::NSWTrigOut> pNSWOut = m_nsw->getOutput(m_region,m_sideId,m_sectorId);
389 
390  // for now, if there is a hit at NSW and the side is included in the detector mask, turn on the inner coin flag
391  coincidenceOut->setInnerCoincidenceFlag( pNSWOut->getNSWeta().size()>0 && m_nswSide);
392  return;
393 
394  // will implement NSW pT calculation later
395 }

◆ doTILECoincidence()

bool LVL1TGCTrigger::TGCSectorLogic::doTILECoincidence ( TGCRPhiCoincidenceOut *  coincidenceOut)
protected

Definition at line 408 of file TGCSectorLogic.cxx.

409 {
411  // The function is called for Run-3 algorithim, but the Run-2 algorithm is
412  // temporarily used for instance.
414 
415  bool isHitTileMu=false;
416  for(int mod=0; mod < LVL1TGC::TGCTileMuCoincidenceLUT::N_Input_TileMuModule; mod++) {
417  uint8_t maskTM = (uint8_t)(m_tileMuLUT->getTrigMask(mod, coincidenceOut->getIdSSC(), m_sectorId, m_sideId));
418  std::shared_ptr<const LVL1TGC::TGCTMDBOut> tm = m_pTMDB->getOutput(m_sideId, m_sectorId, mod);
419  isHitTileMu = isHitTileMu || this->hitTileMu(maskTM, tm->getHit6(), tm->getHit56());
420  }
421 
422  return isHitTileMu;
423 }

◆ getBid()

int LVL1TGCTrigger::TGCSectorLogic::getBid ( ) const
inline

Definition at line 81 of file TGCSectorLogic.h.

81 {return m_bid;};

◆ getId()

int LVL1TGCTrigger::TGCSectorLogic::getId ( ) const
inline

Definition at line 172 of file TGCSectorLogic.h.

173 {
174  return m_id;
175 }

◆ getInnerStationWord()

int LVL1TGCTrigger::TGCSectorLogic::getInnerStationWord ( ) const
inline

Definition at line 203 of file TGCSectorLogic.h.

204 {
205  return m_wordInnerStation;
206 }

◆ getModuleID()

int LVL1TGCTrigger::TGCSectorLogic::getModuleID ( ) const
inline

Definition at line 178 of file TGCSectorLogic.h.

179 {
180  return m_moduleId;
181 }

◆ getNumberOfSubSector()

int LVL1TGCTrigger::TGCSectorLogic::getNumberOfSubSector ( ) const
inline

Definition at line 159 of file TGCSectorLogic.h.

160 {
161  return (m_region == TGCRegionType::FORWARD) ? 8 * LVL1TGC::kNRoiInSSC : LVL1TGC::kNumberOfEndcapRoI;
162 }

◆ getNumberOfSubSectorCluster()

int LVL1TGCTrigger::TGCSectorLogic::getNumberOfSubSectorCluster ( ) const
inline

Definition at line 153 of file TGCSectorLogic.h.

154 {
155  return (m_region == TGCRegionType::FORWARD) ? 8 : LVL1TGC::kNMaxSSC;
156 }

◆ getNumberOfWireHighPtBoard()

int LVL1TGCTrigger::TGCSectorLogic::getNumberOfWireHighPtBoard ( ) const
inline

Definition at line 165 of file TGCSectorLogic.h.

166 {
167  return m_NumberOfWireHighPtBoard;
168 }

◆ getOctantID()

int LVL1TGCTrigger::TGCSectorLogic::getOctantID ( ) const
inline

Definition at line 185 of file TGCSectorLogic.h.

186 {
187  return m_octantId;
188 }

◆ getRegion()

TGCRegionType LVL1TGCTrigger::TGCSectorLogic::getRegion ( ) const
inline

Definition at line 62 of file TGCSectorLogic.h.

62 { return m_region;};

◆ getSideID()

int LVL1TGCTrigger::TGCSectorLogic::getSideID ( ) const
inline

Definition at line 191 of file TGCSectorLogic.h.

192 {
193  return m_sideId;
194 }

◆ getSSCController()

TGCSSCController* LVL1TGCTrigger::TGCSectorLogic::getSSCController ( )
inline

Definition at line 69 of file TGCSectorLogic.h.

69 {return &m_SSCController;};

◆ getTileMuonWord()

int LVL1TGCTrigger::TGCSectorLogic::getTileMuonWord ( ) const
inline

Definition at line 197 of file TGCSectorLogic.h.

198 {
199  return m_wordTileMuon;
200 }

◆ getTrackSelectorOutput()

void LVL1TGCTrigger::TGCSectorLogic::getTrackSelectorOutput ( std::shared_ptr< TGCTrackSelectorOut > &  trackSelectorOut) const

Definition at line 127 of file TGCSectorLogic.cxx.

128 {
129  trackSelectorOut=m_trackSelectorOut;
130 }

◆ hitTileMu()

bool LVL1TGCTrigger::TGCSectorLogic::hitTileMu ( const uint8_t &  mask,
const uint8_t &  hit6,
const uint8_t &  hit56 
) const
private

returns whether TMDBOut satisfies the Tile-CW mask (Run-2 algo.)

Parameters
[in]maskTrigger mask per TMDB module (3 bits)
[in]hit6TMDBOut for D6
[in]hit56TMDBOut for D5+D6

Definition at line 467 of file TGCSectorLogic.cxx.

468 {
474  switch(mask) {
475  case LVL1TGC::TGCTileMuCoincidenceLUT::TM_D6_L:
476  return (hit6==LVL1TGC::TGCTMDBOut::TM_LOW || hit6==LVL1TGC::TGCTMDBOut::TM_HIGH);
477  break;
478  case LVL1TGC::TGCTileMuCoincidenceLUT::TM_D6_H:
479  return (hit6==LVL1TGC::TGCTMDBOut::TM_HIGH);
480  break;
481  case LVL1TGC::TGCTileMuCoincidenceLUT::TM_D56_L:
482  return (hit56==LVL1TGC::TGCTMDBOut::TM_LOW || hit56==LVL1TGC::TGCTMDBOut::TM_HIGH);
483  break;
484  case LVL1TGC::TGCTileMuCoincidenceLUT::TM_D56_H:
485  return (hit56==LVL1TGC::TGCTMDBOut::TM_HIGH);
486  break;
487  default:
488  return false;
489  break;
490  }
491  return true;
492 }

◆ operator=()

TGCSectorLogic & LVL1TGCTrigger::TGCSectorLogic::operator= ( const TGCSectorLogic &  right)
private

Definition at line 280 of file TGCSectorLogic.cxx.

281 {
282  if ( this != &right ) {
283  m_tgcArgs = right.m_tgcArgs;
284  m_matrix = right.m_matrix;
285  m_bid =right.m_bid;
286  m_id =right.m_id;
287  m_sideId = right.m_sideId;
288  m_sectorId=right.m_sectorId;
289  m_moduleId=right.m_moduleId;
290  m_octantId=right.m_octantId;
291  m_region=right.m_region;
292  m_NumberOfWireHighPtBoard=right.m_NumberOfWireHighPtBoard;
293  m_mapEIFI=right.m_mapEIFI;
294  m_pTMDB=right.m_pTMDB;
295  m_wordTileMuon=0;
296  m_wordInnerStation=0;
297  m_stripHighPtBoard=right.m_stripHighPtBoard;
298  m_stripHighPtChipOut=0;
299  m_useEIFI=right.m_useEIFI;
300  m_useTileMu=right.m_useTileMu;
301  for( int i = 0; i < m_SSCController.getNumberOfWireHighPtBoard(); i += 1) {
302  m_wireHighPtBoard[i] = right.m_wireHighPtBoard[i];
303  m_wireHighPtChipOut[i] = right.m_wireHighPtChipOut[i];
304  }
305  for (unsigned int iSlot=0; iSlot<TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR; iSlot++) {
306  m_innerTrackletSlots[iSlot] = right.m_innerTrackletSlots[iSlot];
307  }
308  }
309  return *this;
310 }

◆ setBIS78()

void LVL1TGCTrigger::TGCSectorLogic::setBIS78 ( std::shared_ptr< const LVL1TGC::TGCBIS78 >  bis78)

Definition at line 110 of file TGCSectorLogic.cxx.

111 {
112  m_bis78 = bis78;
113  if(m_bis78 == 0) tgcArgs()->set_USE_BIS78(false);
114 }

◆ setInnerTrackletSlots()

void LVL1TGCTrigger::TGCSectorLogic::setInnerTrackletSlots ( const TGCInnerTrackletSlot *  innerTrackletSlots[])

Definition at line 324 of file TGCSectorLogic.cxx.

325 {
326  for(unsigned int iSlot=0; iSlot<TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR; iSlot++) {
327  m_innerTrackletSlots[iSlot] = innerTrackletSlots[iSlot];
328  }
329 }

◆ setNSW()

void LVL1TGCTrigger::TGCSectorLogic::setNSW ( std::shared_ptr< const LVL1TGC::TGCNSW >  nsw)

Definition at line 104 of file TGCSectorLogic.cxx.

105 {
106  m_nsw = nsw;
107  if(m_nsw == 0) tgcArgs()->set_USE_NSW(false);
108 }

◆ setStripHighPtBoard()

void LVL1TGCTrigger::TGCSectorLogic::setStripHighPtBoard ( TGCHighPtBoard *  highPtBoard)

Definition at line 122 of file TGCSectorLogic.cxx.

123 {
124  m_stripHighPtBoard = highPtBoard;
125 }

◆ setTMDB()

void LVL1TGCTrigger::TGCSectorLogic::setTMDB ( std::shared_ptr< const LVL1TGC::TGCTMDB >  tmdb)

Definition at line 98 of file TGCSectorLogic.cxx.

99 {
100  m_pTMDB = tmdb;
101  if (m_pTMDB==0) m_useTileMu = false;
102 }

◆ setWireHighPtBoard()

void LVL1TGCTrigger::TGCSectorLogic::setWireHighPtBoard ( int  port,
TGCHighPtBoard *  highPtBoard 
)

Definition at line 116 of file TGCSectorLogic.cxx.

117 {
118  m_wireHighPtBoard[port] = highPtBoard;
119  m_NumberOfWireHighPtBoard +=1;
120 }

◆ showResult()

void LVL1TGCTrigger::TGCSectorLogic::showResult ( )

Definition at line 238 of file TGCSectorLogic.cxx.

239 {
240  std::cout<<"#SL O"<<" BID:"<<m_bid
241  <<" region:"<<((m_region == TGCRegionType::FORWARD) ? "FWD" : "END")
242  <<" SLid:"<<m_id<<" ";
243 }

◆ tgcArgs() [1/2]

TGCArguments* LVL1TGCTrigger::TGCSectorLogic::tgcArgs ( )
inline

Definition at line 85 of file TGCSectorLogic.h.

85 { return m_tgcArgs; }

◆ tgcArgs() [2/2]

const TGCArguments* LVL1TGCTrigger::TGCSectorLogic::tgcArgs ( ) const
inline

Definition at line 86 of file TGCSectorLogic.h.

86 { return m_tgcArgs; }

Member Data Documentation

◆ m_bid

int LVL1TGCTrigger::TGCSectorLogic::m_bid
private

Definition at line 109 of file TGCSectorLogic.h.

◆ m_bis78

std::shared_ptr<const LVL1TGC::TGCBIS78> LVL1TGCTrigger::TGCSectorLogic::m_bis78
private

Definition at line 132 of file TGCSectorLogic.h.

◆ m_id

int LVL1TGCTrigger::TGCSectorLogic::m_id
private

Definition at line 111 of file TGCSectorLogic.h.

◆ m_innerTrackletSlots

const TGCInnerTrackletSlot* LVL1TGCTrigger::TGCSectorLogic::m_innerTrackletSlots[TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR]
private

Definition at line 148 of file TGCSectorLogic.h.

◆ m_mapBIS78

std::shared_ptr<const LVL1TGC::TGCBIS78CoincidenceMap> LVL1TGCTrigger::TGCSectorLogic::m_mapBIS78
private

Definition at line 133 of file TGCSectorLogic.h.

◆ m_mapEIFI

const LVL1TGC::TGCEIFICoincidenceMap* LVL1TGCTrigger::TGCSectorLogic::m_mapEIFI
private

Definition at line 127 of file TGCSectorLogic.h.

◆ m_mapGoodMF

std::shared_ptr<const LVL1TGC::TGCGoodMF> LVL1TGCTrigger::TGCSectorLogic::m_mapGoodMF
private

Definition at line 134 of file TGCSectorLogic.h.

◆ m_mapNSW

std::shared_ptr<const TGCNSWCoincidenceMap> LVL1TGCTrigger::TGCSectorLogic::m_mapNSW
private

Definition at line 131 of file TGCSectorLogic.h.

◆ m_matrix

TGCRPhiCoincidenceMatrix LVL1TGCTrigger::TGCSectorLogic::m_matrix
private

Definition at line 126 of file TGCSectorLogic.h.

◆ m_moduleId

int LVL1TGCTrigger::TGCSectorLogic::m_moduleId
private

Definition at line 113 of file TGCSectorLogic.h.

◆ m_nsw

std::shared_ptr<const LVL1TGC::TGCNSW> LVL1TGCTrigger::TGCSectorLogic::m_nsw
private

Definition at line 130 of file TGCSectorLogic.h.

◆ m_nswSide

bool LVL1TGCTrigger::TGCSectorLogic::m_nswSide {false}
private

Definition at line 121 of file TGCSectorLogic.h.

◆ m_NumberOfWireHighPtBoard

int LVL1TGCTrigger::TGCSectorLogic::m_NumberOfWireHighPtBoard
private

Definition at line 116 of file TGCSectorLogic.h.

◆ m_octantId

int LVL1TGCTrigger::TGCSectorLogic::m_octantId
private

Definition at line 114 of file TGCSectorLogic.h.

◆ m_pTMDB

std::shared_ptr<const LVL1TGC::TGCTMDB> LVL1TGCTrigger::TGCSectorLogic::m_pTMDB
private

Definition at line 129 of file TGCSectorLogic.h.

◆ m_region

TGCRegionType LVL1TGCTrigger::TGCSectorLogic::m_region
private

Definition at line 115 of file TGCSectorLogic.h.

◆ m_sectorId

int LVL1TGCTrigger::TGCSectorLogic::m_sectorId
private

Definition at line 113 of file TGCSectorLogic.h.

◆ m_sideId

LVL1TGC::TGCSide LVL1TGCTrigger::TGCSectorLogic::m_sideId
private

Definition at line 112 of file TGCSectorLogic.h.

◆ m_SSCController

TGCSSCController LVL1TGCTrigger::TGCSectorLogic::m_SSCController
private

Definition at line 123 of file TGCSectorLogic.h.

◆ m_stripHighPtBoard

TGCHighPtBoard* LVL1TGCTrigger::TGCSectorLogic::m_stripHighPtBoard
private

Definition at line 144 of file TGCSectorLogic.h.

◆ m_stripHighPtChipOut

TGCHighPtChipOut* LVL1TGCTrigger::TGCSectorLogic::m_stripHighPtChipOut
private

Definition at line 145 of file TGCSectorLogic.h.

◆ m_tgcArgs

TGCArguments* LVL1TGCTrigger::TGCSectorLogic::m_tgcArgs
private

Definition at line 149 of file TGCSectorLogic.h.

◆ m_tileMuLUT

std::shared_ptr<const LVL1TGC::TGCTileMuCoincidenceLUT> LVL1TGCTrigger::TGCSectorLogic::m_tileMuLUT
private

Definition at line 128 of file TGCSectorLogic.h.

◆ m_trackSelector

TGCTrackSelector LVL1TGCTrigger::TGCSectorLogic::m_trackSelector
private

Definition at line 136 of file TGCSectorLogic.h.

◆ m_trackSelectorOut

std::shared_ptr<TGCTrackSelectorOut> LVL1TGCTrigger::TGCSectorLogic::m_trackSelectorOut
private

Definition at line 137 of file TGCSectorLogic.h.

◆ m_useEIFI

bool LVL1TGCTrigger::TGCSectorLogic::m_useEIFI {false}
private

Definition at line 118 of file TGCSectorLogic.h.

◆ m_useGoodMF

bool LVL1TGCTrigger::TGCSectorLogic::m_useGoodMF {false}
private

Definition at line 120 of file TGCSectorLogic.h.

◆ m_useTileMu

bool LVL1TGCTrigger::TGCSectorLogic::m_useTileMu {false}
private

Definition at line 119 of file TGCSectorLogic.h.

◆ m_wireHighPtBoard

TGCHighPtBoard* LVL1TGCTrigger::TGCSectorLogic::m_wireHighPtBoard[MaxNumberOfWireHighPtBoard]
private

Definition at line 142 of file TGCSectorLogic.h.

◆ m_wireHighPtChipOut

TGCHighPtChipOut* LVL1TGCTrigger::TGCSectorLogic::m_wireHighPtChipOut[MaxNumberOfWireHighPtBoard]
private

Definition at line 143 of file TGCSectorLogic.h.

◆ m_wordInnerStation

int LVL1TGCTrigger::TGCSectorLogic::m_wordInnerStation
private

Definition at line 140 of file TGCSectorLogic.h.

◆ m_wordTileMuon

int LVL1TGCTrigger::TGCSectorLogic::m_wordTileMuon
private

Definition at line 139 of file TGCSectorLogic.h.

The documentation for this class was generated from the following files:
LVL1TGCTrigger::TGCSSCController::distribute
TGCSSCControllerOut * distribute(TGCHighPtChipOut *wire[], TGCHighPtChipOut *strip)
Definition: TGCSSCController.cxx:21
LVL1TGCTrigger::TGCHighPtBoard::eraseOutput
void eraseOutput()
Definition: TGCHighPtBoard.cxx:149
LVL1TGCTrigger::TGCRegionType::ENDCAP
@ ENDCAP
LVL1TGCTrigger::TGCSectorLogic::tgcArgs
TGCArguments * tgcArgs()
Definition: TGCSectorLogic.h:85
LVL1TGCTrigger::TGCSectorLogic::m_innerTrackletSlots
const TGCInnerTrackletSlot * m_innerTrackletSlots[TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR]
Definition: TGCSectorLogic.h:148
LVL1TGC::CSIDE
@ CSIDE
Definition: TGCNumbering.h:15
LVL1TGCTrigger::TGCRPhiCoincidenceMatrix::inputR
void inputR(int rIn, int dRIn, int ptRIn)
Definition: TGCRPhiCoincidenceMatrix.cxx:21
LVL1TGCTrigger::TGCSSCControllerOut::print
void print() const
Definition: TGCSSCControllerOut.cxx:61
LVL1TGCTrigger::TGCArguments::TILE_MU
bool TILE_MU() const
Definition: TGCArguments.cxx:44
LVL1TGCTrigger::TGCTrackSelector::select
bool select(std::shared_ptr< TGCTrackSelectorOut > TrackcandidateOut)
Definition: TGCTrackSelector.cxx:48
LVL1TGCTrigger::TGCSectorLogic::m_useTileMu
bool m_useTileMu
Definition: TGCSectorLogic.h:119
xAOD::uint8_t
uint8_t
Definition: Muon_v1.cxx:575
LVL1TGCTrigger::TGCSectorLogic::MaxNumberOfWireHighPtBoard
@ MaxNumberOfWireHighPtBoard
Definition: TGCSectorLogic.h:89
LVL1TGCTrigger::TGCSectorLogic::m_mapNSW
std::shared_ptr< const TGCNSWCoincidenceMap > m_mapNSW
Definition: TGCSectorLogic.h:131
LVL1TGC::TGCTileMuCoincidenceLUT::TM_D56_L
@ TM_D56_L
Definition: TGCTileMuCoincidenceLUT.h:85
LVL1TGCTrigger::TGCInnerTrackletSlot::NUMBER_OF_REGIONS
@ NUMBER_OF_REGIONS
Definition: TGCInnerTrackletSlot.h:35
LVL1TGCTrigger::TGCSectorLogic::m_nsw
std::shared_ptr< const LVL1TGC::TGCNSW > m_nsw
Definition: TGCSectorLogic.h:130
CaloCondBlobAlgs_fillNoiseFromASCII.db
db
Definition: CaloCondBlobAlgs_fillNoiseFromASCII.py:43
LVL1TGCTrigger::TGCSectorLogic::m_trackSelectorOut
std::shared_ptr< TGCTrackSelectorOut > m_trackSelectorOut
Definition: TGCSectorLogic.h:137
LVL1TGCTrigger::TGCSectorLogic::m_wordInnerStation
int m_wordInnerStation
Definition: TGCSectorLogic.h:140
test_pyathena.pt
pt
Definition: test_pyathena.py:11
RunTileCalibRec.tmdb
tmdb
Definition: RunTileCalibRec.py:234
LVL1TGCTrigger::TGCSectorLogic::m_id
int m_id
Definition: TGCSectorLogic.h:111
LVL1TGCTrigger::TGCSectorLogic::m_NumberOfWireHighPtBoard
int m_NumberOfWireHighPtBoard
Definition: TGCSectorLogic.h:116
LVL1TGCTrigger::TGCSectorLogic::collectInput
void collectInput()
Definition: TGCSectorLogic.cxx:214
LVL1TGCTrigger::TGCSectorLogic::doInnerCoincidence
void doInnerCoincidence(const SG::ReadCondHandleKey< TGCTriggerData > &readCondKey, int SSCId, TGCRPhiCoincidenceOut *coincidenceOut)
LVL1TGCTrigger::TGCArguments::USE_INNER
bool USE_INNER() const
Definition: TGCArguments.cxx:42
LVL1TGCTrigger::TGCRegionType::FORWARD
@ FORWARD
LVL1TGCTrigger::TGCSectorLogic::m_bis78
std::shared_ptr< const LVL1TGC::TGCBIS78 > m_bis78
Definition: TGCSectorLogic.h:132
LVL1TGCTrigger::TGCSectorLogic::m_sideId
LVL1TGC::TGCSide m_sideId
Definition: TGCSectorLogic.h:112
python.DomainsRegistry.reg
reg
globals -----------------------------------------------------------------—
Definition: DomainsRegistry.py:343
LVL1TGCTrigger::TGCInnerTrackletSlot::WIRE
@ WIRE
Definition: TGCInnerTrackletSlot.h:36
LVL1TGCTrigger::TGCSectorLogic::doTILECoincidence
bool doTILECoincidence(TGCRPhiCoincidenceOut *coincidenceOut)
Definition: TGCSectorLogic.cxx:408
LVL1TGCTrigger::TGCSectorLogic::m_SSCController
TGCSSCController m_SSCController
Definition: TGCSectorLogic.h:123
SUSY_SimplifiedModel_PostInclude.process
string process
Definition: SUSY_SimplifiedModel_PostInclude.py:42
LVL1TGCTrigger::TGCSectorLogic::doTGCBIS78Coincidence
bool doTGCBIS78Coincidence(TGCRPhiCoincidenceOut *coincidenceOut)
Definition: TGCSectorLogic.cxx:397
python.utils.AtlRunQueryLookup.mask
string mask
Definition: AtlRunQueryLookup.py:460
LVL1TGC::TGCTileMuCoincidenceLUT::TM_D6_L
@ TM_D6_L
Definition: TGCTileMuCoincidenceLUT.h:83
LVL1TGCTrigger::TGCSectorLogic::m_stripHighPtBoard
TGCHighPtBoard * m_stripHighPtBoard
Definition: TGCSectorLogic.h:144
LVL1TGCTrigger::TGCSectorLogic::m_matrix
TGCRPhiCoincidenceMatrix m_matrix
Definition: TGCSectorLogic.h:126
LVL1TGCTrigger::TGCSectorLogic::m_bid
int m_bid
Definition: TGCSectorLogic.h:109
LVL1TGC::NSWTrigOut::getNSWeta
const std::vector< uint8_t > & getNSWeta() const
Definition: NSWTrigOut.h:66
LVL1TGCTrigger::TGCSectorLogic::m_sectorId
int m_sectorId
Definition: TGCSectorLogic.h:113
LVL1TGCTrigger::TGCArguments::set_USE_BIS78
void set_USE_BIS78(bool v)
Definition: TGCArguments.cxx:38
LVL1TGCTrigger::TGCSectorLogic::m_octantId
int m_octantId
Definition: TGCSectorLogic.h:114
LVL1TGCTrigger::TGCSSCControllerOut::MaxNumberOfPhiInSSC
@ MaxNumberOfPhiInSSC
Definition: TGCSSCControllerOut.h:15
LVL1TGCTrigger::TGCSectorLogic::m_nswSide
bool m_nswSide
Definition: TGCSectorLogic.h:121
LVL1TGCTrigger::NumberOfOctant
const int NumberOfOctant
Definition: TGCElectronicsSystem.h:19
LVL1TGC::TGCTMDBOut::TM_HIGH
@ TM_HIGH
Definition: TGCTMDBOut.h:13
maskDeadModules.mod
mod
Definition: maskDeadModules.py:36
LVL1TGCTrigger::TGCArguments::FORCE_NSW_COIN
bool FORCE_NSW_COIN() const
Definition: TGCArguments.cxx:48
LVL1TGCTrigger::TGCTrackSelector::input
void input(TGCRPhiCoincidenceOut *rPhiOut)
Definition: TGCTrackSelector.cxx:38
lumiFormat.i
int i
Definition: lumiFormat.py:92
LVL1TGCTrigger::TGCRPhiCoincidenceMatrix::doCoincidence
TGCRPhiCoincidenceOut * doCoincidence()
Definition: TGCRPhiCoincidenceMatrix.cxx:62
LVL1TGCTrigger::TGCSectorLogic::m_tileMuLUT
std::shared_ptr< const LVL1TGC::TGCTileMuCoincidenceLUT > m_tileMuLUT
Definition: TGCSectorLogic.h:128
LVL1TGCTrigger::TGCSSCController::getNumberOfWireHighPtBoard
int getNumberOfWireHighPtBoard()
Definition: TGCSSCController.h:24
LVL1TGCTrigger::TGCSectorLogic::m_mapGoodMF
std::shared_ptr< const LVL1TGC::TGCGoodMF > m_mapGoodMF
Definition: TGCSectorLogic.h:134
LVL1TGCTrigger::TGCInnerTrackletSlot::NUMBER_OF_TRIGGER_BITS
@ NUMBER_OF_TRIGGER_BITS
Definition: TGCInnerTrackletSlot.h:39
LVL1TGCTrigger::TGCSectorLogic::m_wireHighPtBoard
TGCHighPtBoard * m_wireHighPtBoard[MaxNumberOfWireHighPtBoard]
Definition: TGCSectorLogic.h:142
LVL1TGCTrigger::TGCSectorLogic::hitTileMu
bool hitTileMu(const uint8_t &mask, const uint8_t &hit6, const uint8_t &hit56) const
Definition: TGCSectorLogic.cxx:467
LVL1TGC::TGCTileMuCoincidenceLUT::TM_D6_H
@ TM_D6_H
Definition: TGCTileMuCoincidenceLUT.h:84
LVL1TGC::TGCEIFICoincidenceMap::getFlagROI
int getFlagROI(const unsigned int roi, const unsigned int ssc, const unsigned int sec) const
Definition: TGCEIFICoincidenceMap.cxx:267
LVL1TGCTrigger::TGCInnerTrackletSlot::STRIP
@ STRIP
Definition: TGCInnerTrackletSlot.h:37
LVL1TGCTrigger::TGCSectorLogic::doTGCEICoincidence
bool doTGCEICoincidence(TGCRPhiCoincidenceOut *coincidenceOut)
Definition: TGCSectorLogic.cxx:426
LVL1TGC::TGCTileMuCoincidenceLUT::N_Input_TileMuModule
@ N_Input_TileMuModule
Definition: TGCTileMuCoincidenceLUT.h:89
LVL1TGC::TGCTMDBOut::getHit56
TileModuleHit getHit56() const
Definition: TGCTMDBOut.h:37
LVL1TGCTrigger::TGCRPhiCoincidenceMatrix::clear
void clear()
Definition: TGCRPhiCoincidenceMatrix.cxx:51
LVL1TGC::TGCTMDBOut::getHit6
TileModuleHit getHit6() const
Definition: TGCTMDBOut.h:38
LVL1TGCTrigger::TGCArguments::set_USE_NSW
void set_USE_NSW(bool v)
Definition: TGCArguments.cxx:35
LVL1TGCTrigger::TGCSectorLogic::m_useEIFI
bool m_useEIFI
Definition: TGCSectorLogic.h:118
LVL1TGCTrigger::TGCRPhiCoincidenceMatrix::setSideId
void setSideId(int sideIdIn)
Definition: TGCRPhiCoincidenceMatrix.h:23
LVL1TGCTrigger::TGCArguments::USE_BIS78
bool USE_BIS78() const
Definition: TGCArguments.cxx:50
LVL1TGCTrigger::TGCSectorLogic::doTGCNSWCoincidence
void doTGCNSWCoincidence(TGCRPhiCoincidenceOut *coincidenceOut)
Definition: TGCSectorLogic.cxx:387
LVL1TGCTrigger::TGCSectorLogic::getNumberOfSubSectorCluster
int getNumberOfSubSectorCluster() const
Definition: TGCSectorLogic.h:153
LVL1TGCTrigger::TGCSectorLogic::m_moduleId
int m_moduleId
Definition: TGCSectorLogic.h:113
LVL1TGC::TGCEIFICoincidenceMap::getTriggerBit
int getTriggerBit(const int slot, const int ssc, const int sec, const int reg, const int read, const int bit) const
Definition: TGCEIFICoincidenceMap.cxx:284
LVL1TGCTrigger::TGCRPhiCoincidenceMatrix::inputPhi
void inputPhi(int phiIn, int dPhiIn, int ptPhiIn)
Definition: TGCRPhiCoincidenceMatrix.cxx:33
LVL1TGCTrigger::TGCSectorLogic::m_mapBIS78
std::shared_ptr< const LVL1TGC::TGCBIS78CoincidenceMap > m_mapBIS78
Definition: TGCSectorLogic.h:133
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