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36 m_NumberOfWireHighPtBoard(0),
37 m_SSCController(tgcargs,this),
38 m_matrix(tgcargs,this),
40 m_trackSelector(this),
42 m_wordInnerStation(0),
43 m_stripHighPtBoard(0),
44 m_stripHighPtChipOut(0),
151 if(SSCCOut->
hasHit(SSCid)){
156 if(SSCCOut->
hasHit(SSCid, phiposInSSC)){
158 SSCCOut->
getDPhi(SSCid,phiposInSSC),
159 SSCCOut->
getPtPhi(SSCid,phiposInSSC));
165 if(SSCCOut->
hasHit(SSCid,
true)){
170 if(SSCCOut->
hasHit(SSCid, phiposInSSC,
true)){
172 SSCCOut->
getDPhi(SSCid,phiposInSSC,
true),
173 SSCCOut->
getPtPhi(SSCid,phiposInSSC,
true));
178 if (oredCoincidenceOut) {
180 if (coincidenceOut->
isSuperior(oredCoincidenceOut)) {
181 delete oredCoincidenceOut;
183 delete coincidenceOut;
184 coincidenceOut = oredCoincidenceOut;
187 coincidenceOut = oredCoincidenceOut;
192 if (coincidenceOut) {
203 if (coincidenceOut) {
207 if(SSCCOut!=0)
delete SSCCOut;
240 std::cout<<
"#SL O"<<
" BID:"<<
m_bid
242 <<
" SLid:"<<
m_id<<
" ";
247 : m_bid(right.m_bid), m_id(right.m_id),
248 m_sideId(right.m_sideId),
249 m_sectorId(right.m_sectorId), m_moduleId(right.m_moduleId),
250 m_octantId(right.m_octantId),
251 m_region(right.m_region),
252 m_NumberOfWireHighPtBoard(right.m_NumberOfWireHighPtBoard),
253 m_useEIFI(right.m_useEIFI), m_useTileMu(right.m_useTileMu),
254 m_useGoodMF(right.m_useGoodMF), m_nswSide(right.m_nswSide),
255 m_SSCController(right.tgcArgs(),this),
256 m_matrix(right.tgcArgs(),this),
257 m_mapEIFI(right.m_mapEIFI),
258 m_pTMDB(right.m_pTMDB),
259 m_wordTileMuon(0), m_wordInnerStation(0),
260 m_stripHighPtBoard(right.m_stripHighPtBoard),
261 m_stripHighPtChipOut(0),
262 m_tgcArgs(right.m_tgcArgs)
282 if (
this != &right ) {
333 if (coincidenceOut == 0)
return;
335 int pt = coincidenceOut->
getpT();
347 int pos = 4*coincidenceOut->
getR() + coincidenceOut->
getPhi();
352 bool validBIS78 =
false;
365 int pos = 4*coincidenceOut->
getR() + coincidenceOut->
getPhi();
398 std::shared_ptr<const LVL1TGC::BIS78TrigOut> pBIS78Out =
m_bis78->getOutput(
m_sectorId);
399 if ( pBIS78Out.get() == 0 )
return false;
403 coincidenceOut->
getRoI());
415 bool isHitTileMu=
false;
428 bool isHitInner=
false;
435 bool isHitWire =
false;
439 if(isHitWire){
break;}
443 bool isHitStrip =
false;
447 if(isHitStrip){
break;}
450 isHitInner = isHitWire && isHitStrip;
TGCSSCControllerOut * distribute(TGCHighPtChipOut *wire[], TGCHighPtChipOut *strip)
int getPtPhi(int ssc, int phipos, bool ored=false) const
const TGCInnerTrackletSlot * m_innerTrackletSlots[TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR]
void inputR(int rIn, int dRIn, int ptRIn)
bool select(std::shared_ptr< TGCTrackSelectorOut > TrackcandidateOut)
bool hasHit(int ssc, bool ored=false) const
std::shared_ptr< const TGCNSWCoincidenceMap > m_mapNSW
std::shared_ptr< const LVL1TGC::TGCNSW > m_nsw
int getPtR(int ssc) const
std::shared_ptr< TGCTrackSelectorOut > m_trackSelectorOut
int m_NumberOfWireHighPtBoard
void setInnerTrackletSlots(const TGCInnerTrackletSlot *innerTrackletSlots[])
void setBIS78(std::shared_ptr< const LVL1TGC::TGCBIS78 > bis78)
void doInnerCoincidence(const SG::ReadCondHandleKey< TGCTriggerData > &readCondKey, int SSCId, TGCRPhiCoincidenceOut *coincidenceOut)
TGCSectorLogic & operator=(const TGCSectorLogic &right)
std::shared_ptr< const LVL1TGC::TGCBIS78 > m_bis78
LVL1TGC::TGCSide m_sideId
void setNSW(std::shared_ptr< const LVL1TGC::TGCNSW > nsw)
bool doTILECoincidence(TGCRPhiCoincidenceOut *coincidenceOut)
TGCSSCController m_SSCController
bool doTGCBIS78Coincidence(TGCRPhiCoincidenceOut *coincidenceOut)
TGCHighPtBoard * m_stripHighPtBoard
TGCSectorLogic(TGCArguments *, const TGCDatabaseManager *db, TGCRegionType regionIn, int id)
void setGoodMFFlag(bool goodMFFlagIn)
TGCRPhiCoincidenceMatrix m_matrix
virtual ~TGCSectorLogic()
const std::vector< uint8_t > & getNSWeta() const
void set_USE_BIS78(bool v)
bool isSuperior(const TGCRPhiCoincidenceOut *right) const
bool getTriggerBit(const unsigned int region, const unsigned int readout, const unsigned int iBit) const
bool FORCE_NSW_COIN() const
void input(TGCRPhiCoincidenceOut *rPhiOut)
void setTMDB(std::shared_ptr< const LVL1TGC::TGCTMDB > tmdb)
TGCRPhiCoincidenceOut * doCoincidence()
std::shared_ptr< const LVL1TGC::TGCTileMuCoincidenceLUT > m_tileMuLUT
const std::string & NSWSideInfo() const
int getNumberOfWireHighPtBoard()
void setWireHighPtBoard(int port, TGCHighPtBoard *highPtBoard)
std::shared_ptr< const LVL1TGC::TGCGoodMF > m_mapGoodMF
TGCHighPtBoard * m_wireHighPtBoard[MaxNumberOfWireHighPtBoard]
bool hitTileMu(const uint8_t &mask, const uint8_t &hit6, const uint8_t &hit56) const
int getDPhi(int ssc, int phipos, bool ored=false) const
@ MaxNumberOfWireHighPtBoard
int getFlagROI(const unsigned int roi, const unsigned int ssc, const unsigned int sec) const
bool doTGCEICoincidence(TGCRPhiCoincidenceOut *coincidenceOut)
@ NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR
TileModuleHit getHit56() const
TileModuleHit getHit6() const
void setSideId(int sideIdIn)
void clockIn(const SG::ReadCondHandleKey< TGCTriggerData > &readCondKey, int bidIn, bool process=true)
void doTGCNSWCoincidence(TGCRPhiCoincidenceOut *coincidenceOut)
int getNumberOfSubSectorCluster() const
int getTriggerBit(const int slot, const int ssc, const int sec, const int reg, const int read, const int bit) const
void inputPhi(int phiIn, int dPhiIn, int ptPhiIn)
void setInnerCoincidenceFlag(bool InnerCoincidenceFlagIn)
std::shared_ptr< const LVL1TGC::TGCBIS78CoincidenceMap > m_mapBIS78
bool doTGCFICoincidence(TGCRPhiCoincidenceOut *coincidenceOut)
void setCoincidenceLUT(std::shared_ptr< const LVL1TGC::BigWheelCoincidenceLUT > lut)
const LVL1TGC::TGCEIFICoincidenceMap * m_mapEIFI
TGCHighPtChipOut * m_wireHighPtChipOut[MaxNumberOfWireHighPtBoard]
void setStripHighPtBoard(TGCHighPtBoard *highPtBoard)
void dec2bin(int dec, char *binstr, int length)
TGCSide
The sides of TGC (A- or C-side)
void getTrackSelectorOutput(std::shared_ptr< TGCTrackSelectorOut > &trackSelectorOut) const
int getPhi(int ssc, int phipos, bool ored=false) const
TGCHighPtChipOut * getOutput()
void setRegion(TGCRegionType regionIn)
void setSSCId(int SSCIdIn)
TGCTrackSelector m_trackSelector
std::shared_ptr< const LVL1TGC::TGCTMDB > m_pTMDB
TGCHighPtChipOut * m_stripHighPtChipOut