ATLAS Offline Software
TGCSectorLogic.cxx
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1 /*
2  Copyright (C) 2002-2023 CERN for the benefit of the ATLAS collaboration
3 */
4 
11 #include "TrigT1TGC/TGCTMDB.h"
12 #include "TrigT1TGC/TGCTMDBOut.h"
15 #include "TrigT1TGC/TGCNSW.h"
16 #include "TrigT1TGC/NSWTrigOut.h"
18 #include "TrigT1TGC/TGCBIS78.h"
19 #include "TrigT1TGC/BIS78TrigOut.h"
21 #include "TrigT1TGC/TGCGoodMF.h"
23 
26 
27 #include <iostream>
28 
29 namespace LVL1TGCTrigger {
30 
32  TGCRegionType regionIn, int idIn)
33  : m_bid(0),
34  m_id(idIn),
35  m_region(regionIn),
36  m_NumberOfWireHighPtBoard(0),
37  m_SSCController(tgcargs,this),
38  m_matrix(tgcargs,this),
39  m_pTMDB(0),
40  m_trackSelector(this),
41  m_wordTileMuon(0),
42  m_wordInnerStation(0),
43  m_stripHighPtBoard(0),
44  m_stripHighPtChipOut(0),
45  m_tgcArgs(tgcargs)
46 {
47  m_sideId = static_cast<LVL1TGC::TGCSide>((idIn / NumberOfModule) / NumberOfOctant);
49  m_moduleId = idIn % NumberOfModule;
50 
52  m_sectorId = m_moduleId%3 + 2*(m_moduleId/3);
54  } else {
57  }
58 
59  m_nswSide = (tgcArgs()->NSWSideInfo().find('A')!=std::string::npos && m_sideId == LVL1TGC::TGCSide::ASIDE)
60  || (tgcArgs()->NSWSideInfo().find('C')!=std::string::npos && m_sideId == LVL1TGC::TGCSide::CSIDE);
61 
62  m_SSCController.setRegion(regionIn);
63 
65  m_mapEIFI = db->getEIFICoincidenceMap(m_sideId);
66 
68 
69  m_matrix.setCoincidenceLUT(db->getBigWheelCoincidenceLUT());
70  m_tileMuLUT = db->getTileMuCoincidenceLUT();
71  m_useTileMu = (m_tileMuLUT != nullptr) && m_useTileMu;
72 
73  m_mapGoodMF = db->getGoodMFMap();
74  m_mapNSW = db->getNSWCoincidenceMap(m_sideId, m_octantId, m_moduleId);
75  if(tgcArgs()->USE_BIS78()) m_mapBIS78 = db->getBIS78CoincidenceMap();
76 
78 
79  for(int i=0; i<MaxNumberOfWireHighPtBoard; i++){
80  m_wireHighPtBoard[i] = 0;
82  }
83 
84  for(unsigned int iSlot=0; iSlot<TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR; iSlot++) {
85  m_innerTrackletSlots[iSlot] = 0;
86  }
87 
89  if(m_mapEIFI == 0) m_useEIFI = false;
90  m_useGoodMF = (m_mapGoodMF != nullptr);
91  if(m_mapNSW == 0) tgcArgs()->set_USE_NSW(false);
92  if(m_mapBIS78 == 0) tgcArgs()->set_USE_BIS78(false);
93 }
94 
96 {}
97 
98 void TGCSectorLogic::setTMDB(std::shared_ptr<const LVL1TGC::TGCTMDB> tmdb)
99 {
100  m_pTMDB = tmdb;
101  if (m_pTMDB==0) m_useTileMu = false;
102 }
103 
104 void TGCSectorLogic::setNSW(std::shared_ptr<const LVL1TGC::TGCNSW> nsw)
105 {
106  m_nsw = nsw;
107  if(m_nsw == 0) tgcArgs()->set_USE_NSW(false);
108 }
109 
110 void TGCSectorLogic::setBIS78(std::shared_ptr<const LVL1TGC::TGCBIS78> bis78)
111 {
112  m_bis78 = bis78;
113  if(m_bis78 == 0) tgcArgs()->set_USE_BIS78(false);
114 }
115 
117 {
118  m_wireHighPtBoard[port] = highPtBoard;
120 }
121 
123 {
124  m_stripHighPtBoard = highPtBoard;
125 }
126 
127 void TGCSectorLogic::getTrackSelectorOutput(std::shared_ptr<TGCTrackSelectorOut> &trackSelectorOut)const
128 {
129  trackSelectorOut=m_trackSelectorOut;
130 }
131 
133  int bidIn, bool process)
134 {
135  // skip to process if want. (e.g. no hit in TGC)
136  if(!process) return;
137 
138  m_bid=bidIn;
139 
140  collectInput();
141 
142  TGCSSCControllerOut* SSCCOut =
144 #ifdef TGCDEBUG
145  SSCCOut->print();
146 #endif
147  deleteHPBOut();
148 
149  for(int SSCid=0; SSCid<getNumberOfSubSectorCluster(); SSCid+=1){
150  TGCRPhiCoincidenceOut* coincidenceOut = 0;
151  if(SSCCOut->hasHit(SSCid)){
152  m_matrix.clear();
153  m_matrix.setSSCId(SSCid);
154  m_matrix.inputR(SSCCOut->getR(SSCid),SSCCOut->getDR(SSCid),SSCCOut->getPtR(SSCid));
155  for(int phiposInSSC = 0 ;phiposInSSC < TGCSSCControllerOut::MaxNumberOfPhiInSSC; phiposInSSC++){
156  if(SSCCOut->hasHit(SSCid, phiposInSSC)){
157  m_matrix.inputPhi(SSCCOut->getPhi(SSCid,phiposInSSC),
158  SSCCOut->getDPhi(SSCid,phiposInSSC),
159  SSCCOut->getPtPhi(SSCid,phiposInSSC));
160  }
161  }
162  coincidenceOut = m_matrix.doCoincidence();
163  }
165  if(SSCCOut->hasHit(SSCid,true)){
166  m_matrix.clear();
167  m_matrix.setSSCId(SSCid);
168  m_matrix.inputR(SSCCOut->getR(SSCid),SSCCOut->getDR(SSCid),SSCCOut->getPtR(SSCid));
169  for(int phiposInSSC = 0 ;phiposInSSC < TGCSSCControllerOut::MaxNumberOfPhiInSSC; phiposInSSC++){
170  if(SSCCOut->hasHit(SSCid, phiposInSSC, true)){
171  m_matrix.inputPhi(SSCCOut->getPhi(SSCid,phiposInSSC,true),
172  SSCCOut->getDPhi(SSCid,phiposInSSC,true),
173  SSCCOut->getPtPhi(SSCid,phiposInSSC,true));
174  }
175  }
176 
177  TGCRPhiCoincidenceOut* oredCoincidenceOut = m_matrix.doCoincidence();
178  if (oredCoincidenceOut) {
179  if(coincidenceOut) {
180  if (coincidenceOut->isSuperior(oredCoincidenceOut)) {
181  delete oredCoincidenceOut;
182  } else {
183  delete coincidenceOut;
184  coincidenceOut = oredCoincidenceOut;
185  }
186  } else {
187  coincidenceOut = oredCoincidenceOut;
188  }
189  }
190  }
191 
192  if (coincidenceOut) {
193  if (m_useGoodMF) {
194  bool isgoodMF = m_mapGoodMF->test_GoodMF(m_moduleId,SSCid,coincidenceOut->getRoI());
195  coincidenceOut->setGoodMFFlag(isgoodMF);
196  }
197  }
198 
200  // do coincidence with Inner Tracklet of EI, NSW, Tile, and/or RPC-BIS78
201  doInnerCoincidence(SSCid, coincidenceOut);
202 
203  if (coincidenceOut) {
204  m_trackSelector.input(coincidenceOut);
205  }
206  }
207  if(SSCCOut!=0) delete SSCCOut;
208  SSCCOut=0;
209 
210  // Track selector chooses up to 4 track candidates to be sent to MUCTPI.
212 }
213 
215 {
216  for(int i = 0; i < m_SSCController.getNumberOfWireHighPtBoard(); i += 1) {
219  }
220 
223 }
224 
226 {
229 
230  int i;
231  for( i = 0; i < m_SSCController.getNumberOfWireHighPtBoard(); i += 1) {
232  if(m_wireHighPtChipOut[i]!=0) delete m_wireHighPtChipOut[i];
234  }
235 }
236 
237 
239 {
240  std::cout<<"#SL O"<<" BID:"<<m_bid
241  <<" region:"<<((m_region == TGCRegionType::FORWARD) ? "FWD" : "END")
242  <<" SLid:"<<m_id<<" ";
243 }
244 
245 
247  : m_bid(right.m_bid), m_id(right.m_id),
248  m_sideId(right.m_sideId),
249  m_sectorId(right.m_sectorId), m_moduleId(right.m_moduleId),
250  m_octantId(right.m_octantId),
251  m_region(right.m_region),
252  m_NumberOfWireHighPtBoard(right.m_NumberOfWireHighPtBoard),
253  m_useEIFI(right.m_useEIFI), m_useTileMu(right.m_useTileMu),
254  m_useGoodMF(right.m_useGoodMF), m_nswSide(right.m_nswSide),
255  m_SSCController(right.tgcArgs(),this),
256  m_matrix(right.tgcArgs(),this),
257  m_mapEIFI(right.m_mapEIFI),
258  m_pTMDB(right.m_pTMDB),
259  m_wordTileMuon(0), m_wordInnerStation(0),
260  m_stripHighPtBoard(right.m_stripHighPtBoard),
261  m_stripHighPtChipOut(0),
262  m_tgcArgs(right.m_tgcArgs)
263 {
264  for(int i=0; i<MaxNumberOfWireHighPtBoard; i++){
265  m_wireHighPtBoard[i] = 0;
266  m_wireHighPtChipOut[i] = 0;
267  }
268 
269  for( int i = 0; i < m_SSCController.getNumberOfWireHighPtBoard(); i += 1) {
272  }
273 
274  for (unsigned int iSlot=0; iSlot<TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR; iSlot++) {
275  m_innerTrackletSlots[iSlot] = right.m_innerTrackletSlots[iSlot];
276  }
277 }
278 
281 {
282  if ( this != &right ) {
283  m_tgcArgs = right.m_tgcArgs;
284  m_matrix = right.m_matrix;
285  m_bid =right.m_bid;
286  m_id =right.m_id;
287  m_sideId = right.m_sideId;
288  m_sectorId=right.m_sectorId;
289  m_moduleId=right.m_moduleId;
290  m_octantId=right.m_octantId;
291  m_region=right.m_region;
293  m_mapEIFI=right.m_mapEIFI;
294  m_pTMDB=right.m_pTMDB;
295  m_wordTileMuon=0;
299  m_useEIFI=right.m_useEIFI;
300  m_useTileMu=right.m_useTileMu;
301  for( int i = 0; i < m_SSCController.getNumberOfWireHighPtBoard(); i += 1) {
304  }
305  for (unsigned int iSlot=0; iSlot<TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR; iSlot++) {
306  m_innerTrackletSlots[iSlot] = right.m_innerTrackletSlots[iSlot];
307  }
308  }
309  return *this;
310 }
311 
312 
313 void TGCSectorLogic::dec2bin(int dec, char* binstr, int length)
314 {
315  for (int i=0; i<length; i++){
316  if((dec>>i) & 1)
317  binstr[length-1-i] = '1';
318  else
319  binstr[length-1-i] = '0';
320  }
321  binstr[length] ='\0';
322 }
323 
325 {
326  for(unsigned int iSlot=0; iSlot<TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR; iSlot++) {
327  m_innerTrackletSlots[iSlot] = innerTrackletSlots[iSlot];
328  }
329 }
330 
331 
333  if (coincidenceOut == 0) return;
334 
335  int pt = coincidenceOut->getpT();
336  if (pt==0) return;
337 
338  if(SSCId <= 4 && m_region == TGCRegionType::ENDCAP){ //3 detectors are used to inner coincidnece in SSC#0~4 in Endcap;
339 
340  // WHICH INNER COINCIDENCE
341  // select a inner station detector which is used in inner coincidence algorithm.
342  //Defenation of innerDetectorNumber :: enum{EI=0,TILE,BIS78};
343 
344  /*int innerDetectorNumber = which_InnerCoincidence();*/ //this function will be implemented.
345 
346  // The below section is a tmporary method. It will be replaced with WICHINNER COINCIDENCE.
347  int pos = 4*coincidenceOut->getR() + coincidenceOut->getPhi();
348  // check if inner is used for the roi
349  bool validEI = (m_mapEIFI->getFlagROI(pos, coincidenceOut->getIdSSC(), m_sectorId) == 1);
350  // check if TileMu is used for the roi
351  bool validTileMu = (m_tileMuLUT->getFlagROI(pos, coincidenceOut->getIdSSC(), m_sectorId, m_sideId) == 1);
352  bool validBIS78 = false;
353  if(tgcArgs()->USE_BIS78()) validBIS78=(m_mapBIS78->getFlagROI(pos, coincidenceOut->getIdSSC(), m_sectorId, m_sideId) == 1);
354 
355  bool isEI=false;
356  bool isTILE=false;
357  bool isBIS78=false;
358  if(m_useEIFI && validEI){isEI=doTGCEICoincidence(coincidenceOut);}
359  if(m_useTileMu && validTileMu){isTILE=doTILECoincidence(coincidenceOut); }
360  if(validBIS78){isBIS78=doTGCBIS78Coincidence(coincidenceOut); }
361 
362  coincidenceOut->setInnerCoincidenceFlag(isEI || isTILE || isBIS78 || (!m_useEIFI && !validEI && !m_useTileMu && !validTileMu && !tgcArgs()->USE_BIS78() && !validBIS78));
363  } else {
364  // NSW or FI are used to inner coincidnece in SSC#5~18 in Endcap and Forward region
365  int pos = 4*coincidenceOut->getR() + coincidenceOut->getPhi();
366  bool validFI = (m_mapEIFI->getFlagROI(pos, coincidenceOut->getIdSSC(), m_sectorId) == 1) && m_region == TGCRegionType::ENDCAP;
367 
368  if(tgcArgs()->USE_NSW() && m_nswSide){
369  if(tgcArgs()->FORCE_NSW_COIN()){
370  coincidenceOut->setInnerCoincidenceFlag(true);
371  }
372  else{
373  doTGCNSWCoincidence(coincidenceOut);
374  }
375  }
376  else if(!m_nswSide && validFI){
377  if(m_useEIFI){
378  coincidenceOut->setInnerCoincidenceFlag( doTGCFICoincidence(coincidenceOut) );
379  }
380  } else {
381  coincidenceOut->setInnerCoincidenceFlag(true); // TBD
382  }
383  }
384 }
385 
386 
388  std::shared_ptr<const LVL1TGC::NSWTrigOut> pNSWOut = m_nsw->getOutput(m_region,m_sideId,m_sectorId);
389 
390  // for now, if there is a hit at NSW and the side is included in the detector mask, turn on the inner coin flag
391  coincidenceOut->setInnerCoincidenceFlag( pNSWOut->getNSWeta().size()>0 && m_nswSide);
392  return;
393 
394  // will implement NSW pT calculation later
395 }
396 
398  std::shared_ptr<const LVL1TGC::BIS78TrigOut> pBIS78Out = m_bis78->getOutput(m_sectorId);
399  if ( pBIS78Out.get() == 0 ) return false;
400  int pt=0;
401 
402  pt = m_mapBIS78->TGCBIS78_pt(pBIS78Out.get(),
403  coincidenceOut->getRoI());
404 
405  return (pt > 0);
406 }
407 
409 {
411  // The function is called for Run-3 algorithim, but the Run-2 algorithm is
412  // temporarily used for instance.
414 
415  bool isHitTileMu=false;
417  uint8_t maskTM = (uint8_t)(m_tileMuLUT->getTrigMask(mod, coincidenceOut->getIdSSC(), m_sectorId, m_sideId));
418  std::shared_ptr<const LVL1TGC::TGCTMDBOut> tm = m_pTMDB->getOutput(m_sideId, m_sectorId, mod);
419  isHitTileMu = isHitTileMu || this->hitTileMu(maskTM, tm->getHit6(), tm->getHit56());
420  }
421 
422  return isHitTileMu;
423 }
424 
425 
427 
428  bool isHitInner=false;
429  for(unsigned int iSlot=0;iSlot<TGCInnerTrackletSlotHolder::NUMBER_OF_SLOTS_PER_TRIGGER_SECTOR; iSlot++) {
430  const TGCInnerTrackletSlot* hit = m_innerTrackletSlots[iSlot];
431 
432  for (size_t reg=0;reg< TGCInnerTrackletSlot::NUMBER_OF_REGIONS; reg++){
433 
434  // Wire
435  bool isHitWire = false;
436  for (size_t bit=0; bit< TGCInnerTrackletSlot::NUMBER_OF_TRIGGER_BITS; bit++){
437  isHitWire = m_mapEIFI->getTriggerBit(iSlot, coincidenceOut->getIdSSC(), m_sectorId, reg, TGCInnerTrackletSlot::WIRE, bit)
438  && hit->getTriggerBit(reg,TGCInnerTrackletSlot::WIRE,bit) ;
439  if(isHitWire){break;}
440  }
441 
442  // Strip
443  bool isHitStrip = false;
444  for (size_t bit=0;bit< TGCInnerTrackletSlot::NUMBER_OF_TRIGGER_BITS; bit++){
445  isHitStrip = m_mapEIFI->getTriggerBit(iSlot, coincidenceOut->getIdSSC(), m_sectorId, reg, TGCInnerTrackletSlot::STRIP, bit)
447  if(isHitStrip){break;}
448  }
449 
450  isHitInner = isHitWire && isHitStrip;
451  if(isHitInner){
452  return true;
453  }
454  }
455 
456  }
457 
458  return false;
459 }
460 
461 
463  return doTGCEICoincidence(coincidenceOut);
464 }
465 
466 
467 bool TGCSectorLogic::hitTileMu(const uint8_t& mask, const uint8_t& hit6, const uint8_t& hit56) const
468 {
474  switch(mask) {
477  break;
479  return (hit6==LVL1TGC::TGCTMDBOut::TM_HIGH);
480  break;
483  break;
485  return (hit56==LVL1TGC::TGCTMDBOut::TM_HIGH);
486  break;
487  default:
488  return false;
489  break;
490  }
491  return true;
492 }
493 
494 } //end of namespace bracket
LVL1TGCTrigger::TGCSSCController::distribute
TGCSSCControllerOut * distribute(TGCHighPtChipOut *wire[], TGCHighPtChipOut *strip)
Definition: TGCSSCController.cxx:21
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Definition: TGCHighPtBoard.cxx:149
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Definition: TGCSectorLogic.h:85
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Definition: TGCSSCControllerOut.h:177
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Definition: TGCRPhiCoincidenceMatrix.cxx:18
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Definition: TGCTrackSelector.cxx:48
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Definition: TGCSectorLogic.h:119
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Definition: TGCRPhiCoincidenceOut.h:16
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@ TM_D56_L
Definition: TGCTileMuCoincidenceLUT.h:85
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Definition: TGCSectorLogic.h:130
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Definition: TGCSSCControllerOut.h:135
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Definition: RunTileCalibRec.py:234
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Definition: TGCSectorLogic.h:111
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Definition: TGCSectorLogic.h:116
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Definition: TGCSectorLogic.cxx:110
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Definition: TGCArguments.cxx:42
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Definition: TGCSectorLogic.h:112
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Definition: TGCSectorLogic.cxx:104
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Definition: TGCSectorLogic.cxx:408
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Definition: TGCSectorLogic.h:123
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