104{
105 const EventContext& ctx = getContext();
106
107
108
109 SG::ReadHandle<FPGATrackSimHitCollection> FPGAHits(
m_FPGAHitKey, ctx);
110 if (!FPGAHits.isValid()) {
112 ATH_MSG_WARNING(
"Didn't receive FPGAHits_2nd on first event; assuming no input events.");
113 }
114 SmartIF<IEventProcessor> appMgr{service("ApplicationMgr")};
115 if (!appMgr) {
116 ATH_MSG_ERROR(
"Failed to retrieve ApplicationMgr as IEventProcessor");
117 return StatusCode::FAILURE;
118 }
119 return appMgr->stopRun();
120 }
121
123 if (!FPGAInputTracks.isValid()) {
124 SmartIF<IEventProcessor> appMgr{service("ApplicationMgr")};
125 if (!appMgr) {
126 ATH_MSG_ERROR(
"Failed to retrieve ApplicationMgr as IEventProcessor");
127 return StatusCode::FAILURE;
128 }
129 return appMgr->stopRun();
130 }
131
132
133 SG::WriteHandle<FPGATrackSimRoadCollection> FPGARoads_2nd (
m_FPGARoadKey, ctx);
134
135 ATH_CHECK( FPGARoads_2nd.record (std::make_unique<FPGATrackSimRoadCollection>()));
136
137 SG::WriteHandle<FPGATrackSimTrackCollection> FPGATracks_2ndHandle (
m_FPGATrackKey, ctx);
138 ATH_CHECK(FPGATracks_2ndHandle.record (std::make_unique<FPGATrackSimTrackCollection>()));
139 {
140 std::optional<Athena::Chrono> chrono;
142
143 if (!
m_evtSel->getSelectedEvent()) {
145 return StatusCode::SUCCESS;
146 }
147
148
150 }
151
152
153 std::vector<std::shared_ptr<const FPGATrackSimHit>> phits_2nd;
154 phits_2nd.reserve(FPGAHits->size());
155 for (
const FPGATrackSimHit*
hit : *FPGAHits) {
156 phits_2nd.emplace_back(
hit, [](
const FPGATrackSimHit*) {});
157 }
158
159 ATH_MSG_DEBUG(
"Retrieved " << phits_2nd.size() <<
" hits and " << FPGAInputTracks->size() <<
" tracks from storegate");
160
161
162 SG::ReadHandle<FPGATrackSimTruthTrackCollection> FPGATruthTracks(
m_FPGATruthTrackKey, ctx);
163 if (!FPGATruthTracks.isValid()) {
164 ATH_MSG_ERROR(
"Could not find FPGA Truth Track Collection with key " << FPGATruthTracks.key());
165 return StatusCode::FAILURE;
166 }
167
168
170 if (!FPGAOfflineTracks.isValid()) {
171 ATH_MSG_ERROR(
"Could not find FPGA Offline Track Collection with key " << FPGAOfflineTracks.key());
172 return StatusCode::FAILURE;
173 }
174
175
177 if (!FPGAEventInfo.isValid()) {
178 ATH_MSG_ERROR(
"Could not find FPGA Event Info with key " << FPGAEventInfo.key());
179 return StatusCode::FAILURE;
180 }
181 FPGATrackSimEventInfo eventInfo = *FPGAEventInfo.cptr();
183
184
185 std::vector<FPGATrackSimRoad> roads;
186
187 {
188 std::optional<Athena::Chrono> chrono;
190
192
193 for (auto const& road : roads) {
194 FPGARoads_2nd->push_back(road);
195 }
196 }
197
198 auto mon_nroads = Monitored::Scalar<unsigned>("nroads_2nd", roads.size());
199 unsigned bitmask_best(0);
200 unsigned nhit_best(0);
201 for (auto const &road : roads) {
202 unsigned bitmask = road.getHitLayers();
203 if (road.getNHitLayers() > nhit_best) {
204 nhit_best = road.getNHitLayers();
205 bitmask_best = bitmask;
206 }
208 if (bitmask & (1 << l)) {
209 auto mon_layerIDs = Monitored::Scalar<unsigned>("layerIDs_2nd",l);
210 Monitored::Group(
m_monTool,mon_layerIDs);
211 }
212 }
213 }
214
216 if (bitmask_best & (1 << l)) {
217 auto mon_layerIDs_best = Monitored::Scalar<unsigned>("layerIDs_2nd_best",l);
218 Monitored::Group(
m_monTool,mon_layerIDs_best);
219 }
220 }
222
223
224 auto mon_nroads_postfilter = Monitored::Scalar<unsigned>("nroads_2nd_postfilter", roads.size());
225 Monitored::Group(
m_monTool, mon_nroads_postfilter);
226
227
228
229 std::vector<FPGATrackSimTrack> tracks;
230 {
231 std::optional<Athena::Chrono> chrono;
237 } else {
239
241
242 std::vector<FPGATrackSimTrack> filteredTracks;
243
244 for (const auto& road : roads) {
245
246 std::vector<FPGATrackSimTrack> tracksForCurrentRoad;
247 std::vector<FPGATrackSimRoad> roadVec = {road};
249
250
251 if (!tracksForCurrentRoad.empty()) {
252 auto bestTrackIter = std::min_element(
253 tracksForCurrentRoad.begin(), tracksForCurrentRoad.end(),
254 [](
const FPGATrackSimTrack&
a,
const FPGATrackSimTrack& b) {
255 return a.getChi2ndof() < b.getChi2ndof();
256 });
257
258 if (bestTrackIter != tracksForCurrentRoad.end() && bestTrackIter->getChi2ndof() < 1.e15) {
259 filteredTracks.push_back(*bestTrackIter);
260
261
262 auto mon_chi2 = Monitored::Scalar<float>("chi2_2nd_all", bestTrackIter->getChi2ndof());
264 }
265 }
266 }
267
268
269 tracks = std::move(filteredTracks);
270
271
272 if (!tracks.empty()) {
273 float bestChi2Overall = std::min_element(
274 tracks.begin(), tracks.end(),
275 [](
const FPGATrackSimTrack&
a,
const FPGATrackSimTrack& b) {
276 return a.getChi2ndof() < b.getChi2ndof();
277 })->getChi2ndof();
278
279 auto mon_best_chi2 = Monitored::Scalar<float>("best_chi2_2nd", bestChi2Overall);
280 Monitored::Group(
m_monTool, mon_best_chi2);
281 }
282 } else {
284 float bestchi2 = 1.e15;
285 for (const FPGATrackSimTrack& track : tracks) {
287 if (
chi2 < bestchi2) bestchi2 =
chi2;
288 auto mon_chi2 = Monitored::Scalar<float>(
"chi2_2nd_all",
chi2);
290 }
291 auto mon_best_chi2 = Monitored::Scalar<float>("best_chi2_2nd", bestchi2);
292 Monitored::Group(
m_monTool, mon_best_chi2);
293 }
294 }
295 } else {
296
298 }
299 }
300 auto mon_ntracks = Monitored::Scalar<unsigned>("ntrack_2nd", tracks.size());
302
303
304 {
305 std::optional<Athena::Chrono> chrono;
308 }
309 {
310 std::optional<Athena::Chrono> chrono;
312
315 }
316 }
317 const auto& truthtracks = *FPGATruthTracks;
318 const auto& offlineTracks = *FPGAOfflineTracks;
319
320
321 {
322 std::optional<Athena::Chrono> chrono;
325 for (auto track : tracks) {
327 track.setQOverPt(truthtracks.front().getQOverPt());
329 track.setD0(truthtracks.front().getD0());
331 track.setPhi(truthtracks.front().getPhi());
333 track.setZ0(truthtracks.front().getZ0());
335 track.setEta(truthtracks.front().getEta());
336 }
337 }
338 }
339
340 unsigned ntrackOLRChi2 = 0;
341 {
342 std::optional<Athena::Chrono> chrono;
344 for (const FPGATrackSimTrack& track : tracks) {
347 if (
track.passedOR()) {
348 ntrackOLRChi2++;
350
351
352 float chi2olr =
track.getChi2ndof();
353 auto mon_chi2_or = Monitored::Scalar<float>("chi2_2nd_afterOLR", chi2olr);
354 Monitored::Group(
m_monTool, mon_chi2_or);
355 }
356 }
357 }
358 auto mon_ntracks_olr = Monitored::Scalar<unsigned>("ntrack_2nd_afterOLR", ntrackOLRChi2);
359 Monitored::Group(
m_monTool,mon_ntracks_olr);
360 }
361
364
365
366 {
367 std::optional<Athena::Chrono> chrono;
369 if (truthtracks.size() > 0) {
371 auto passroad = Monitored::Scalar<bool>("eff_road_2nd",(roads.size() > 0));
372 auto passtrack = Monitored::Scalar<bool>("eff_track_2nd",(tracks.size() > 0));
373 auto truthpT_zoom = Monitored::Scalar<float>("pT_zoom",truthtracks.front().getPt()*0.001);
374 auto truthpT = Monitored::Scalar<float>("pT",truthtracks.front().getPt()*0.001);
375 auto trutheta = Monitored::Scalar<float>("eta",truthtracks.front().getEta());
376 auto truthphi= Monitored::Scalar<float>("phi",truthtracks.front().getPhi());
377 auto truthd0= Monitored::Scalar<float>("d0",truthtracks.front().getD0());
378 auto truthz0= Monitored::Scalar<float>("z0",truthtracks.front().getZ0());
381
382 unsigned npasschi2(0);
383 unsigned npasschi2OLR(0);
384
385 if (tracks.size() > 0) {
388 for (const auto& track : tracks) {
390 npasschi2++;
391 if (
track.passedOR()) {
392 npasschi2OLR++;
393 }
394 }
395 }
396 }
401
402 auto passtrackchi2 = Monitored::Scalar<bool>("eff_track_chi2_2nd",(npasschi2 > 0));
403 Monitored::Group(
m_monTool,passroad,passtrack,truthpT_zoom,truthpT,trutheta,truthphi,truthd0,truthz0,passtrackchi2);
404 }
405 }
406
407 {
408 std::optional<Athena::Chrono> chrono;
410 for (const FPGATrackSimTrack& track : tracks) FPGATracks_2ndHandle->push_back(track);
411 }
412
413
414 {
415 std::optional<Athena::Chrono> chrono;
418 auto dataFlowInfo = std::make_unique<FPGATrackSimDataFlowInfo>();
420 }
421
425 }
426 }
427
428
431
432 return StatusCode::SUCCESS;
433}
#define ATH_CHECK
Evaluate an expression and check for errors.
#define ATH_MSG_WARNING(x)
void roadsToTrack(std::vector< FPGATrackSimRoad > &roads, std::vector< FPGATrackSimTrack > &track_cands, const FPGATrackSimPlaneMap *pmap)
ToolHandle< IFPGATrackSimTrackExtensionTool > m_trackExtensionTool
SG::WriteHandleKey< FPGATrackSimRoadCollection > m_FPGARoadKey
ServiceHandle< IChronoStatSvc > m_chrono
unsigned long m_maxNTracksTot
Gaudi::Property< float > m_trackScoreCut
SG::ReadHandleKey< FPGATrackSimOfflineTrackCollection > m_FPGAOfflineTrackKey
unsigned long m_maxNTracksChi2OLRTot
ToolHandle< GenericMonitoringTool > m_monTool
SG::WriteHandleKey< FPGATrackSimTrackCollection > m_FPGATrackKey
SG::ReadHandleKey< FPGATrackSimTrackCollection > m_FPGAInputTrackKey
SG::ReadHandleKey< FPGATrackSimTruthTrackCollection > m_FPGATruthTrackKey
Gaudi::Property< bool > m_writeOutNonSPStripHits
unsigned long m_maxNRoadsFound
FPGATrackSimLogicalEventOutputHeader * m_logicEventOutputHeader
SG::ReadHandleKey< FPGATrackSimEventInfo > m_FPGAEventInfoKey
Gaudi::Property< bool > m_doHoughRootOutput2nd
unsigned long m_maxNTracksChi2Tot
ToolHandle< FPGATrackSimHoughRootOutputTool > m_houghRootOutputTool
Gaudi::Property< bool > m_doNNTrack_2nd
Gaudi::Property< bool > m_doTracking
ServiceHandle< IFPGATrackSimEventSelectionSvc > m_evtSel
ToolHandle< FPGATrackSimNNTrackTool > m_NNTrackTool
Gaudi::Property< int > m_SetTruthParametersForTracks
FPGATrackSimLogicalEventInputHeader * m_slicedHitHeader
ToolHandle< FPGATrackSimTrackFitterTool > m_trackFitterTool
ServiceHandle< IFPGATrackSimMappingSvc > m_FPGATrackSimMapping
StatusCode writeOutputData(const std::vector< FPGATrackSimRoad > &roads_2nd, std::vector< FPGATrackSimTrack > const &tracks_2nd, FPGATrackSimDataFlowInfo const *dataFlowInfo)
Gaudi::Property< bool > m_passLowestChi2TrackOnly
long m_nTracksChi2OLRFound
ToolHandle< FPGATrackSimOverlapRemovalTool > m_overlapRemovalTool
Gaudi::Property< bool > m_writeOutputData
SG::ReadHandleKey< FPGATrackSimHitCollection > m_FPGAHitKey
double chi2(TH1 *h0, TH1 *h1)
l
Printing final latex table to .tex output file.
constexpr bool enableBenchmark