Execute method.
104{
105
106
107
108 SG::ReadHandle<FPGATrackSimHitCollection> FPGAHits(
m_FPGAHitKey, ctx);
109 if (!FPGAHits.isValid()) {
111 ATH_MSG_WARNING(
"Didn't receive FPGAHits_2nd on first event; assuming no input events.");
112 }
113 SmartIF<IEventProcessor> appMgr{service("ApplicationMgr")};
114 if (!appMgr) {
115 ATH_MSG_ERROR(
"Failed to retrieve ApplicationMgr as IEventProcessor");
116 return StatusCode::FAILURE;
117 }
118 return appMgr->stopRun();
119 }
120
122 if (!FPGAInputTracks.isValid()) {
123 SmartIF<IEventProcessor> appMgr{service("ApplicationMgr")};
124 if (!appMgr) {
125 ATH_MSG_ERROR(
"Failed to retrieve ApplicationMgr as IEventProcessor");
126 return StatusCode::FAILURE;
127 }
128 return appMgr->stopRun();
129 }
130
131
132 SG::WriteHandle<FPGATrackSimRoadCollection> FPGARoads_2nd (
m_FPGARoadKey, ctx);
133
134 ATH_CHECK( FPGARoads_2nd.record (std::make_unique<FPGATrackSimRoadCollection>()));
135
136 SG::WriteHandle<FPGATrackSimTrackCollection> FPGATracks_2ndHandle (
m_FPGATrackKey, ctx);
137 ATH_CHECK(FPGATracks_2ndHandle.record (std::make_unique<FPGATrackSimTrackCollection>()));
138 {
139 std::optional<Athena::Chrono> chrono;
141
142 if (!
m_evtSel->getSelectedEvent()) {
144 return StatusCode::SUCCESS;
145 }
146
147
149 }
150
151
152 std::vector<std::shared_ptr<const FPGATrackSimHit>> phits_2nd;
153 phits_2nd.reserve(FPGAHits->size());
154 for (const FPGATrackSimHit* hit : *FPGAHits) {
155 phits_2nd.emplace_back(hit, [](const FPGATrackSimHit*) {});
156 }
157
158 ATH_MSG_DEBUG(
"Retrieved " << phits_2nd.size() <<
" hits and " << FPGAInputTracks->size() <<
" tracks from storegate");
159
160
161 SG::ReadHandle<FPGATrackSimTruthTrackCollection> FPGATruthTracks(
m_FPGATruthTrackKey, ctx);
162 if (!FPGATruthTracks.isValid()) {
163 ATH_MSG_ERROR(
"Could not find FPGA Truth Track Collection with key " << FPGATruthTracks.key());
164 return StatusCode::FAILURE;
165 }
166
167
169 if (!FPGAOfflineTracks.isValid()) {
170 ATH_MSG_ERROR(
"Could not find FPGA Offline Track Collection with key " << FPGAOfflineTracks.key());
171 return StatusCode::FAILURE;
172 }
173
174
176 if (!FPGAEventInfo.isValid()) {
177 ATH_MSG_ERROR(
"Could not find FPGA Event Info with key " << FPGAEventInfo.key());
178 return StatusCode::FAILURE;
179 }
180 FPGATrackSimEventInfo eventInfo = *FPGAEventInfo.cptr();
182
183
184 std::vector<FPGATrackSimRoad> roads;
185
186 {
187 std::optional<Athena::Chrono> chrono;
189
191
192 for (auto const& road : roads) {
193 FPGARoads_2nd->push_back(road);
194 }
195 }
196
197 auto mon_nroads = Monitored::Scalar<unsigned>("nroads_2nd", roads.size());
198 unsigned bitmask_best(0);
199 unsigned nhit_best(0);
200 for (auto const &road : roads) {
201 unsigned bitmask = road.getHitLayers();
202 if (road.getNHitLayers() > nhit_best) {
203 nhit_best = road.getNHitLayers();
204 bitmask_best = bitmask;
205 }
207 if (bitmask & (1 << l)) {
208 auto mon_layerIDs = Monitored::Scalar<unsigned>("layerIDs_2nd",l);
209 Monitored::Group(
m_monTool,mon_layerIDs);
210 }
211 }
212 }
213
215 if (bitmask_best & (1 << l)) {
216 auto mon_layerIDs_best = Monitored::Scalar<unsigned>("layerIDs_2nd_best",l);
217 Monitored::Group(
m_monTool,mon_layerIDs_best);
218 }
219 }
221
222
223 auto mon_nroads_postfilter = Monitored::Scalar<unsigned>("nroads_2nd_postfilter", roads.size());
224 Monitored::Group(
m_monTool, mon_nroads_postfilter);
225
226
227
228 std::vector<FPGATrackSimTrack> tracks;
229 {
230 std::optional<Athena::Chrono> chrono;
236 } else {
238
240
241 std::vector<FPGATrackSimTrack> filteredTracks;
242
243 for (const auto& road : roads) {
244
245 std::vector<FPGATrackSimTrack> tracksForCurrentRoad;
246 std::vector<FPGATrackSimRoad> roadVec = {road};
248
249
250 if (!tracksForCurrentRoad.empty()) {
251 auto bestTrackIter = std::min_element(
252 tracksForCurrentRoad.begin(), tracksForCurrentRoad.end(),
253 [](
const FPGATrackSimTrack&
a,
const FPGATrackSimTrack& b) {
254 return a.getChi2ndof() < b.getChi2ndof();
255 });
256
257 if (bestTrackIter != tracksForCurrentRoad.end() && bestTrackIter->getChi2ndof() < 1.e15) {
258 filteredTracks.push_back(*bestTrackIter);
259
260
261 auto mon_chi2 = Monitored::Scalar<float>("chi2_2nd_all", bestTrackIter->getChi2ndof());
263 }
264 }
265 }
266
267
268 tracks = std::move(filteredTracks);
269
270
271 if (!tracks.empty()) {
272 float bestChi2Overall = std::min_element(
273 tracks.begin(), tracks.end(),
274 [](
const FPGATrackSimTrack&
a,
const FPGATrackSimTrack& b) {
275 return a.getChi2ndof() < b.getChi2ndof();
276 })->getChi2ndof();
277
278 auto mon_best_chi2 = Monitored::Scalar<float>("best_chi2_2nd", bestChi2Overall);
279 Monitored::Group(
m_monTool, mon_best_chi2);
280 }
281 } else {
283 float bestchi2 = 1.e15;
284 for (const FPGATrackSimTrack& track : tracks) {
286 if (
chi2 < bestchi2) bestchi2 =
chi2;
287 auto mon_chi2 = Monitored::Scalar<float>(
"chi2_2nd_all",
chi2);
289 }
290 auto mon_best_chi2 = Monitored::Scalar<float>("best_chi2_2nd", bestchi2);
291 Monitored::Group(
m_monTool, mon_best_chi2);
292 }
293 }
294 } else {
295
297 }
298 }
299 auto mon_ntracks = Monitored::Scalar<unsigned>("ntrack_2nd", tracks.size());
301
302
303 {
304 std::optional<Athena::Chrono> chrono;
307 }
308 {
309 std::optional<Athena::Chrono> chrono;
311
314 }
315 }
316 const auto& truthtracks = *FPGATruthTracks;
317 const auto& offlineTracks = *FPGAOfflineTracks;
318
319
320 {
321 std::optional<Athena::Chrono> chrono;
324 for (auto track : tracks) {
326 track.setQOverPt(truthtracks.front().getQOverPt());
328 track.setD0(truthtracks.front().getD0());
330 track.setPhi(truthtracks.front().getPhi());
332 track.setZ0(truthtracks.front().getZ0());
334 track.setEta(truthtracks.front().getEta());
335 }
336 }
337 }
338
339 unsigned ntrackOLRChi2 = 0;
340 {
341 std::optional<Athena::Chrono> chrono;
343 for (const FPGATrackSimTrack& track : tracks) {
346 if (
track.passedOR()) {
347 ntrackOLRChi2++;
349
350
351 float chi2olr =
track.getChi2ndof();
352 auto mon_chi2_or = Monitored::Scalar<float>("chi2_2nd_afterOLR", chi2olr);
353 Monitored::Group(
m_monTool, mon_chi2_or);
354 }
355 }
356 }
357 auto mon_ntracks_olr = Monitored::Scalar<unsigned>("ntrack_2nd_afterOLR", ntrackOLRChi2);
358 Monitored::Group(
m_monTool,mon_ntracks_olr);
359 }
360
363
364
365 {
366 std::optional<Athena::Chrono> chrono;
368 if (truthtracks.size() > 0) {
370 auto passroad = Monitored::Scalar<bool>("eff_road_2nd",(roads.size() > 0));
371 auto passtrack = Monitored::Scalar<bool>("eff_track_2nd",(tracks.size() > 0));
372 auto truthpT_zoom = Monitored::Scalar<float>("pT_zoom",truthtracks.front().getPt()*0.001);
373 auto truthpT = Monitored::Scalar<float>("pT",truthtracks.front().getPt()*0.001);
374 auto trutheta = Monitored::Scalar<float>("eta",truthtracks.front().getEta());
375 auto truthphi= Monitored::Scalar<float>("phi",truthtracks.front().getPhi());
376 auto truthd0= Monitored::Scalar<float>("d0",truthtracks.front().getD0());
377 auto truthz0= Monitored::Scalar<float>("z0",truthtracks.front().getZ0());
380
381 unsigned npasschi2(0);
382 unsigned npasschi2OLR(0);
383
384 if (tracks.size() > 0) {
387 for (const auto& track : tracks) {
389 npasschi2++;
390 if (
track.passedOR()) {
391 npasschi2OLR++;
392 }
393 }
394 }
395 }
400
401 auto passtrackchi2 = Monitored::Scalar<bool>("eff_track_chi2_2nd",(npasschi2 > 0));
402 Monitored::Group(
m_monTool,passroad,passtrack,truthpT_zoom,truthpT,trutheta,truthphi,truthd0,truthz0,passtrackchi2);
403 }
404 }
405
406 {
407 std::optional<Athena::Chrono> chrono;
409 for (const FPGATrackSimTrack& track : tracks) FPGATracks_2ndHandle->push_back(track);
410 }
411
412
413 {
414 std::optional<Athena::Chrono> chrono;
417 auto dataFlowInfo = std::make_unique<FPGATrackSimDataFlowInfo>();
419 }
420
424 }
425 }
426
427
430
431 return StatusCode::SUCCESS;
432}
#define ATH_CHECK
Evaluate an expression and check for errors.
#define ATH_MSG_WARNING(x)
void roadsToTrack(std::vector< FPGATrackSimRoad > &roads, std::vector< FPGATrackSimTrack > &track_cands, const FPGATrackSimPlaneMap *pmap)
ToolHandle< IFPGATrackSimTrackExtensionTool > m_trackExtensionTool
SG::WriteHandleKey< FPGATrackSimRoadCollection > m_FPGARoadKey
ServiceHandle< IChronoStatSvc > m_chrono
unsigned long m_maxNTracksTot
Gaudi::Property< float > m_trackScoreCut
SG::ReadHandleKey< FPGATrackSimOfflineTrackCollection > m_FPGAOfflineTrackKey
unsigned long m_maxNTracksChi2OLRTot
ToolHandle< GenericMonitoringTool > m_monTool
SG::WriteHandleKey< FPGATrackSimTrackCollection > m_FPGATrackKey
SG::ReadHandleKey< FPGATrackSimTrackCollection > m_FPGAInputTrackKey
SG::ReadHandleKey< FPGATrackSimTruthTrackCollection > m_FPGATruthTrackKey
Gaudi::Property< bool > m_writeOutNonSPStripHits
unsigned long m_maxNRoadsFound
FPGATrackSimLogicalEventOutputHeader * m_logicEventOutputHeader
SG::ReadHandleKey< FPGATrackSimEventInfo > m_FPGAEventInfoKey
Gaudi::Property< bool > m_doHoughRootOutput2nd
unsigned long m_maxNTracksChi2Tot
ToolHandle< FPGATrackSimHoughRootOutputTool > m_houghRootOutputTool
Gaudi::Property< bool > m_doNNTrack_2nd
Gaudi::Property< bool > m_doTracking
ServiceHandle< IFPGATrackSimEventSelectionSvc > m_evtSel
ToolHandle< FPGATrackSimNNTrackTool > m_NNTrackTool
Gaudi::Property< int > m_SetTruthParametersForTracks
FPGATrackSimLogicalEventInputHeader * m_slicedHitHeader
ToolHandle< FPGATrackSimTrackFitterTool > m_trackFitterTool
ServiceHandle< IFPGATrackSimMappingSvc > m_FPGATrackSimMapping
StatusCode writeOutputData(const std::vector< FPGATrackSimRoad > &roads_2nd, std::vector< FPGATrackSimTrack > const &tracks_2nd, FPGATrackSimDataFlowInfo const *dataFlowInfo)
Gaudi::Property< bool > m_passLowestChi2TrackOnly
long m_nTracksChi2OLRFound
ToolHandle< FPGATrackSimOverlapRemovalTool > m_overlapRemovalTool
Gaudi::Property< bool > m_writeOutputData
SG::ReadHandleKey< FPGATrackSimHitCollection > m_FPGAHitKey
double chi2(TH1 *h0, TH1 *h1)
l
Printing final latex table to .tex output file.
constexpr bool enableBenchmark