LVL1::gFexTowerSummer Class Reference

#include <gFexTowerSummer.h>

Inheritance diagram for LVL1::gFexTowerSummer:

Collaboration diagram for LVL1::gFexTowerSummer:

Public Types
typedef std::array< std::array< int, LVL1::gFEXPos::AB_COLUMNS >, LVL1::gFEXPos::ABC_ROWS >	gtFPGA

Public Member Functions
	gFexTowerSummer (const std::string &name, ISvcLocator *svc)
virtual StatusCode	initialize () override
	Function initialising the algorithm.
virtual StatusCode	execute (const EventContext &) const override
	Function executing the algorithm.
virtual StatusCode	sysInitialize () override
	Override sysInitialize.
virtual bool	isClonable () const override
	Specify if the algorithm is clonable.
virtual unsigned int	cardinality () const override
	Cardinality (Maximum number of clones that can exist) special value 0 means that algorithm is reentrant.
virtual StatusCode	sysExecute (const EventContext &ctx) override
	Execute an algorithm.
virtual const DataObjIDColl &	extraOutputDeps () const override
	Return the list of extra output dependencies.
virtual bool	filterPassed (const EventContext &ctx) const
virtual void	setFilterPassed (bool state, const EventContext &ctx) const
ServiceHandle< StoreGateSvc > &	evtStore ()
	The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.
const ServiceHandle< StoreGateSvc > &	detStore () const
	The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.
virtual StatusCode	sysStart () override
	Handle START transition.
virtual std::vector< Gaudi::DataHandle * >	inputHandles () const override
	Return this algorithm's input handles.
virtual std::vector< Gaudi::DataHandle * >	outputHandles () const override
	Return this algorithm's output handles.
Gaudi::Details::PropertyBase &	declareProperty (Gaudi::Property< T, V, H > &t)
void	updateVHKA (Gaudi::Details::PropertyBase &)
MsgStream &	msg () const
bool	msgLvl (const MSG::Level lvl) const

Protected Member Functions
void	renounceArray (SG::VarHandleKeyArray &handlesArray)
	remove all handles from I/O resolution
std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void >	renounce (T &h)
void	extraDeps_update_handler (Gaudi::Details::PropertyBase &ExtraDeps)
	Add StoreName to extra input/output deps as needed.

Private Types
typedef ServiceHandle< StoreGateSvc >	StoreGateSvc_t

Private Member Functions
StatusCode	gtReconstructABC (const EventContext &ctx, unsigned int XFPGA, gtFPGA &XgtF, gtFPGA &Xgt, gtFPGA &Xsaturation) const
void	undoMLE (int &datumPtr) const
void	signExtend (int *xptr, int upto) const
void	getEtaPhi (float &Eta, float &Phi, int iEta, int iPhi, int gFEXtowerID) const
Gaudi::Details::PropertyBase &	declareGaudiProperty (Gaudi::Property< T, V, H > &hndl, const SG::VarHandleKeyType &)
	specialization for handling Gaudi::Property<SG::VarHandleKey>

Private Attributes
SG::ReadHandleKey< xAOD::gFexTowerContainer >	m_gFexFiberTowersReadKey
SG::WriteHandleKey< xAOD::gFexTowerContainer >	m_gTowersWriteKey
SG::WriteHandleKey< xAOD::gFexTowerContainer >	m_gTowers50WriteKey
SG::WriteHandleKey< xAOD::gFexTowerContainer >	m_gTowersEMWriteKey
SG::WriteHandleKey< xAOD::gFexTowerContainer >	m_gTowersHADWriteKey
DataObjIDColl	m_extendedExtraObjects
	Extra output dependency collection, extended by AthAlgorithmDHUpdate to add symlinks.
StoreGateSvc_t	m_evtStore
	Pointer to StoreGate (event store by default)
StoreGateSvc_t	m_detStore
	Pointer to StoreGate (detector store by default)
std::vector< SG::VarHandleKeyArray * >	m_vhka
bool	m_varHandleArraysDeclared

Detailed Description

Definition at line 31 of file gFexTowerSummer.h.

Member Typedef Documentation

gtFPGA

typedef std::array<std::array<int, LVL1::gFEXPos::AB_COLUMNS>, LVL1::gFEXPos::ABC_ROWS> LVL1::gFexTowerSummer::gtFPGA

Definition at line 41 of file gFexTowerSummer.h.

StoreGateSvc_t

typedef ServiceHandle<StoreGateSvc> AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::StoreGateSvc_t

privateinherited

Definition at line 388 of file AthCommonDataStore.h.

Constructor & Destructor Documentation

gFexTowerSummer()

LVL1::gFexTowerSummer::gFexTowerSummer	(	const std::string &	name,
		ISvcLocator *	svc )

Definition at line 28 of file gFexTowerSummer.cxx.

    : AthReentrantAlgorithm(name, svc) {}

Member Function Documentation

cardinality()

unsigned int AthCommonReentrantAlgorithm< Gaudi::Algorithm >::cardinality ( ) const

overridevirtualinherited

Cardinality (Maximum number of clones that can exist) special value 0 means that algorithm is reentrant.

Override this to return 0 for reentrant algorithms.

Definition at line 75 of file AthCommonReentrantAlgorithm.cxx.

{
  return 0;
}

declareGaudiProperty()

Gaudi::Details::PropertyBase & AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::declareGaudiProperty ( Gaudi::Property< T, V, H > & hndl, const SG::VarHandleKeyType &  )

inlineprivateinherited

specialization for handling Gaudi::Property<SG::VarHandleKey>

Definition at line 156 of file AthCommonDataStore.h.

  {
    return *AthCommonDataStore<PBASE>::declareProperty(hndl.name(),
                                                       hndl.value(), 
                                                       hndl.documentation());
 
  }

declareProperty()

Gaudi::Details::PropertyBase & AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::declareProperty ( Gaudi::Property< T, V, H > & t )

inlineinherited

Definition at line 145 of file AthCommonDataStore.h.

                                                                     {
    typedef typename SG::HandleClassifier<T>::type htype;
    return AthCommonDataStore<PBASE>::declareGaudiProperty(t, htype());
  }

detStore()

const ServiceHandle< StoreGateSvc > & AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::detStore ( ) const

inlineinherited

The standard StoreGateSvc/DetectorStore Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 95 of file AthCommonDataStore.h.

{ return m_detStore; }

evtStore()

ServiceHandle< StoreGateSvc > & AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::evtStore ( )

inlineinherited

The standard StoreGateSvc (event store) Returns (kind of) a pointer to the StoreGateSvc.

Definition at line 85 of file AthCommonDataStore.h.

{ return m_evtStore; }

execute()

StatusCode LVL1::gFexTowerSummer::execute ( const EventContext & ctx ) const

overridevirtual

Function executing the algorithm.

Definition at line 49 of file gFexTowerSummer.cxx.

                                                                 {
 
  // WriteHandle for gFEX Input Towers
  SG::WriteHandle<xAOD::gFexTowerContainer> gTowersContainer(m_gTowersWriteKey, ctx);
  ATH_CHECK( gTowersContainer.record(std::make_unique<xAOD::gFexTowerContainer>(), std::make_unique<xAOD::gFexTowerAuxContainer>()));
  ATH_MSG_DEBUG("Recorded gFexEmulatedTower 200 MeV container with key "<< gTowersContainer.key());
 
  SG::WriteHandle<xAOD::gFexTowerContainer> gTowers50Container(m_gTowers50WriteKey, ctx);
  ATH_CHECK( gTowers50Container.record(std::make_unique<xAOD::gFexTowerContainer>(), std::make_unique<xAOD::gFexTowerAuxContainer>()));
  ATH_MSG_DEBUG("Recorded gFexEmulatedTower 50 MeV container with key "<< gTowers50Container.key());
 
  xAOD::gFexTowerContainer*  gTowersEMContainerPtr = nullptr;
  xAOD::gFexTowerContainer*  gTowersHADContainerPtr = nullptr;
  SG::WriteHandle<xAOD::gFexTowerContainer> gTowersEMContainer = (!m_gTowersEMWriteKey.empty()) ? SG::WriteHandle<xAOD::gFexTowerContainer>(m_gTowersEMWriteKey, ctx) : SG::WriteHandle<xAOD::gFexTowerContainer>();
  SG::WriteHandle<xAOD::gFexTowerContainer> gTowersHADContainer = (!m_gTowersHADWriteKey.empty()) ? SG::WriteHandle<xAOD::gFexTowerContainer>(m_gTowersHADWriteKey, ctx) : SG::WriteHandle<xAOD::gFexTowerContainer>();
 
  if (!m_gTowersEMWriteKey.empty()) {
    ATH_CHECK( gTowersEMContainer.record(std::make_unique<xAOD::gFexTowerContainer>(), std::make_unique<xAOD::gFexTowerAuxContainer>()));
    ATH_MSG_DEBUG("Recorded gFexEmulatedTower 200 MeV EM container with key "<< m_gTowersEMWriteKey.key());
    gTowersEMContainerPtr = &*gTowersEMContainer;
  }
  if (!m_gTowersHADWriteKey.empty()) {
    ATH_CHECK( gTowersHADContainer.record(std::make_unique<xAOD::gFexTowerContainer>(), std::make_unique<xAOD::gFexTowerAuxContainer>()));
    ATH_MSG_DEBUG("Recorded gFexEmulatedTower 200 MeV HAD container with key "<< m_gTowersHADWriteKey.key());
    gTowersHADContainerPtr = &*gTowersHADContainer;
  }
 
  // Atwr, Btwr, Ctwr will contain gTowers towers for each FPGA
  gtFPGA Atwr  = {{{0}}};
  gtFPGA Btwr  = {{{0}}};
  gtFPGA Ctwr  = {{{0}}};
  
  gtFPGA AtwrF  = {{{0}}};
  gtFPGA BtwrF  = {{{0}}};
  gtFPGA CtwrF  = {{{0}}};
  
  gtFPGA Asatur  = {{{0}}};
  gtFPGA Bsatur  = {{{0}}};
  gtFPGA Csatur  = {{{0}}};
 
  for(int irow=0; irow<LVL1::gFEXPos::ABC_ROWS; irow++){
    for(int icolumn=0; icolumn<LVL1::gFEXPos::AB_COLUMNS; icolumn++){
      Atwr[irow][icolumn] = 0;
      AtwrF[irow][icolumn] = 0;
      Asatur[irow][icolumn] = 0;
      Btwr[irow][icolumn] = 0;
      BtwrF[irow][icolumn] = 0;
      Bsatur[irow][icolumn] = 0;
      Ctwr[irow][icolumn] = 0;
      CtwrF[irow][icolumn] = 0;
      Csatur[irow][icolumn] = 0;      
    }
  }
 
  // reconstruct the gTowers/saturation
  ATH_CHECK( gtReconstructABC(ctx, 0, AtwrF, Atwr, Asatur));
  ATH_CHECK( gtReconstructABC(ctx, 1, BtwrF, Btwr, Bsatur));
  ATH_CHECK( gtReconstructABC(ctx, 2, CtwrF, Ctwr, Csatur));  
  
 
  // Write the towers
  int iEta = 0;
  int iPhi = 0;
  float Eta = 0;
  float Phi = 0;
  int Et  = 0;
  int EtF  = 0;
  int Fpga = 0;
  char IsSaturated = 0;
  int towerID = 0;
 
  // Assign ID based on FPGA (FPGA-A 0->0; FPGA-B 1->10000, FPGA-C 2->20000) and gTower number assigned as per firmware convention
 
  int twr_rows = Atwr.size(); // 32
  int twr_cols = Atwr[0].size(); // 12
 
  Fpga = 0;
 
  // Save towers from FPGA A in gTower EDM
  for (int irow = 0; irow < twr_rows; irow++){
    for (int icol = 0; icol < twr_cols; icol++){
      iEta = icol + 8;
      iPhi = irow;
      Et = Atwr[irow][icol];
      EtF = AtwrF[irow][icol];
      IsSaturated = Asatur[irow][icol];
      getEtaPhi(Eta, Phi, iEta, iPhi, towerID);
      gTowersContainer->push_back( std::make_unique<xAOD::gFexTower>() );
      gTowersContainer->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
      gTowers50Container->push_back( std::make_unique<xAOD::gFexTower>() );
      gTowers50Container->back()->initialize(iEta, iPhi, Eta, Phi, EtF, Fpga, IsSaturated, towerID);
      if (gTowersEMContainerPtr) {
        gTowersEMContainerPtr->push_back( std::make_unique<xAOD::gFexTower>() );
        gTowersEMContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
      }
      if (gTowersHADContainerPtr) {
        gTowersHADContainerPtr->push_back( std::make_unique<xAOD::gFexTower>() );
        gTowersHADContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
      }
      towerID += 1;
  
    }
  }
    
  // Save towers from FPGA B in gTower EDM
  Fpga = 1;
  towerID = 10000;
  // Save towers from FPGA B in gTower EDM             
  for (int irow = 0; irow < twr_rows; irow++){
    for (int icol = 0; icol < twr_cols; icol++){
      iEta = icol + 20;
      iPhi = irow;
      Et = Btwr[irow][icol];
      EtF = BtwrF[irow][icol];
      IsSaturated = Bsatur[irow][icol];
      getEtaPhi(Eta, Phi, iEta, iPhi, towerID);
      gTowersContainer->push_back( std::make_unique<xAOD::gFexTower>() );
      gTowersContainer->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID); 
      gTowers50Container->push_back( std::make_unique<xAOD::gFexTower>() );
      gTowers50Container->back()->initialize(iEta, iPhi, Eta, Phi, EtF, Fpga, IsSaturated, towerID);
      if (gTowersEMContainerPtr) {
        gTowersEMContainerPtr->push_back( std::make_unique<xAOD::gFexTower>() );
        gTowersEMContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
      }
      if (gTowersHADContainerPtr) {
        gTowersHADContainerPtr->push_back( std::make_unique<xAOD::gFexTower>() );
        gTowersHADContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
      }
      towerID += 1;    
    }
  }
  
  // Save towers from FPGA C in gTower EDM
  Fpga = 2;
  towerID = 20000;
  for (int irow = 0; irow < twr_rows; irow++){
    for (int icol = 0; icol < twr_cols/2; icol++){                
      iEta = icol + 2;
      iPhi = irow;
      Et = Ctwr[irow][icol];
      EtF = CtwrF[irow][icol];
      IsSaturated = Csatur[irow][icol];
      getEtaPhi(Eta, Phi, iEta, iPhi, towerID);
      gTowersContainer->push_back( std::make_unique<xAOD::gFexTower>() );
      gTowersContainer->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
      gTowers50Container->push_back( std::make_unique<xAOD::gFexTower>() );
      gTowers50Container->back()->initialize(iEta, iPhi, Eta, Phi, EtF, Fpga, IsSaturated, towerID);
      if (gTowersEMContainerPtr) {
        gTowersEMContainerPtr->push_back( std::make_unique<xAOD::gFexTower>() );
        gTowersEMContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
      }
      if (gTowersHADContainerPtr) {
        gTowersHADContainerPtr->push_back( std::make_unique<xAOD::gFexTower>() );
        gTowersHADContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
      }
      towerID += 1;   
    }
    for (int icol = twr_cols/2; icol < twr_cols; icol++){                
      iEta = icol + 26;
      iPhi = irow;
      Et = Ctwr[irow][icol];
      EtF = CtwrF[irow][icol];
      IsSaturated = Csatur[irow][icol];
      getEtaPhi(Eta, Phi, iEta, iPhi, towerID);
      gTowersContainer->push_back( std::make_unique<xAOD::gFexTower>() );
      gTowersContainer->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
      gTowers50Container->push_back( std::make_unique<xAOD::gFexTower>() );
      gTowers50Container->back()->initialize(iEta, iPhi, Eta, Phi, EtF, Fpga, IsSaturated, towerID);
      if (gTowersEMContainerPtr) {
        gTowersEMContainerPtr->push_back( std::make_unique<xAOD::gFexTower>() );
        gTowersEMContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
      }
      if (gTowersHADContainerPtr) {
        gTowersHADContainerPtr->push_back( std::make_unique<xAOD::gFexTower>() );
        gTowersHADContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
      }
      towerID += 1;      
    }
  }
 
  return StatusCode::SUCCESS;
}

extraDeps_update_handler()

void AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::extraDeps_update_handler ( Gaudi::Details::PropertyBase & ExtraDeps )

protectedinherited

Add StoreName to extra input/output deps as needed.

use the logic of the VarHandleKey to parse the DataObjID keys supplied via the ExtraInputs and ExtraOuputs Properties to add the StoreName if it's not explicitly given

extraOutputDeps()

const DataObjIDColl & AthCommonReentrantAlgorithm< Gaudi::Algorithm >::extraOutputDeps ( ) const

overridevirtualinherited

Return the list of extra output dependencies.

This list is extended to include symlinks implied by inheritance relations.

Definition at line 94 of file AthCommonReentrantAlgorithm.cxx.

{
  // If we didn't find any symlinks to add, just return the collection
  // from the base class.  Otherwise, return the extended collection.
  if (!m_extendedExtraObjects.empty()) {
    return m_extendedExtraObjects;
  }
  return BaseAlg::extraOutputDeps();
}

filterPassed()

virtual bool AthCommonReentrantAlgorithm< Gaudi::Algorithm >::filterPassed ( const EventContext & ctx ) const

inlinevirtualinherited

Definition at line 96 of file AthCommonReentrantAlgorithm.h.

                                                           {
    return execState( ctx ).filterPassed();
  }

getEtaPhi()

void LVL1::gFexTowerSummer::getEtaPhi ( float & Eta, float & Phi, int iEta, int iPhi, int gFEXtowerID ) const

private

Definition at line 675 of file gFexTowerSummer.cxx.

                                                        {
 
  float s_centralPhiWidth =
      (2 * M_PI) / 32;  // In central region, gFex has 32 bins in phi
  float s_forwardPhiWidth =
      (2 * M_PI) / 16;  // In forward region, gFex has 16 bins in phi (before
                        // rearranging bins)
 
  const std::vector<float> s_EtaCenter = {
      -4.5, -3.8, -3.38, -3.18, -3.15, -3,   -2.8, -2.6, -2.35, -2.1,
      -1.9, -1.7, -1.5,  -1.3,  -1.1,  -0.9, -0.7, -0.5, -0.3,  -0.1,
      0.1,  0.3,  0.5,   0.7,   0.9,   1.1,  1.3,  1.5,  1.7,   1.9,
      2.1,  2.35, 2.6,   2.8,   3.0,   3.15, 3.18, 3.38, 3.8,   4.5};
 
  // Transform Eta and Phi indices for the most forward towers into the
  // "original" indices, as before rearranging the towers such that the forward
  // region is 12(ieta)x32(iphi). The FPGA-C has now the same format (12*32) as
  // FPGA-A and FPGA-B. This is the result of a transformation in the firmware.
  // Note that for the most forward towers, the Phi index and Eta index have
  // been considered accordingly, so in order to get the correct float values of
  // Phi and Eta we need to retrieve the "original" indices.
  int towerID_base = 20000;
  int iEtaOld = 0, iPhiOld = 0;
 
  if (iEta == 2) {
    if (iPhi == ((gFEXtowerID - towerID_base) / 24) * 2) {
      iEtaOld = 0;
      iPhiOld = iPhi / 2;
    }
    if (iPhi == (((gFEXtowerID - towerID_base - 12) / 24) * 2) + 1) {
      iEtaOld = 1;
      iPhiOld = (iPhi - 1) / 2;
    }
  }
 
  else if (iEta == 3) {
    if (iPhi == ((gFEXtowerID - towerID_base - 1) / 24) * 2) {
      iEtaOld = 2;
      iPhiOld = iPhi / 2;
    }
    if (iPhi == (((gFEXtowerID - towerID_base - 13) / 24) * 2) + 1) {
      iEtaOld = 3;
      iPhiOld = (iPhi - 1) / 2;
    }
  }
 
  else if (iEta == 36) {
    if (iPhi == (((gFEXtowerID - towerID_base - 22) / 24) * 2) + 1) {
      iEtaOld = 36;
      iPhiOld = (iPhi - 1) / 2;
    }
    if (iPhi == ((gFEXtowerID - towerID_base - 10) / 24) * 2) {
      iEtaOld = 37;
      iPhiOld = iPhi / 2;
    }
  }
 
  else if (iEta == 37) {
    if (iPhi == (((gFEXtowerID - towerID_base - 23) / 24) * 2) + 1) {
      iEtaOld = 38;
      iPhiOld = (iPhi - 1) / 2;
    }
    if (iPhi == ((gFEXtowerID - towerID_base - 11) / 24) * 2) {
      iEtaOld = 39;
      iPhiOld = iPhi / 2;
    }
  }
 
  else {
    iEtaOld = iEta;
    iPhiOld = iPhi;
  }
 
  Eta = s_EtaCenter[iEtaOld];
 
  float Phi_gFex = -99;
 
  if ((iEtaOld <= 3) || ((iEtaOld >= 36))) {
    Phi_gFex = ((iPhiOld * s_forwardPhiWidth) + s_forwardPhiWidth / 2);
  } else {
    Phi_gFex = ((iPhiOld * s_centralPhiWidth) + s_centralPhiWidth / 2);
  }
 
  if (Phi_gFex < M_PI) {
    Phi = Phi_gFex;
  } else {
    Phi = (Phi_gFex - 2 * M_PI);
  }
}

gtReconstructABC()

StatusCode LVL1::gFexTowerSummer::gtReconstructABC ( const EventContext & ctx, unsigned int XFPGA, gtFPGA & XgtF, gtFPGA & Xgt, gtFPGA & Xsaturation ) const

private

Definition at line 233 of file gFexTowerSummer.cxx.

                                                    {
 
  // Loop over the Fiber Towers and fill gTower arrays as per original byte stream decoder
  
  // Reading the Fiber Tower container
  SG::ReadHandle<xAOD::gFexTowerContainer> gFexFiberTowerContainer(m_gFexFiberTowersReadKey, ctx);
  if (!gFexFiberTowerContainer.isValid()) {
    ATH_MSG_ERROR("Could not retrieve Fiber tower collection "
                  << gFexFiberTowerContainer.key());
    return StatusCode::FAILURE;
  }
 
  if (gFexFiberTowerContainer->empty()) {
    ATH_MSG_WARNING("Cannot fill gTowers here, fiber container is empty. "
            << gFexFiberTowerContainer->size());
    return StatusCode::SUCCESS;
  }
  
  // Zero the input gTower sums/saturation
  for(int irow=0; irow<LVL1::gFEXPos::ABC_ROWS; irow++){
    for(int icolumn=0; icolumn<LVL1::gFEXPos::AB_COLUMNS; icolumn++){
      Xgt[irow][icolumn] = 0;
      XgtF[irow][icolumn] = 0;
      Xsaturation[irow][icolumn] = 0;
    }
  }
 
  // Energy arrays for the EM and hadronic in standard and extra eta regions
  // 200 MeV towers
  std::array<int, LVL1::gFEXPos::AB_TOWERS> etowerData{}; // 384
  std::array<int, LVL1::gFEXPos::AB_TOWERS> htowerData{};
  std::array<int, LVL1::gFEXPos::ABC_ROWS>  xetowerData{}; // 32
  std::array<int, LVL1::gFEXPos::ABC_ROWS>  xhtowerData{};
  std::array<int, LVL1::gFEXPos::ABC_ROWS>  ohtowerData{};
  
  // 50 MeV towers
  std::array<int, LVL1::gFEXPos::AB_TOWERS> etowerDataF{};
  std::array<int, LVL1::gFEXPos::AB_TOWERS> htowerDataF{};
  std::array<int, LVL1::gFEXPos::ABC_ROWS>  xetowerDataF{};
  std::array<int, LVL1::gFEXPos::ABC_ROWS>  xhtowerDataF{};
  std::array<int, LVL1::gFEXPos::ABC_ROWS>  ohtowerDataF{};
 
  // saturation
  std::array<bool, LVL1::gFEXPos::AB_TOWERS> saturationData{}; // 384
 
  // loop over the Fiber towers, and fill the tower energy arrays 
  for(const xAOD::gFexTower* gfexFiberTower : *gFexFiberTowerContainer){
    // first match the FPGA
    unsigned int fiberTowerFpga = gfexFiberTower->fpga();
    if (fiberTowerFpga != XFPGA) continue;
 
    // working with "local" fiber number, iFiber
    unsigned int fiberTowerId = gfexFiberTower->gFEXtowerID();
    unsigned int offset = (XFPGA == 2) ? 20000 : (XFPGA == 1) ? 10000 : 0;
    unsigned int iFiber = (fiberTowerId - offset)/16;
 
    // Do not exceed maximum number of fibers for FPGA
    unsigned int maxFiberN =  (XFPGA == 2) ? LVL1::gFEXPos::C_FIBERS : LVL1::gFEXPos::AB_FIBERS;
    if (iFiber >= maxFiberN) continue;
    
    ATH_MSG_DEBUG(" accessing " << fiberTowerId << " " << XFPGA << " " << offset << " " << iFiber);
    
    unsigned int iDatum = fiberTowerId%16;
   
    int fiber_type  = (XFPGA == 0) ? LVL1::gFEXPos::AMPD_NFI[iFiber] :
      (XFPGA == 1) ? LVL1::gFEXPos::BMPD_NFI[iFiber] : LVL1::gFEXPos::CMPD_NFI[iFiber];
 
    // tells where the data is coming from
    // -  0 - EMB, EMB/EMEC -> EM contribution
    // -  1 - TREX,HEC - Had contribution     
    // -  2 - extended region ( EMEC)         
    // -  3 - extended region ( HEC)
    // -  6 - 200MeV region only ( HEC)
    // - 11 - HEC - Had contribution
 
    int dataType = (XFPGA == 0) ? LVL1::gFEXPos::AMPD_DTYP_ARR[fiber_type][iDatum] :
      (XFPGA == 1) ? LVL1::gFEXPos::BMPD_DTYP_ARR[fiber_type][iDatum] :
      LVL1::gFEXPos::CMPD_DTYP_ARR[fiber_type][iDatum];
 
    // tower number 0 - 383
    int ntower = (XFPGA == 0) ? LVL1::gFEXPos::AMPD_GTRN_ARR[iFiber][iDatum] :
      (XFPGA == 1) ? LVL1::gFEXPos::BMPD_GTRN_ARR[iFiber][iDatum] :
      LVL1::gFEXPos::CMPD_GTRN_ARR[iFiber][iDatum];
    
    // calo type
    // FPGA 0/1 0,1,2
    // FPGA 2   3
    int caloType = (XFPGA == 0) ? LVL1::gFEXPos::ACALO_TYPE[iFiber] :
      (XFPGA == 1) ? LVL1::gFEXPos::BCALO_TYPE[iFiber] : LVL1::gFEXPos::CCALO_TYPE[iFiber]; 
 
    // saturation
    bool fiberSaturation = (bool)(gfexFiberTower->isSaturated());
    if (fiberSaturation) {
      saturationData[ntower] = fiberSaturation;
    }
 
    // Get the MLE from the EDM (stored as float)
    unsigned int Toweret_mle = (unsigned int)(gfexFiberTower->towerEt());
 
    // FPGA 0/1
    if(caloType < 3) {
      switch(dataType){
      case 0:
  etowerData[ntower] = Toweret_mle;
  undoMLE( etowerData[ntower] );
  etowerDataF[ntower] = etowerData[ntower];
  break;
      case 1:
  htowerData[ntower] = Toweret_mle;
  
  // mulitply by 20 to make 50 MeV LSB
  // include this here before mulitplication by 20 
  htowerData[ntower]  = 20*htowerData[ntower];
  htowerDataF[ntower] =  htowerData[ntower];
  break;
 
      case 2:
  xetowerData[ntower] = Toweret_mle;
  undoMLE( xetowerData[ntower] );
  xetowerDataF[ntower]       = xetowerData[ntower];
  break;
    
      case 3:
  xhtowerData[ntower] = Toweret_mle;
  undoMLE( xhtowerData[ntower] );
  xhtowerDataF[ntower]       = xhtowerData[ntower];
    break;
    
      case 6:
    ohtowerData[ntower] = Toweret_mle; 
    undoMLE( ohtowerData[ntower] );
    ohtowerDataF[ntower]       =  ohtowerData[ntower];
    break;
 
      case 11:
    htowerData[ntower] = Toweret_mle; 
    undoMLE( htowerData[ntower] );
    htowerDataF[ntower] = htowerData[ntower];
    break;
      }
    } else {
 
      // this is FPGA C
      // only types 2 and 3 exist in FPGA C    
      switch(dataType){ 
      case 2:
    // 
    etowerData[ntower] = Toweret_mle;
    undoMLE( etowerData[ntower] );
    etowerDataF[ntower] = etowerData[ntower]; 
 
    break;
        
      case 3:
    htowerData[ntower] = Toweret_mle;   
    undoMLE( htowerData[ntower] );
    htowerDataF[ntower] = htowerData[ntower];
    break;
 
      case 15:
    break;
 
      case 99:
    break; 
        
      default:
    ATH_MSG_ERROR("Tower with unknown datatype "
              << dataType);
    return StatusCode::FAILURE;
 
      }         
    } // end of case statement for FPGAC 
 
    ATH_MSG_DEBUG(" end of loop: " << XFPGA << " tower: " << ntower << " e " << etowerDataF[ntower] << " h " << htowerData[ntower] << " fibertower " << fiberTowerId);
    
  } // end of loop over fiber towers    
 
  // Sum the energy arrays into the output gTowers
  if( XFPGA == 0 ) {
    for(int itower=0;itower<384;itower++){
      int icolumn = itower%12;
      int irow    =  itower/12;
 
      // saturation
      Xsaturation[irow][icolumn] = saturationData[itower];
 
      
      // 50 MeV towers 
      int xF = etowerDataF[itower] + htowerDataF[itower];
      // 200 MeV towers 
      int x   = ( (etowerData[itower]>>2) + (htowerData[itower]>>2) );
      
      ATH_MSG_DEBUG("sss1 " << icolumn << " " << irow << " " << xF << " " << x << " " <<  etowerDataF[itower] <<"  " << htowerDataF[itower]);
 
      signExtend(&xF,18);
      signExtend(&x,18);
 
      ATH_MSG_DEBUG("sss2 " << icolumn << " " << irow << " " << xF << " " << x);
        
      Xgt[irow][icolumn]  = x;
      XgtF[irow][icolumn] = xF;
 
      ATH_MSG_DEBUG("sss3 " << icolumn << " " << irow << " " << XgtF[irow][icolumn] << " " <<  Xgt[irow][icolumn]);
    
      // eta  region in FPGA A  (eta ~ -2.5)
      if ( icolumn == 0) {
        int xx =  ( (xetowerData[irow]>>2) + (xhtowerData[irow]>>2) );
        signExtend(&xx,18);
        Xgt[irow][icolumn]  = Xgt[irow][icolumn]  + xx;
        ATH_MSG_DEBUG("sss4 " << icolumn << " " << irow << " " << XgtF[irow][icolumn] << " " <<  Xgt[irow][icolumn]);
      }
 
      if ( icolumn == 4) {
        // 200 MeV towers
        int ox =  (ohtowerData[irow] >> 2 ) ;
        signExtend(&ox,18);
        Xgt[irow][icolumn]  = Xgt[irow][icolumn]   + ox ;
        ATH_MSG_DEBUG("sss5 " << icolumn << " " << irow << " " << XgtF[irow][icolumn] << " " <<  Xgt[irow][icolumn]);
      }
      
      ATH_MSG_DEBUG("sss filling standard " << Xgt[irow][icolumn]  << " fiber " << XgtF[irow][icolumn]);
    }
  }
  else if ( XFPGA == 1 ) {
    for(int itower=0;itower<384;itower++){
      int icolumn = itower%12;
      int irow    =  itower/12;
 
      // saturation
      Xsaturation[irow][icolumn] = saturationData[itower];
      
      // 50 MeV towers
      int xF =  etowerDataF[itower]  +  htowerDataF[itower] ;
      // 200 MeV towers 
      int x  =  ( (etowerData[itower]>>2) +  (htowerData[itower] >> 2) );
      
      signExtend(&xF,18);
      signExtend(&x,18);
      
      Xgt[irow][icolumn]  = x;
      XgtF[irow][icolumn] = xF;
      
      // extra region FPGA B (eta ~ 2.5) 
      if ( icolumn == 11) {
        // 200 MeV towers 
        int xx = ( (xetowerData[irow]>>2) + (xhtowerData[irow]>>2) );
        signExtend(&xx,18);
        Xgt[irow][icolumn]  = Xgt[irow][icolumn]  + xx;
      }
      if ( icolumn == 7 ) {
        // 200 MeV towers
        int xo =  ohtowerData[irow]>>2;
        signExtend(&xo,18);
        Xgt[irow][icolumn]  = Xgt[irow][icolumn]   + xo;
      }
    }
  }
  else if ( XFPGA == 2 ) {
    for(int itower=0;itower<384;itower++){
      int icolumn = itower%12;
      int irow    =  itower/12;
 
      // saturation
      Xsaturation[irow][icolumn] = saturationData[itower];
      
      // 50 MeV towers 
      int xF =   etowerDataF[itower] + htowerDataF[itower] ;
      // 200 MeV towers 
      int x =  ( (etowerData[itower]>>2 ) + (htowerData[itower]>>2));
      signExtend(&xF,18);
      signExtend(&x,18);
    
      Xgt[irow][icolumn] = x;
      XgtF[irow][icolumn] = xF;
    }
  } 
  
  return StatusCode::SUCCESS;
}

initialize()

StatusCode LVL1::gFexTowerSummer::initialize ( )

overridevirtual

Function initialising the algorithm.

Definition at line 31 of file gFexTowerSummer.cxx.

                                       {
 
  ATH_MSG_INFO(
      "Initializing L1CaloFEXAlgos/gFexEmulatedTowers algorithm with name: "
      << name());
  ATH_MSG_INFO("Writing into SG key: " << m_gTowersWriteKey);
 
  // initialise keys
  ATH_CHECK( m_gFexFiberTowersReadKey.initialize());
  ATH_CHECK( m_gTowersWriteKey.initialize() );
  ATH_CHECK( m_gTowers50WriteKey.initialize() );  
 
  ATH_CHECK( m_gTowersEMWriteKey.initialize(SG::AllowEmpty));
  ATH_CHECK( m_gTowersHADWriteKey.initialize(SG::AllowEmpty));  
  
  return StatusCode::SUCCESS;
}

inputHandles()

virtual std::vector< Gaudi::DataHandle * > AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::inputHandles ( ) const

overridevirtualinherited

Return this algorithm's input handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

isClonable()

bool AthCommonReentrantAlgorithm< Gaudi::Algorithm >::isClonable ( ) const

overridevirtualinherited

Specify if the algorithm is clonable.

Reentrant algorithms are clonable.

Reimplemented in InDet::GNNSeedingTrackMaker, InDet::SCT_Clusterization, InDet::SiSPGNNTrackMaker, InDet::SiSPSeededTrackFinder, InDet::SiTrackerSpacePointFinder, ITkPixelCablingAlg, ITkStripCablingAlg, RoIBResultToxAOD, SCT_ByteStreamErrorsTestAlg, SCT_CablingCondAlgFromCoraCool, SCT_CablingCondAlgFromText, SCT_ConditionsParameterTestAlg, SCT_ConditionsSummaryTestAlg, SCT_ConfigurationConditionsTestAlg, SCT_FlaggedConditionTestAlg, SCT_LinkMaskingTestAlg, SCT_MajorityConditionsTestAlg, SCT_ModuleVetoTestAlg, SCT_MonitorConditionsTestAlg, SCT_PrepDataToxAOD, SCT_RawDataToxAOD, SCT_ReadCalibChipDataTestAlg, SCT_ReadCalibDataTestAlg, SCT_RODVetoTestAlg, SCT_SensorsTestAlg, SCT_SiliconConditionsTestAlg, SCT_StripVetoTestAlg, SCT_TdaqEnabledTestAlg, SCT_TestCablingAlg, SCTEventFlagWriter, SCTRawDataProvider, SCTSiLorentzAngleTestAlg, SCTSiPropertiesTestAlg, and Simulation::BeamEffectsAlg.

Definition at line 68 of file AthCommonReentrantAlgorithm.cxx.

{
  // Reentrant algorithms are clonable.
  return true;
}

msg()

MsgStream & AthCommonMsg< Gaudi::Algorithm >::msg ( ) const

inlineinherited

Definition at line 24 of file AthCommonMsg.h.

                                {
    return this->msgStream();
  }

msgLvl()

bool AthCommonMsg< Gaudi::Algorithm >::msgLvl ( const MSG::Level lvl ) const

inlineinherited

Definition at line 30 of file AthCommonMsg.h.

                                               {
    return this->msgLevel(lvl);
  }

outputHandles()

virtual std::vector< Gaudi::DataHandle * > AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::outputHandles ( ) const

overridevirtualinherited

Return this algorithm's output handles.

We override this to include handle instances from key arrays if they have not yet been declared. See comments on updateVHKA.

renounce()

std::enable_if_t< std::is_void_v< std::result_of_t< decltype(&T::renounce)(T)> > &&!std::is_base_of_v< SG::VarHandleKeyArray, T > &&std::is_base_of_v< Gaudi::DataHandle, T >, void > AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::renounce ( T & h )

inlineprotectedinherited

Definition at line 380 of file AthCommonDataStore.h.

  {
    h.renounce();
    PBASE::renounce (h);
  }

renounceArray()

void AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::renounceArray ( SG::VarHandleKeyArray & handlesArray )

inlineprotectedinherited

remove all handles from I/O resolution

Definition at line 364 of file AthCommonDataStore.h.

                                                          {
    handlesArray.renounce();
  }

setFilterPassed()

virtual void AthCommonReentrantAlgorithm< Gaudi::Algorithm >::setFilterPassed ( bool state, const EventContext & ctx ) const

inlinevirtualinherited

Definition at line 100 of file AthCommonReentrantAlgorithm.h.

                                                                            {
    execState( ctx ).setFilterPassed( state );
  }

signExtend()

void LVL1::gFexTowerSummer::signExtend ( int * xptr, int upto ) const

private

Definition at line 657 of file gFexTowerSummer.cxx.

                                                         {
 
  // sign extend x to 32 bits assuming a hardware word length upto+1 bits (e.g. for 16 bit word upto should be 15 as in firmware) 
  // xptr pointer to input datum
  // word length in hardware 
  int x = *xptr; 
  //printf("before %x \n", x);
  //printf("masks %x %x  \n", (0x00000001<<upto) , (0xFFFFFFFF<<(upto+1))  );
  if( x & (0x00000001<<upto) ) {
    x = ( x | (0xFFFFFFFF<<(upto+1)) );
  } else {
    // for now assume 17 bits -- but could be up to 18 bits 
    x = ( x & 0x000FFFF); 
  }
  *xptr = x; 
  
}  

sysExecute()

StatusCode AthCommonReentrantAlgorithm< Gaudi::Algorithm >::sysExecute ( const EventContext & ctx )

overridevirtualinherited

Execute an algorithm.

We override this in order to work around an issue with the Algorithm base class storing the event context in a member variable that can cause crashes in MT jobs.

Definition at line 85 of file AthCommonReentrantAlgorithm.cxx.

{
  return BaseAlg::sysExecute (ctx);
}

sysInitialize()

StatusCode AthCommonReentrantAlgorithm< Gaudi::Algorithm >::sysInitialize ( )

overridevirtualinherited

Override sysInitialize.

Override sysInitialize from the base class.

Loop through all output handles, and if they're WriteCondHandles, automatically register them and this Algorithm with the CondSvc

Scan through all outputHandles, and if they're WriteCondHandles, register them with the CondSvc

Reimplemented from AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >.

Reimplemented in HypoBase, and InputMakerBase.

Definition at line 61 of file AthCommonReentrantAlgorithm.cxx.

                                                               {
  StatusCode sc=AthCommonDataStore<AthCommonMsg<BaseAlg>>::sysInitialize();
 
  if (sc.isFailure()) {
    return sc;
  }
  
  ServiceHandle<ICondSvc> cs("CondSvc",name());
  for (auto h : outputHandles()) {
    if (h->isCondition() && h->mode() == Gaudi::DataHandle::Writer) {
      // do this inside the loop so we don't create the CondSvc until needed
      if ( cs.retrieve().isFailure() ) {
        ATH_MSG_WARNING("no CondSvc found: won't autoreg WriteCondHandles");
        return StatusCode::SUCCESS;
      }      
      if (cs->regHandle(this,*h).isFailure()) {
        sc = StatusCode::FAILURE;
        ATH_MSG_ERROR("unable to register WriteCondHandle " << h->fullKey()
                      << " with CondSvc");
      }
    }
  }
  return sc;  
}

sysStart()

virtual StatusCode AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::sysStart ( )

overridevirtualinherited

Handle START transition.

We override this in order to make sure that conditions handle keys can cache a pointer to the conditions container.

undoMLE()

void LVL1::gFexTowerSummer::undoMLE ( int & datumPtr ) const

private

Definition at line 516 of file gFexTowerSummer.cxx.

                                                 {
 
  // limit input to 12 bits to avoid accidental sign extension
  int din = (0x00000FFF &  datumPtr );
  // map all special cases to zero for now
  // limit negative values
  if( (din > 0) && ( din < 962 )  ) din =  962;
  //zeroZero
  if( din == 0) din = 0x4EE;
 
  int dout = 0; 
  
  int FPGA_CONVLIN_TH1 = 5; 
  int FPGA_CONVLIN_TH2 = 749;
  int FPGA_CONVLIN_TH3 = 1773;
  int FPGA_CONVLIN_TH4 = 2541;
  int FPGA_CONVLIN_TH5 = 4029;
  int FPGA_CONVLIN_TH6 = 4062;
  
  int FPGA_CONVLIN_OF0 = -5072;
  int FPGA_CONVLIN_OF1 = -2012;
  int FPGA_CONVLIN_OF2 = -1262;
  int FPGA_CONVLIN_OF3 = -3036;
  int FPGA_CONVLIN_OF4 = -8120;
  int FPGA_CONVLIN_OF5 = -4118720;
  
  int oth0 = 0;
  int oth1 = 0;
  int oth2 = 0;
  int oth3 = 0;
  int oth4 = 0;
  int oth5 = 0;
  int oth6 = 0;
  
  int r1shv = 0;
  int r2shv = 0;
  int r3shv = 0;
  int r4shv = 0;
  int r5shv = 0;
  int r6shv = 0;
  // int trxv = 0;
  
  int r1conv = 0;
  int r2conv = 0;
  int r3conv = 0;
  int r4conv = 0;
  int r5conv = 0;
  int r6conv = 0;
  // int r3offs = 0;
 
  r1shv = ((din & 0x0000007F) << 9 )  & 0x0000FE00 ;
  r2shv = ((din & 0x00000FFF) << 1 )  & 0x00001FFE ;
  r3shv = (din &  0x00000FFF) ;
  r4shv = ((din & 0x00000FFF) << 1 )  & 0x00001FFE ;
  r5shv = ((din & 0x00000FFF) << 2 )  & 0x00003FFC ;
  r6shv = ((din & 0x00000FFF) << 10 ) & 0x003FFC00 ;
  
  r1conv =  r1shv + FPGA_CONVLIN_OF0;
  r2conv =  r2shv + FPGA_CONVLIN_OF1;
  r3conv =  r3shv + FPGA_CONVLIN_OF2;
  r4conv =  r4shv + FPGA_CONVLIN_OF3;
  r5conv =  r5shv + FPGA_CONVLIN_OF4;
  r6conv =  r6shv + FPGA_CONVLIN_OF5;
 
  if( din > 0 ) {
    oth0 = 1;
  }
  else{
    oth0 = 0; 
  }
  if ( din > FPGA_CONVLIN_TH1 ){
    oth1 = 1;
  }
  else{
    oth1 = 0; 
  }
  if ( din > FPGA_CONVLIN_TH2 ){
    oth2 = 1;
  }else{
    oth2 = 0; 
  }
  if ( din > FPGA_CONVLIN_TH3 ){
    oth3 = 1;
  }else{
    oth3 = 0; 
  }
  if ( din > FPGA_CONVLIN_TH4 ){
    oth4 = 1;
  }else{
    oth4 = 0; 
  }
  if ( din > FPGA_CONVLIN_TH5 ){
    oth5 = 1;
  }
  else{
    oth5 = 0; 
    }
  if ( din > FPGA_CONVLIN_TH6 ){
    oth6 = 1;
  }
  else{
    oth6 = 0; 
  }
 
 
  // divide by 2 to 50 MeV LSB
  
  if( (! oth0) & (! oth1 ) & (! oth2 ) & (! oth3 ) &  (! oth4 ) & (! oth5 ) & (! oth6 )   ) {
    dout = 0;
  } 
  else if( ( oth0) & (! oth1 ) & (! oth2 ) & (! oth3 ) &  (! oth4 ) & (! oth5 ) & (! oth6 )  ) {
    dout =  r1conv >>1;
  } 
  else if( ( oth0) & (  oth1 ) & (! oth2 ) & (! oth3 ) &  (! oth4 ) & (! oth5 ) & (! oth6 )  ) {
    dout = r2conv >>1;
  } 
  else if( ( oth0) & (  oth1 ) & ( oth2 ) & (! oth3 ) &  (! oth4 ) & (! oth5 ) & (! oth6 )  ) {
    dout = r3conv >>1;
  }  
  else if( ( oth0) & (  oth1 ) & (  oth2 ) & ( oth3 ) &  (! oth4 ) & (! oth5 ) & (! oth6 )  ) {
    dout = r4conv >>1;
  }  
  else if( ( oth0) & (  oth1 ) & (  oth2 ) & ( oth3 ) &  (  oth4 ) & (! oth5 ) & (! oth6 ) ) {
    dout = r5conv >>1;
  } 
  else if( ( oth0) & (  oth1 ) & (  oth2 ) & ( oth3 ) &  (  oth4 ) & ( oth5 ) & (! oth6 ) ) {
    dout = r6conv >>1;
  }  
  else if( ( oth0) & (  oth1 ) & (  oth2 ) & ( oth3 ) &  (  oth4 ) & (  oth5 ) & ( oth6 )  ) {
    dout = 0;
  } 
  else {
    dout = 0; 
  }
 
  signExtend(&dout,15);
  
  datumPtr = dout;
}

updateVHKA()

void AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::updateVHKA ( Gaudi::Details::PropertyBase & )

inlineinherited

Definition at line 308 of file AthCommonDataStore.h.

                                               {
    // debug() << "updateVHKA for property " << p.name() << " " << p.toString() 
    //         << "  size: " << m_vhka.size() << endmsg;
    for (auto &a : m_vhka) {
      std::vector<SG::VarHandleKey*> keys = a->keys();
      for (auto k : keys) {
        k->setOwner(this);
      }
    }
  }

Member Data Documentation

m_detStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::m_detStore

privateinherited

Pointer to StoreGate (detector store by default)

Definition at line 393 of file AthCommonDataStore.h.

m_evtStore

StoreGateSvc_t AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::m_evtStore

privateinherited

Pointer to StoreGate (event store by default)

Definition at line 390 of file AthCommonDataStore.h.

m_extendedExtraObjects

DataObjIDColl AthCommonReentrantAlgorithm< Gaudi::Algorithm >::m_extendedExtraObjects

privateinherited

Extra output dependency collection, extended by AthAlgorithmDHUpdate to add symlinks.

Empty if no symlinks were found.

Definition at line 114 of file AthCommonReentrantAlgorithm.h.

m_gFexFiberTowersReadKey

SG::ReadHandleKey<xAOD::gFexTowerContainer> LVL1::gFexTowerSummer::m_gFexFiberTowersReadKey

private

Initial value:

{
      this, "gFexDataTowers", "L1_gFexDataTowers","gFexDataTowers container"}

Definition at line 48 of file gFexTowerSummer.h.

                                                                  {
      this, "gFexDataTowers", "L1_gFexDataTowers","gFexDataTowers container"};

m_gTowers50WriteKey

SG::WriteHandleKey<xAOD::gFexTowerContainer> LVL1::gFexTowerSummer::m_gTowers50WriteKey

private

Initial value:

{
    this, "gTowers50WriteKey", "L1_gFexDataTowers50", "Write gFEX 50 MeV Trigger Tower container"}

Definition at line 55 of file gFexTowerSummer.h.

                                                              {
    this, "gTowers50WriteKey", "L1_gFexDataTowers50", "Write gFEX 50 MeV Trigger Tower container"};

m_gTowersEMWriteKey

SG::WriteHandleKey<xAOD::gFexTowerContainer> LVL1::gFexTowerSummer::m_gTowersEMWriteKey

private

Initial value:

{
      this, "gTowersEMWriteKey", "L1_gFexEmulatedEMTowers", "Write gFEX 200 MeV Trigger Tower EM container"}

Definition at line 59 of file gFexTowerSummer.h.

                                                              {
      this, "gTowersEMWriteKey", "L1_gFexEmulatedEMTowers", "Write gFEX 200 MeV Trigger Tower EM container"};

m_gTowersHADWriteKey

SG::WriteHandleKey<xAOD::gFexTowerContainer> LVL1::gFexTowerSummer::m_gTowersHADWriteKey

private

Initial value:

{
      this, "gTowersHADWriteKey", "L1_gFexEmulatedHADTowers", "Write gFEX 200 MeV Trigger Tower HAD container"}

Definition at line 62 of file gFexTowerSummer.h.

                                                               {
      this, "gTowersHADWriteKey", "L1_gFexEmulatedHADTowers", "Write gFEX 200 MeV Trigger Tower HAD container"};  

m_gTowersWriteKey

SG::WriteHandleKey<xAOD::gFexTowerContainer> LVL1::gFexTowerSummer::m_gTowersWriteKey

private

Initial value:

{
      this, "gTowers200WriteKey", "L1_gFexDataTowers200","Write gFEX 200 MeV Trigger Tower container"}

Definition at line 52 of file gFexTowerSummer.h.

                                                            {
      this, "gTowers200WriteKey", "L1_gFexDataTowers200","Write gFEX 200 MeV Trigger Tower container"};

m_varHandleArraysDeclared

bool AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::m_varHandleArraysDeclared

privateinherited

Definition at line 399 of file AthCommonDataStore.h.

m_vhka

std::vector<SG::VarHandleKeyArray*> AthCommonDataStore< AthCommonMsg< Gaudi::Algorithm > >::m_vhka

privateinherited

Definition at line 398 of file AthCommonDataStore.h.

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The documentation for this class was generated from the following files:

• gFexTowerSummer.h
• gFexTowerSummer.cxx