Loading [MathJax]/extensions/tex2jax.js
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ATLAS Offline Software
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consteval uint64_t | SELECTBITS (uint8_t len, uint8_t startbit) |
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EVT_HDR_w1 | get_bitfields_EVT_HDR_w1 (const uint64_t &in) |
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EVT_HDR_w2 | get_bitfields_EVT_HDR_w2 (const uint64_t &in) |
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EVT_HDR_w3 | get_bitfields_EVT_HDR_w3 (const uint64_t &in) |
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uint64_t | get_dataformat_EVT_HDR_w1 (const EVT_HDR_w1 &in) |
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uint64_t | get_dataformat_EVT_HDR_w2 (const EVT_HDR_w2 &in) |
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uint64_t | get_dataformat_EVT_HDR_w3 (const EVT_HDR_w3 &in) |
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EVT_HDR_w1 | fill_EVT_HDR_w1 (const uint64_t &flag, const uint64_t &l0id, const uint64_t &bcid, const uint64_t &spare) |
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EVT_HDR_w2 | fill_EVT_HDR_w2 (const uint64_t &runnumber, const uint64_t &time) |
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EVT_HDR_w3 | fill_EVT_HDR_w3 (const uint64_t &status, const uint64_t &crc) |
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uint64_t | to_real_EVT_HDR_w1_flag (const uint64_t &in) |
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uint64_t | to_real_EVT_HDR_w1_l0id (const uint64_t &in) |
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uint64_t | to_real_EVT_HDR_w1_bcid (const uint64_t &in) |
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uint64_t | to_real_EVT_HDR_w1_spare (const uint64_t &in) |
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uint64_t | to_real_EVT_HDR_w2_runnumber (const uint64_t &in) |
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uint64_t | to_real_EVT_HDR_w2_time (const uint64_t &in) |
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uint64_t | to_real_EVT_HDR_w3_status (const uint64_t &in) |
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uint64_t | to_real_EVT_HDR_w3_crc (const uint64_t &in) |
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EVT_FTR_w1 | get_bitfields_EVT_FTR_w1 (const uint64_t &in) |
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EVT_FTR_w2 | get_bitfields_EVT_FTR_w2 (const uint64_t &in) |
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EVT_FTR_w3 | get_bitfields_EVT_FTR_w3 (const uint64_t &in) |
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uint64_t | get_dataformat_EVT_FTR_w1 (const EVT_FTR_w1 &in) |
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uint64_t | get_dataformat_EVT_FTR_w2 (const EVT_FTR_w2 &in) |
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uint64_t | get_dataformat_EVT_FTR_w3 (const EVT_FTR_w3 &in) |
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EVT_FTR_w1 | fill_EVT_FTR_w1 (const uint64_t &flag, const uint64_t &spare, const uint64_t &hdr_crc) |
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EVT_FTR_w2 | fill_EVT_FTR_w2 (const uint64_t &error_flags) |
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EVT_FTR_w3 | fill_EVT_FTR_w3 (const uint64_t &word_count, const uint64_t &crc) |
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uint64_t | to_real_EVT_FTR_w1_flag (const uint64_t &in) |
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uint64_t | to_real_EVT_FTR_w1_spare (const uint64_t &in) |
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uint64_t | to_real_EVT_FTR_w1_hdr_crc (const uint64_t &in) |
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uint64_t | to_real_EVT_FTR_w2_error_flags (const uint64_t &in) |
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uint64_t | to_real_EVT_FTR_w3_word_count (const uint64_t &in) |
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uint64_t | to_real_EVT_FTR_w3_crc (const uint64_t &in) |
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M_HDR_w1 | get_bitfields_M_HDR_w1 (const uint64_t &in) |
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uint64_t | get_dataformat_M_HDR_w1 (const M_HDR_w1 &in) |
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M_HDR_w1 | fill_M_HDR_w1 (const uint64_t &flag, const uint64_t &modid, const uint64_t &modhash, const uint64_t &spare) |
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uint64_t | to_real_M_HDR_w1_flag (const uint64_t &in) |
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uint64_t | to_real_M_HDR_w1_modid (const uint64_t &in) |
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uint64_t | to_real_M_HDR_w1_modhash (const uint64_t &in) |
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uint64_t | to_real_M_HDR_w1_spare (const uint64_t &in) |
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SLICE_HDR_w1 | get_bitfields_SLICE_HDR_w1 (const uint64_t &in) |
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uint64_t | get_dataformat_SLICE_HDR_w1 (const SLICE_HDR_w1 &in) |
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SLICE_HDR_w1 | fill_SLICE_HDR_w1 (const uint64_t &flag, const uint64_t &sliceid, const uint64_t &eta_region, const uint64_t &phi_region, const uint64_t &spare) |
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uint64_t | to_real_SLICE_HDR_w1_flag (const uint64_t &in) |
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uint64_t | to_real_SLICE_HDR_w1_sliceid (const uint64_t &in) |
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uint64_t | to_real_SLICE_HDR_w1_eta_region (const uint64_t &in) |
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uint64_t | to_real_SLICE_HDR_w1_phi_region (const uint64_t &in) |
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uint64_t | to_real_SLICE_HDR_w1_spare (const uint64_t &in) |
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RD_HDR_w1 | get_bitfields_RD_HDR_w1 (const uint64_t &in) |
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RD_HDR_w2 | get_bitfields_RD_HDR_w2 (const uint64_t &in) |
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uint64_t | get_dataformat_RD_HDR_w1 (const RD_HDR_w1 &in) |
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uint64_t | get_dataformat_RD_HDR_w2 (const RD_HDR_w2 &in) |
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RD_HDR_w1 | fill_RD_HDR_w1 (const uint64_t &flag, const uint64_t &type, const uint64_t &eta_region, const uint64_t &phi_region, const uint64_t &slice, const uint64_t &hough_x_bin, const uint64_t &hough_y_bin, const uint64_t &second_stage, const uint64_t &layer_bitmask, const uint64_t &spare) |
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RD_HDR_w2 | fill_RD_HDR_w2 (const uint64_t &global_phi, const uint64_t &global_eta, const uint64_t &spare) |
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uint64_t | to_real_RD_HDR_w1_flag (const uint64_t &in) |
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uint64_t | to_real_RD_HDR_w1_type (const uint64_t &in) |
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uint64_t | to_real_RD_HDR_w1_eta_region (const uint64_t &in) |
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uint64_t | to_real_RD_HDR_w1_phi_region (const uint64_t &in) |
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uint64_t | to_real_RD_HDR_w1_slice (const uint64_t &in) |
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uint64_t | to_real_RD_HDR_w1_hough_x_bin (const uint64_t &in) |
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uint64_t | to_real_RD_HDR_w1_hough_y_bin (const uint64_t &in) |
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uint64_t | to_real_RD_HDR_w1_second_stage (const uint64_t &in) |
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uint64_t | to_real_RD_HDR_w1_layer_bitmask (const uint64_t &in) |
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uint64_t | to_real_RD_HDR_w1_spare (const uint64_t &in) |
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uint64_t | to_real_RD_HDR_w2_global_phi (const uint64_t &in) |
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uint64_t | to_real_RD_HDR_w2_global_eta (const uint64_t &in) |
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uint64_t | to_real_RD_HDR_w2_spare (const uint64_t &in) |
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GTRACK_HDR_w1 | get_bitfields_GTRACK_HDR_w1 (const uint64_t &in) |
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GTRACK_HDR_w2 | get_bitfields_GTRACK_HDR_w2 (const uint64_t &in) |
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GTRACK_HDR_w3 | get_bitfields_GTRACK_HDR_w3 (const uint64_t &in) |
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uint64_t | get_dataformat_GTRACK_HDR_w1 (const GTRACK_HDR_w1 &in) |
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uint64_t | get_dataformat_GTRACK_HDR_w2 (const GTRACK_HDR_w2 &in) |
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uint64_t | get_dataformat_GTRACK_HDR_w3 (const GTRACK_HDR_w3 &in) |
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GTRACK_HDR_w1 | fill_GTRACK_HDR_w1 (const uint64_t &flag, const uint64_t &type, const uint64_t &eta_region, const uint64_t &phi_region, const uint64_t &slice, const uint64_t &hough_x_bin, const uint64_t &hough_y_bin, const uint64_t &second_stage, const uint64_t &layer_bitmask, const uint64_t &spare) |
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GTRACK_HDR_w2 | fill_GTRACK_HDR_w2 (const double &score, const double &d0, const double &z0, const uint64_t &spare) |
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GTRACK_HDR_w3 | fill_GTRACK_HDR_w3 (const int64_t &qoverpt, const int64_t &phi, const int64_t &eta, const uint64_t &spare) |
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uint64_t | to_real_GTRACK_HDR_w1_flag (const uint64_t &in) |
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uint64_t | to_real_GTRACK_HDR_w1_type (const uint64_t &in) |
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uint64_t | to_real_GTRACK_HDR_w1_eta_region (const uint64_t &in) |
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uint64_t | to_real_GTRACK_HDR_w1_phi_region (const uint64_t &in) |
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uint64_t | to_real_GTRACK_HDR_w1_slice (const uint64_t &in) |
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uint64_t | to_real_GTRACK_HDR_w1_hough_x_bin (const uint64_t &in) |
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uint64_t | to_real_GTRACK_HDR_w1_hough_y_bin (const uint64_t &in) |
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uint64_t | to_real_GTRACK_HDR_w1_second_stage (const uint64_t &in) |
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uint64_t | to_real_GTRACK_HDR_w1_layer_bitmask (const uint64_t &in) |
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uint64_t | to_real_GTRACK_HDR_w1_spare (const uint64_t &in) |
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double | to_real_GTRACK_HDR_w2_score (const uint64_t &in) |
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double | to_real_GTRACK_HDR_w2_d0 (const int64_t &in) |
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double | to_real_GTRACK_HDR_w2_z0 (const int64_t &in) |
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uint64_t | to_real_GTRACK_HDR_w2_spare (const uint64_t &in) |
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int64_t | to_real_GTRACK_HDR_w3_qoverpt (const int64_t &in) |
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int64_t | to_real_GTRACK_HDR_w3_phi (const int64_t &in) |
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int64_t | to_real_GTRACK_HDR_w3_eta (const int64_t &in) |
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uint64_t | to_real_GTRACK_HDR_w3_spare (const uint64_t &in) |
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PIXEL_CLUSTER | get_bitfields_PIXEL_CLUSTER (const uint64_t &in) |
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uint64_t | get_dataformat_PIXEL_CLUSTER (const PIXEL_CLUSTER &in) |
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PIXEL_CLUSTER | fill_PIXEL_CLUSTER (const uint64_t &last, const uint64_t &col, const uint64_t &row, const double ¢roid_col, const double ¢roid_row, const uint64_t &spare) |
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uint64_t | to_real_PIXEL_CLUSTER_last (const uint64_t &in) |
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uint64_t | to_real_PIXEL_CLUSTER_col (const uint64_t &in) |
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uint64_t | to_real_PIXEL_CLUSTER_row (const uint64_t &in) |
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double | to_real_PIXEL_CLUSTER_centroid_col (const uint64_t &in) |
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double | to_real_PIXEL_CLUSTER_centroid_row (const uint64_t &in) |
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uint64_t | to_real_PIXEL_CLUSTER_spare (const uint64_t &in) |
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STRIP_CLUSTER | get_bitfields_STRIP_CLUSTER (const uint64_t &in) |
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uint64_t | get_dataformat_STRIP_CLUSTER_up32 (const uint64_t &in) |
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uint64_t | get_dataformat_STRIP_CLUSTER_low32 (const uint64_t &in) |
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uint64_t | get_dataformat_STRIP_CLUSTER (const STRIP_CLUSTER &in) |
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uint64_t | get_dataformat_STRIP_CLUSTER_64 (const uint64_t &up, const uint64_t &low) |
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STRIP_CLUSTER | fill_STRIP_CLUSTER (const uint64_t &last, const uint64_t &row, const uint64_t &nstrips, const uint64_t &strip_index, const uint64_t &spare) |
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uint64_t | to_real_STRIP_CLUSTER_last (const uint64_t &in) |
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uint64_t | to_real_STRIP_CLUSTER_row (const uint64_t &in) |
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uint64_t | to_real_STRIP_CLUSTER_nstrips (const uint64_t &in) |
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uint64_t | to_real_STRIP_CLUSTER_strip_index (const uint64_t &in) |
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uint64_t | to_real_STRIP_CLUSTER_spare (const uint64_t &in) |
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GHITZ_w1 | get_bitfields_GHITZ_w1 (const uint64_t &in) |
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GHITZ_w2 | get_bitfields_GHITZ_w2 (const uint64_t &in) |
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uint64_t | get_dataformat_GHITZ_w1 (const GHITZ_w1 &in) |
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uint64_t | get_dataformat_GHITZ_w2 (const GHITZ_w2 &in) |
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GHITZ_w1 | fill_GHITZ_w1 (const uint64_t &last, const uint64_t &lyr, const double &rad, const double &phi, const double &z, const uint64_t &lastofslice, const uint64_t &spare) |
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GHITZ_w2 | fill_GHITZ_w2 (const uint64_t &cluster1, const uint64_t &cluster2, const uint64_t &row, const uint64_t &spare) |
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uint64_t | to_real_GHITZ_w1_last (const uint64_t &in) |
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uint64_t | to_real_GHITZ_w1_lyr (const uint64_t &in) |
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double | to_real_GHITZ_w1_rad (const uint64_t &in) |
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double | to_real_GHITZ_w1_phi (const int64_t &in) |
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double | to_real_GHITZ_w1_z (const int64_t &in) |
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uint64_t | to_real_GHITZ_w1_lastofslice (const uint64_t &in) |
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uint64_t | to_real_GHITZ_w1_spare (const uint64_t &in) |
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uint64_t | to_real_GHITZ_w2_cluster1 (const uint64_t &in) |
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uint64_t | to_real_GHITZ_w2_cluster2 (const uint64_t &in) |
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uint64_t | to_real_GHITZ_w2_row (const uint64_t &in) |
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uint64_t | to_real_GHITZ_w2_spare (const uint64_t &in) |
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EDM_STRIPCLUSTER_w1 | get_bitfields_EDM_STRIPCLUSTER_w1 (const uint64_t &in) |
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EDM_STRIPCLUSTER_w2 | get_bitfields_EDM_STRIPCLUSTER_w2 (const uint64_t &in) |
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EDM_STRIPCLUSTER_w3 | get_bitfields_EDM_STRIPCLUSTER_w3 (const uint64_t &in) |
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EDM_STRIPCLUSTER_w4 | get_bitfields_EDM_STRIPCLUSTER_w4 (const uint64_t &in) |
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EDM_STRIPCLUSTER_w5 | get_bitfields_EDM_STRIPCLUSTER_w5 (const uint64_t &in) |
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EDM_STRIPCLUSTER_w6 | get_bitfields_EDM_STRIPCLUSTER_w6 (const uint64_t &in) |
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EDM_STRIPCLUSTER_w7 | get_bitfields_EDM_STRIPCLUSTER_w7 (const uint64_t &in) |
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EDM_STRIPCLUSTER_w8 | get_bitfields_EDM_STRIPCLUSTER_w8 (const uint64_t &in) |
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EDM_STRIPCLUSTER_w9 | get_bitfields_EDM_STRIPCLUSTER_w9 (const uint64_t &in) |
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uint64_t | get_dataformat_EDM_STRIPCLUSTER_w1 (const EDM_STRIPCLUSTER_w1 &in) |
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uint64_t | get_dataformat_EDM_STRIPCLUSTER_w2 (const EDM_STRIPCLUSTER_w2 &in) |
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uint64_t | get_dataformat_EDM_STRIPCLUSTER_w3 (const EDM_STRIPCLUSTER_w3 &in) |
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uint64_t | get_dataformat_EDM_STRIPCLUSTER_w4 (const EDM_STRIPCLUSTER_w4 &in) |
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uint64_t | get_dataformat_EDM_STRIPCLUSTER_w5 (const EDM_STRIPCLUSTER_w5 &in) |
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uint64_t | get_dataformat_EDM_STRIPCLUSTER_w6 (const EDM_STRIPCLUSTER_w6 &in) |
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uint64_t | get_dataformat_EDM_STRIPCLUSTER_w7 (const EDM_STRIPCLUSTER_w7 &in) |
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uint64_t | get_dataformat_EDM_STRIPCLUSTER_w8 (const EDM_STRIPCLUSTER_w8 &in) |
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uint64_t | get_dataformat_EDM_STRIPCLUSTER_w9 (const EDM_STRIPCLUSTER_w9 &in) |
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EDM_STRIPCLUSTER_w1 | fill_EDM_STRIPCLUSTER_w1 (const uint64_t &flag, const uint64_t &id_hash, const uint64_t &spare) |
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EDM_STRIPCLUSTER_w2 | fill_EDM_STRIPCLUSTER_w2 (const uint64_t &identifier) |
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EDM_STRIPCLUSTER_w3 | fill_EDM_STRIPCLUSTER_w3 (const uint64_t &rdo_list_w1) |
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EDM_STRIPCLUSTER_w4 | fill_EDM_STRIPCLUSTER_w4 (const uint64_t &rdo_list_w2) |
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EDM_STRIPCLUSTER_w5 | fill_EDM_STRIPCLUSTER_w5 (const uint64_t &rdo_list_w3) |
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EDM_STRIPCLUSTER_w6 | fill_EDM_STRIPCLUSTER_w6 (const uint64_t &rdo_list_w4) |
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EDM_STRIPCLUSTER_w7 | fill_EDM_STRIPCLUSTER_w7 (const double &localposition_x, const double &localposition_y, const double &localcovariance_xx, const uint64_t &spare) |
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EDM_STRIPCLUSTER_w8 | fill_EDM_STRIPCLUSTER_w8 (const double &globalposition_x, const double &globalposition_y, const uint64_t &channels_in_phi, const uint64_t &spare) |
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EDM_STRIPCLUSTER_w9 | fill_EDM_STRIPCLUSTER_w9 (const double &globalposition_z, const uint64_t &lastword, const uint64_t &index, const uint64_t &spare) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w1_flag (const uint64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w1_id_hash (const uint64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w1_spare (const uint64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w2_identifier (const uint64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w3_rdo_list_w1 (const uint64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w4_rdo_list_w2 (const uint64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w5_rdo_list_w3 (const uint64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w6_rdo_list_w4 (const uint64_t &in) |
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double | to_real_EDM_STRIPCLUSTER_w7_localposition_x (const int64_t &in) |
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double | to_real_EDM_STRIPCLUSTER_w7_localposition_y (const int64_t &in) |
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double | to_real_EDM_STRIPCLUSTER_w7_localcovariance_xx (const uint64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w7_spare (const uint64_t &in) |
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double | to_real_EDM_STRIPCLUSTER_w8_globalposition_x (const int64_t &in) |
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double | to_real_EDM_STRIPCLUSTER_w8_globalposition_y (const int64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w8_channels_in_phi (const uint64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w8_spare (const uint64_t &in) |
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double | to_real_EDM_STRIPCLUSTER_w9_globalposition_z (const int64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w9_lastword (const uint64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w9_index (const uint64_t &in) |
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uint64_t | to_real_EDM_STRIPCLUSTER_w9_spare (const uint64_t &in) |
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EDM_PIXELCLUSTER_w1 | get_bitfields_EDM_PIXELCLUSTER_w1 (const uint64_t &in) |
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EDM_PIXELCLUSTER_w2 | get_bitfields_EDM_PIXELCLUSTER_w2 (const uint64_t &in) |
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EDM_PIXELCLUSTER_w3 | get_bitfields_EDM_PIXELCLUSTER_w3 (const uint64_t &in) |
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EDM_PIXELCLUSTER_w4 | get_bitfields_EDM_PIXELCLUSTER_w4 (const uint64_t &in) |
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EDM_PIXELCLUSTER_w5 | get_bitfields_EDM_PIXELCLUSTER_w5 (const uint64_t &in) |
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EDM_PIXELCLUSTER_w6 | get_bitfields_EDM_PIXELCLUSTER_w6 (const uint64_t &in) |
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EDM_PIXELCLUSTER_w7 | get_bitfields_EDM_PIXELCLUSTER_w7 (const uint64_t &in) |
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EDM_PIXELCLUSTER_w8 | get_bitfields_EDM_PIXELCLUSTER_w8 (const uint64_t &in) |
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EDM_PIXELCLUSTER_w9 | get_bitfields_EDM_PIXELCLUSTER_w9 (const uint64_t &in) |
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EDM_PIXELCLUSTER_w10 | get_bitfields_EDM_PIXELCLUSTER_w10 (const uint64_t &in) |
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uint64_t | get_dataformat_EDM_PIXELCLUSTER_w1 (const EDM_PIXELCLUSTER_w1 &in) |
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uint64_t | get_dataformat_EDM_PIXELCLUSTER_w2 (const EDM_PIXELCLUSTER_w2 &in) |
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uint64_t | get_dataformat_EDM_PIXELCLUSTER_w3 (const EDM_PIXELCLUSTER_w3 &in) |
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uint64_t | get_dataformat_EDM_PIXELCLUSTER_w4 (const EDM_PIXELCLUSTER_w4 &in) |
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uint64_t | get_dataformat_EDM_PIXELCLUSTER_w5 (const EDM_PIXELCLUSTER_w5 &in) |
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uint64_t | get_dataformat_EDM_PIXELCLUSTER_w6 (const EDM_PIXELCLUSTER_w6 &in) |
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uint64_t | get_dataformat_EDM_PIXELCLUSTER_w7 (const EDM_PIXELCLUSTER_w7 &in) |
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uint64_t | get_dataformat_EDM_PIXELCLUSTER_w8 (const EDM_PIXELCLUSTER_w8 &in) |
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uint64_t | get_dataformat_EDM_PIXELCLUSTER_w9 (const EDM_PIXELCLUSTER_w9 &in) |
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uint64_t | get_dataformat_EDM_PIXELCLUSTER_w10 (const EDM_PIXELCLUSTER_w10 &in) |
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EDM_PIXELCLUSTER_w1 | fill_EDM_PIXELCLUSTER_w1 (const uint64_t &flag, const uint64_t &id_hash, const uint64_t &spare) |
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EDM_PIXELCLUSTER_w2 | fill_EDM_PIXELCLUSTER_w2 (const uint64_t &identifier) |
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EDM_PIXELCLUSTER_w3 | fill_EDM_PIXELCLUSTER_w3 (const uint64_t &rdo_list_w1) |
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EDM_PIXELCLUSTER_w4 | fill_EDM_PIXELCLUSTER_w4 (const uint64_t &rdo_list_w2) |
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EDM_PIXELCLUSTER_w5 | fill_EDM_PIXELCLUSTER_w5 (const uint64_t &rdo_list_w3) |
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EDM_PIXELCLUSTER_w6 | fill_EDM_PIXELCLUSTER_w6 (const uint64_t &rdo_list_w4) |
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EDM_PIXELCLUSTER_w7 | fill_EDM_PIXELCLUSTER_w7 (const double &localposition_x, const double &localposition_y, const uint64_t &channels_in_phi, const uint64_t &channels_in_eta, const double &width_in_eta, const uint64_t &spare) |
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EDM_PIXELCLUSTER_w8 | fill_EDM_PIXELCLUSTER_w8 (const double &localcovariance_xx, const double &localcovariance_yy, const double &omega_x, const double &omega_y, const uint64_t &spare) |
|
EDM_PIXELCLUSTER_w9 | fill_EDM_PIXELCLUSTER_w9 (const double &globalposition_x, const double &globalposition_y, const uint64_t &spare) |
|
EDM_PIXELCLUSTER_w10 | fill_EDM_PIXELCLUSTER_w10 (const double &globalposition_z, const uint64_t &total_tot, const uint64_t &lastword, const uint64_t &spare) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w1_flag (const uint64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w1_id_hash (const uint64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w1_spare (const uint64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w2_identifier (const uint64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w3_rdo_list_w1 (const uint64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w4_rdo_list_w2 (const uint64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w5_rdo_list_w3 (const uint64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w6_rdo_list_w4 (const uint64_t &in) |
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double | to_real_EDM_PIXELCLUSTER_w7_localposition_x (const int64_t &in) |
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double | to_real_EDM_PIXELCLUSTER_w7_localposition_y (const int64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w7_channels_in_phi (const uint64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w7_channels_in_eta (const uint64_t &in) |
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double | to_real_EDM_PIXELCLUSTER_w7_width_in_eta (const uint64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w7_spare (const uint64_t &in) |
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double | to_real_EDM_PIXELCLUSTER_w8_localcovariance_xx (const uint64_t &in) |
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double | to_real_EDM_PIXELCLUSTER_w8_localcovariance_yy (const uint64_t &in) |
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double | to_real_EDM_PIXELCLUSTER_w8_omega_x (const uint64_t &in) |
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double | to_real_EDM_PIXELCLUSTER_w8_omega_y (const uint64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w8_spare (const uint64_t &in) |
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double | to_real_EDM_PIXELCLUSTER_w9_globalposition_x (const int64_t &in) |
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double | to_real_EDM_PIXELCLUSTER_w9_globalposition_y (const int64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w9_spare (const uint64_t &in) |
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double | to_real_EDM_PIXELCLUSTER_w10_globalposition_z (const int64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w10_total_tot (const uint64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w10_lastword (const uint64_t &in) |
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uint64_t | to_real_EDM_PIXELCLUSTER_w10_spare (const uint64_t &in) |
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PIXEL_EF_RDO | get_bitfields_PIXEL_EF_RDO (const uint64_t &in) |
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uint64_t | get_dataformat_PIXEL_EF_RDO (const PIXEL_EF_RDO &in) |
|
PIXEL_EF_RDO | fill_PIXEL_EF_RDO (const uint64_t &last, const uint64_t &row, const uint64_t &col, const uint64_t &tot, const uint64_t &lvl1, const uint64_t &spare) |
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uint64_t | to_real_PIXEL_EF_RDO_last (const uint64_t &in) |
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uint64_t | to_real_PIXEL_EF_RDO_row (const uint64_t &in) |
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uint64_t | to_real_PIXEL_EF_RDO_col (const uint64_t &in) |
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uint64_t | to_real_PIXEL_EF_RDO_tot (const uint64_t &in) |
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uint64_t | to_real_PIXEL_EF_RDO_lvl1 (const uint64_t &in) |
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uint64_t | to_real_PIXEL_EF_RDO_spare (const uint64_t &in) |
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STRIP_EF_RDO | get_bitfields_STRIP_EF_RDO (const uint64_t &in) |
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uint64_t | get_dataformat_STRIP_EF_RDO_up32 (const uint64_t &in) |
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uint64_t | get_dataformat_STRIP_EF_RDO_low32 (const uint64_t &in) |
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uint64_t | get_dataformat_STRIP_EF_RDO (const STRIP_EF_RDO &in) |
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uint64_t | get_dataformat_STRIP_EF_RDO_64 (const uint64_t &up, const uint64_t &low) |
|
STRIP_EF_RDO | fill_STRIP_EF_RDO (const uint64_t &last, const uint64_t &chipid, const uint64_t &strip_num, const uint64_t &cluster_map, const uint64_t &spare) |
|
uint64_t | to_real_STRIP_EF_RDO_last (const uint64_t &in) |
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uint64_t | to_real_STRIP_EF_RDO_chipid (const uint64_t &in) |
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uint64_t | to_real_STRIP_EF_RDO_strip_num (const uint64_t &in) |
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uint64_t | to_real_STRIP_EF_RDO_cluster_map (const uint64_t &in) |
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uint64_t | to_real_STRIP_EF_RDO_spare (const uint64_t &in) |
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◆ EDM_PIXELCLUSTER_w1
◆ EDM_PIXELCLUSTER_w10
◆ EDM_PIXELCLUSTER_w2
◆ EDM_PIXELCLUSTER_w3
◆ EDM_PIXELCLUSTER_w4
◆ EDM_PIXELCLUSTER_w5
◆ EDM_PIXELCLUSTER_w6
◆ EDM_PIXELCLUSTER_w7
◆ EDM_PIXELCLUSTER_w8
◆ EDM_PIXELCLUSTER_w9
◆ EDM_STRIPCLUSTER_w1
◆ EDM_STRIPCLUSTER_w2
◆ EDM_STRIPCLUSTER_w3
◆ EDM_STRIPCLUSTER_w4
◆ EDM_STRIPCLUSTER_w5
◆ EDM_STRIPCLUSTER_w6
◆ EDM_STRIPCLUSTER_w7
◆ EDM_STRIPCLUSTER_w8
◆ EDM_STRIPCLUSTER_w9
◆ EVT_FTR_w1
◆ EVT_FTR_w2
◆ EVT_FTR_w3
◆ EVT_HDR_w1
◆ EVT_HDR_w2
◆ EVT_HDR_w3
◆ GHITZ_w1
◆ GHITZ_w2
◆ GTRACK_HDR_w1
◆ GTRACK_HDR_w2
◆ GTRACK_HDR_w3
◆ M_HDR_w1
◆ PIXEL_CLUSTER
◆ PIXEL_EF_RDO
◆ RD_HDR_w1
◆ RD_HDR_w2
◆ SLICE_HDR_w1
◆ STRIP_CLUSTER
◆ STRIP_EF_RDO
◆ fill_EDM_PIXELCLUSTER_w1()
◆ fill_EDM_PIXELCLUSTER_w10()
◆ fill_EDM_PIXELCLUSTER_w2()
◆ fill_EDM_PIXELCLUSTER_w3()
◆ fill_EDM_PIXELCLUSTER_w4()
◆ fill_EDM_PIXELCLUSTER_w5()
◆ fill_EDM_PIXELCLUSTER_w6()
◆ fill_EDM_PIXELCLUSTER_w7()
EDM_PIXELCLUSTER_w7 FPGADataFormatUtilities::fill_EDM_PIXELCLUSTER_w7 |
( |
const double & |
localposition_x, |
|
|
const double & |
localposition_y, |
|
|
const uint64_t & |
channels_in_phi, |
|
|
const uint64_t & |
channels_in_eta, |
|
|
const double & |
width_in_eta, |
|
|
const uint64_t & |
spare |
|
) |
| |
|
inline |
Definition at line 2061 of file FPGADataFormatUtilities.h.
2065 temp.channels_in_phi = channels_in_phi;
2066 temp.channels_in_eta = channels_in_eta;
◆ fill_EDM_PIXELCLUSTER_w8()
◆ fill_EDM_PIXELCLUSTER_w9()
◆ fill_EDM_STRIPCLUSTER_w1()
◆ fill_EDM_STRIPCLUSTER_w2()
◆ fill_EDM_STRIPCLUSTER_w3()
◆ fill_EDM_STRIPCLUSTER_w4()
◆ fill_EDM_STRIPCLUSTER_w5()
◆ fill_EDM_STRIPCLUSTER_w6()
◆ fill_EDM_STRIPCLUSTER_w7()
EDM_STRIPCLUSTER_w7 FPGADataFormatUtilities::fill_EDM_STRIPCLUSTER_w7 |
( |
const double & |
localposition_x, |
|
|
const double & |
localposition_y, |
|
|
const double & |
localcovariance_xx, |
|
|
const uint64_t & |
spare |
|
) |
| |
|
inline |
◆ fill_EDM_STRIPCLUSTER_w8()
EDM_STRIPCLUSTER_w8 FPGADataFormatUtilities::fill_EDM_STRIPCLUSTER_w8 |
( |
const double & |
globalposition_x, |
|
|
const double & |
globalposition_y, |
|
|
const uint64_t & |
channels_in_phi, |
|
|
const uint64_t & |
spare |
|
) |
| |
|
inline |
◆ fill_EDM_STRIPCLUSTER_w9()
◆ fill_EVT_FTR_w1()
EVT_FTR_w1 FPGADataFormatUtilities::fill_EVT_FTR_w1 |
( |
const uint64_t & |
flag, |
|
|
const uint64_t & |
spare, |
|
|
const uint64_t & |
hdr_crc |
|
) |
| |
|
inline |
◆ fill_EVT_FTR_w2()
EVT_FTR_w2 FPGADataFormatUtilities::fill_EVT_FTR_w2 |
( |
const uint64_t & |
error_flags | ) |
|
|
inline |
◆ fill_EVT_FTR_w3()
EVT_FTR_w3 FPGADataFormatUtilities::fill_EVT_FTR_w3 |
( |
const uint64_t & |
word_count, |
|
|
const uint64_t & |
crc |
|
) |
| |
|
inline |
◆ fill_EVT_HDR_w1()
◆ fill_EVT_HDR_w2()
EVT_HDR_w2 FPGADataFormatUtilities::fill_EVT_HDR_w2 |
( |
const uint64_t & |
runnumber, |
|
|
const uint64_t & |
time |
|
) |
| |
|
inline |
◆ fill_EVT_HDR_w3()
EVT_HDR_w3 FPGADataFormatUtilities::fill_EVT_HDR_w3 |
( |
const uint64_t & |
status, |
|
|
const uint64_t & |
crc |
|
) |
| |
|
inline |
◆ fill_GHITZ_w1()
◆ fill_GHITZ_w2()
GHITZ_w2 FPGADataFormatUtilities::fill_GHITZ_w2 |
( |
const uint64_t & |
cluster1, |
|
|
const uint64_t & |
cluster2, |
|
|
const uint64_t & |
row, |
|
|
const uint64_t & |
spare |
|
) |
| |
|
inline |
◆ fill_GTRACK_HDR_w1()
GTRACK_HDR_w1 FPGADataFormatUtilities::fill_GTRACK_HDR_w1 |
( |
const uint64_t & |
flag, |
|
|
const uint64_t & |
type, |
|
|
const uint64_t & |
eta_region, |
|
|
const uint64_t & |
phi_region, |
|
|
const uint64_t & |
slice, |
|
|
const uint64_t & |
hough_x_bin, |
|
|
const uint64_t & |
hough_y_bin, |
|
|
const uint64_t & |
second_stage, |
|
|
const uint64_t & |
layer_bitmask, |
|
|
const uint64_t & |
spare |
|
) |
| |
|
inline |
Definition at line 826 of file FPGADataFormatUtilities.h.
830 temp.eta_region = eta_region;
831 temp.phi_region = phi_region;
833 temp.hough_x_bin = hough_x_bin;
834 temp.hough_y_bin = hough_y_bin;
835 temp.second_stage = second_stage;
836 temp.layer_bitmask = layer_bitmask;
◆ fill_GTRACK_HDR_w2()
◆ fill_GTRACK_HDR_w3()
◆ fill_M_HDR_w1()
M_HDR_w1 FPGADataFormatUtilities::fill_M_HDR_w1 |
( |
const uint64_t & |
flag, |
|
|
const uint64_t & |
modid, |
|
|
const uint64_t & |
modhash, |
|
|
const uint64_t & |
spare |
|
) |
| |
|
inline |
◆ fill_PIXEL_CLUSTER()
◆ fill_PIXEL_EF_RDO()
◆ fill_RD_HDR_w1()
RD_HDR_w1 FPGADataFormatUtilities::fill_RD_HDR_w1 |
( |
const uint64_t & |
flag, |
|
|
const uint64_t & |
type, |
|
|
const uint64_t & |
eta_region, |
|
|
const uint64_t & |
phi_region, |
|
|
const uint64_t & |
slice, |
|
|
const uint64_t & |
hough_x_bin, |
|
|
const uint64_t & |
hough_y_bin, |
|
|
const uint64_t & |
second_stage, |
|
|
const uint64_t & |
layer_bitmask, |
|
|
const uint64_t & |
spare |
|
) |
| |
|
inline |
Definition at line 580 of file FPGADataFormatUtilities.h.
584 temp.eta_region = eta_region;
585 temp.phi_region = phi_region;
587 temp.hough_x_bin = hough_x_bin;
588 temp.hough_y_bin = hough_y_bin;
589 temp.second_stage = second_stage;
590 temp.layer_bitmask = layer_bitmask;
◆ fill_RD_HDR_w2()
RD_HDR_w2 FPGADataFormatUtilities::fill_RD_HDR_w2 |
( |
const uint64_t & |
global_phi, |
|
|
const uint64_t & |
global_eta, |
|
|
const uint64_t & |
spare |
|
) |
| |
|
inline |
◆ fill_SLICE_HDR_w1()
SLICE_HDR_w1 FPGADataFormatUtilities::fill_SLICE_HDR_w1 |
( |
const uint64_t & |
flag, |
|
|
const uint64_t & |
sliceid, |
|
|
const uint64_t & |
eta_region, |
|
|
const uint64_t & |
phi_region, |
|
|
const uint64_t & |
spare |
|
) |
| |
|
inline |
Definition at line 428 of file FPGADataFormatUtilities.h.
431 temp.sliceid = sliceid;
432 temp.eta_region = eta_region;
433 temp.phi_region = phi_region;
◆ fill_STRIP_CLUSTER()
◆ fill_STRIP_EF_RDO()
STRIP_EF_RDO FPGADataFormatUtilities::fill_STRIP_EF_RDO |
( |
const uint64_t & |
last, |
|
|
const uint64_t & |
chipid, |
|
|
const uint64_t & |
strip_num, |
|
|
const uint64_t & |
cluster_map, |
|
|
const uint64_t & |
spare |
|
) |
| |
|
inline |
Definition at line 2356 of file FPGADataFormatUtilities.h.
2359 temp.chipid = chipid;
2360 temp.strip_num = strip_num;
2361 temp.cluster_map = cluster_map;
◆ get_bitfields_EDM_PIXELCLUSTER_w1()
◆ get_bitfields_EDM_PIXELCLUSTER_w10()
◆ get_bitfields_EDM_PIXELCLUSTER_w2()
◆ get_bitfields_EDM_PIXELCLUSTER_w3()
◆ get_bitfields_EDM_PIXELCLUSTER_w4()
◆ get_bitfields_EDM_PIXELCLUSTER_w5()
◆ get_bitfields_EDM_PIXELCLUSTER_w6()
◆ get_bitfields_EDM_PIXELCLUSTER_w7()
◆ get_bitfields_EDM_PIXELCLUSTER_w8()
◆ get_bitfields_EDM_PIXELCLUSTER_w9()
◆ get_bitfields_EDM_STRIPCLUSTER_w1()
◆ get_bitfields_EDM_STRIPCLUSTER_w2()
◆ get_bitfields_EDM_STRIPCLUSTER_w3()
◆ get_bitfields_EDM_STRIPCLUSTER_w4()
◆ get_bitfields_EDM_STRIPCLUSTER_w5()
◆ get_bitfields_EDM_STRIPCLUSTER_w6()
◆ get_bitfields_EDM_STRIPCLUSTER_w7()
◆ get_bitfields_EDM_STRIPCLUSTER_w8()
◆ get_bitfields_EDM_STRIPCLUSTER_w9()
◆ get_bitfields_EVT_FTR_w1()
EVT_FTR_w1 FPGADataFormatUtilities::get_bitfields_EVT_FTR_w1 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_EVT_FTR_w2()
EVT_FTR_w2 FPGADataFormatUtilities::get_bitfields_EVT_FTR_w2 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_EVT_FTR_w3()
EVT_FTR_w3 FPGADataFormatUtilities::get_bitfields_EVT_FTR_w3 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_EVT_HDR_w1()
EVT_HDR_w1 FPGADataFormatUtilities::get_bitfields_EVT_HDR_w1 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_EVT_HDR_w2()
EVT_HDR_w2 FPGADataFormatUtilities::get_bitfields_EVT_HDR_w2 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_EVT_HDR_w3()
EVT_HDR_w3 FPGADataFormatUtilities::get_bitfields_EVT_HDR_w3 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_GHITZ_w1()
GHITZ_w1 FPGADataFormatUtilities::get_bitfields_GHITZ_w1 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_GHITZ_w2()
GHITZ_w2 FPGADataFormatUtilities::get_bitfields_GHITZ_w2 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_GTRACK_HDR_w1()
◆ get_bitfields_GTRACK_HDR_w2()
◆ get_bitfields_GTRACK_HDR_w3()
◆ get_bitfields_M_HDR_w1()
M_HDR_w1 FPGADataFormatUtilities::get_bitfields_M_HDR_w1 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_PIXEL_CLUSTER()
◆ get_bitfields_PIXEL_EF_RDO()
PIXEL_EF_RDO FPGADataFormatUtilities::get_bitfields_PIXEL_EF_RDO |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_RD_HDR_w1()
RD_HDR_w1 FPGADataFormatUtilities::get_bitfields_RD_HDR_w1 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_RD_HDR_w2()
RD_HDR_w2 FPGADataFormatUtilities::get_bitfields_RD_HDR_w2 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_SLICE_HDR_w1()
SLICE_HDR_w1 FPGADataFormatUtilities::get_bitfields_SLICE_HDR_w1 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_bitfields_STRIP_CLUSTER()
◆ get_bitfields_STRIP_EF_RDO()
STRIP_EF_RDO FPGADataFormatUtilities::get_bitfields_STRIP_EF_RDO |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_dataformat_EDM_PIXELCLUSTER_w1()
◆ get_dataformat_EDM_PIXELCLUSTER_w10()
◆ get_dataformat_EDM_PIXELCLUSTER_w2()
◆ get_dataformat_EDM_PIXELCLUSTER_w3()
◆ get_dataformat_EDM_PIXELCLUSTER_w4()
◆ get_dataformat_EDM_PIXELCLUSTER_w5()
◆ get_dataformat_EDM_PIXELCLUSTER_w6()
◆ get_dataformat_EDM_PIXELCLUSTER_w7()
◆ get_dataformat_EDM_PIXELCLUSTER_w8()
◆ get_dataformat_EDM_PIXELCLUSTER_w9()
◆ get_dataformat_EDM_STRIPCLUSTER_w1()
◆ get_dataformat_EDM_STRIPCLUSTER_w2()
◆ get_dataformat_EDM_STRIPCLUSTER_w3()
◆ get_dataformat_EDM_STRIPCLUSTER_w4()
◆ get_dataformat_EDM_STRIPCLUSTER_w5()
◆ get_dataformat_EDM_STRIPCLUSTER_w6()
◆ get_dataformat_EDM_STRIPCLUSTER_w7()
◆ get_dataformat_EDM_STRIPCLUSTER_w8()
◆ get_dataformat_EDM_STRIPCLUSTER_w9()
◆ get_dataformat_EVT_FTR_w1()
uint64_t FPGADataFormatUtilities::get_dataformat_EVT_FTR_w1 |
( |
const EVT_FTR_w1 & |
in | ) |
|
|
inline |
◆ get_dataformat_EVT_FTR_w2()
uint64_t FPGADataFormatUtilities::get_dataformat_EVT_FTR_w2 |
( |
const EVT_FTR_w2 & |
in | ) |
|
|
inline |
◆ get_dataformat_EVT_FTR_w3()
uint64_t FPGADataFormatUtilities::get_dataformat_EVT_FTR_w3 |
( |
const EVT_FTR_w3 & |
in | ) |
|
|
inline |
◆ get_dataformat_EVT_HDR_w1()
uint64_t FPGADataFormatUtilities::get_dataformat_EVT_HDR_w1 |
( |
const EVT_HDR_w1 & |
in | ) |
|
|
inline |
◆ get_dataformat_EVT_HDR_w2()
uint64_t FPGADataFormatUtilities::get_dataformat_EVT_HDR_w2 |
( |
const EVT_HDR_w2 & |
in | ) |
|
|
inline |
◆ get_dataformat_EVT_HDR_w3()
uint64_t FPGADataFormatUtilities::get_dataformat_EVT_HDR_w3 |
( |
const EVT_HDR_w3 & |
in | ) |
|
|
inline |
◆ get_dataformat_GHITZ_w1()
uint64_t FPGADataFormatUtilities::get_dataformat_GHITZ_w1 |
( |
const GHITZ_w1 & |
in | ) |
|
|
inline |
◆ get_dataformat_GHITZ_w2()
uint64_t FPGADataFormatUtilities::get_dataformat_GHITZ_w2 |
( |
const GHITZ_w2 & |
in | ) |
|
|
inline |
◆ get_dataformat_GTRACK_HDR_w1()
uint64_t FPGADataFormatUtilities::get_dataformat_GTRACK_HDR_w1 |
( |
const GTRACK_HDR_w1 & |
in | ) |
|
|
inline |
◆ get_dataformat_GTRACK_HDR_w2()
uint64_t FPGADataFormatUtilities::get_dataformat_GTRACK_HDR_w2 |
( |
const GTRACK_HDR_w2 & |
in | ) |
|
|
inline |
◆ get_dataformat_GTRACK_HDR_w3()
uint64_t FPGADataFormatUtilities::get_dataformat_GTRACK_HDR_w3 |
( |
const GTRACK_HDR_w3 & |
in | ) |
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|
inline |
◆ get_dataformat_M_HDR_w1()
uint64_t FPGADataFormatUtilities::get_dataformat_M_HDR_w1 |
( |
const M_HDR_w1 & |
in | ) |
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|
inline |
◆ get_dataformat_PIXEL_CLUSTER()
uint64_t FPGADataFormatUtilities::get_dataformat_PIXEL_CLUSTER |
( |
const PIXEL_CLUSTER & |
in | ) |
|
|
inline |
◆ get_dataformat_PIXEL_EF_RDO()
uint64_t FPGADataFormatUtilities::get_dataformat_PIXEL_EF_RDO |
( |
const PIXEL_EF_RDO & |
in | ) |
|
|
inline |
◆ get_dataformat_RD_HDR_w1()
uint64_t FPGADataFormatUtilities::get_dataformat_RD_HDR_w1 |
( |
const RD_HDR_w1 & |
in | ) |
|
|
inline |
◆ get_dataformat_RD_HDR_w2()
uint64_t FPGADataFormatUtilities::get_dataformat_RD_HDR_w2 |
( |
const RD_HDR_w2 & |
in | ) |
|
|
inline |
◆ get_dataformat_SLICE_HDR_w1()
uint64_t FPGADataFormatUtilities::get_dataformat_SLICE_HDR_w1 |
( |
const SLICE_HDR_w1 & |
in | ) |
|
|
inline |
◆ get_dataformat_STRIP_CLUSTER()
uint64_t FPGADataFormatUtilities::get_dataformat_STRIP_CLUSTER |
( |
const STRIP_CLUSTER & |
in | ) |
|
|
inline |
◆ get_dataformat_STRIP_CLUSTER_64()
uint64_t FPGADataFormatUtilities::get_dataformat_STRIP_CLUSTER_64 |
( |
const uint64_t & |
up, |
|
|
const uint64_t & |
low |
|
) |
| |
|
inline |
◆ get_dataformat_STRIP_CLUSTER_low32()
uint64_t FPGADataFormatUtilities::get_dataformat_STRIP_CLUSTER_low32 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_dataformat_STRIP_CLUSTER_up32()
uint64_t FPGADataFormatUtilities::get_dataformat_STRIP_CLUSTER_up32 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_dataformat_STRIP_EF_RDO()
uint64_t FPGADataFormatUtilities::get_dataformat_STRIP_EF_RDO |
( |
const STRIP_EF_RDO & |
in | ) |
|
|
inline |
◆ get_dataformat_STRIP_EF_RDO_64()
uint64_t FPGADataFormatUtilities::get_dataformat_STRIP_EF_RDO_64 |
( |
const uint64_t & |
up, |
|
|
const uint64_t & |
low |
|
) |
| |
|
inline |
◆ get_dataformat_STRIP_EF_RDO_low32()
uint64_t FPGADataFormatUtilities::get_dataformat_STRIP_EF_RDO_low32 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ get_dataformat_STRIP_EF_RDO_up32()
uint64_t FPGADataFormatUtilities::get_dataformat_STRIP_EF_RDO_up32 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ SELECTBITS()
consteval uint64_t FPGADataFormatUtilities::SELECTBITS |
( |
uint8_t |
len, |
|
|
uint8_t |
startbit |
|
) |
| |
Definition at line 14 of file FPGADataFormatUtilities.h.
15 return (len == 64 ? 0xFFFFFFFFFFFFFFFFULL : (((1ULL << len) - 1ULL) << startbit));
◆ to_real_EDM_PIXELCLUSTER_w10_globalposition_z()
double FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w10_globalposition_z |
( |
const int64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w10_lastword()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w10_lastword |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w10_spare()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w10_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w10_total_tot()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w10_total_tot |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w1_flag()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w1_flag |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w1_id_hash()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w1_id_hash |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w1_spare()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w1_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w2_identifier()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w2_identifier |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w3_rdo_list_w1()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w3_rdo_list_w1 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w4_rdo_list_w2()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w4_rdo_list_w2 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w5_rdo_list_w3()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w5_rdo_list_w3 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w6_rdo_list_w4()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w6_rdo_list_w4 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w7_channels_in_eta()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w7_channels_in_eta |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w7_channels_in_phi()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w7_channels_in_phi |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w7_localposition_x()
double FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w7_localposition_x |
( |
const int64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w7_localposition_y()
double FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w7_localposition_y |
( |
const int64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w7_spare()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w7_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w7_width_in_eta()
double FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w7_width_in_eta |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w8_localcovariance_xx()
double FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w8_localcovariance_xx |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w8_localcovariance_yy()
double FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w8_localcovariance_yy |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w8_omega_x()
double FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w8_omega_x |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w8_omega_y()
double FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w8_omega_y |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w8_spare()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w8_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w9_globalposition_x()
double FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w9_globalposition_x |
( |
const int64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w9_globalposition_y()
double FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w9_globalposition_y |
( |
const int64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_PIXELCLUSTER_w9_spare()
uint64_t FPGADataFormatUtilities::to_real_EDM_PIXELCLUSTER_w9_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w1_flag()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w1_flag |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w1_id_hash()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w1_id_hash |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w1_spare()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w1_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w2_identifier()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w2_identifier |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w3_rdo_list_w1()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w3_rdo_list_w1 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w4_rdo_list_w2()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w4_rdo_list_w2 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w5_rdo_list_w3()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w5_rdo_list_w3 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w6_rdo_list_w4()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w6_rdo_list_w4 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w7_localcovariance_xx()
double FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w7_localcovariance_xx |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w7_localposition_x()
double FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w7_localposition_x |
( |
const int64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w7_localposition_y()
double FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w7_localposition_y |
( |
const int64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w7_spare()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w7_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w8_channels_in_phi()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w8_channels_in_phi |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w8_globalposition_x()
double FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w8_globalposition_x |
( |
const int64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w8_globalposition_y()
double FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w8_globalposition_y |
( |
const int64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w8_spare()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w8_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w9_globalposition_z()
double FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w9_globalposition_z |
( |
const int64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w9_index()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w9_index |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w9_lastword()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w9_lastword |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EDM_STRIPCLUSTER_w9_spare()
uint64_t FPGADataFormatUtilities::to_real_EDM_STRIPCLUSTER_w9_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_FTR_w1_flag()
uint64_t FPGADataFormatUtilities::to_real_EVT_FTR_w1_flag |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_FTR_w1_hdr_crc()
uint64_t FPGADataFormatUtilities::to_real_EVT_FTR_w1_hdr_crc |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_FTR_w1_spare()
uint64_t FPGADataFormatUtilities::to_real_EVT_FTR_w1_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_FTR_w2_error_flags()
uint64_t FPGADataFormatUtilities::to_real_EVT_FTR_w2_error_flags |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_FTR_w3_crc()
uint64_t FPGADataFormatUtilities::to_real_EVT_FTR_w3_crc |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_FTR_w3_word_count()
uint64_t FPGADataFormatUtilities::to_real_EVT_FTR_w3_word_count |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_HDR_w1_bcid()
uint64_t FPGADataFormatUtilities::to_real_EVT_HDR_w1_bcid |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_HDR_w1_flag()
uint64_t FPGADataFormatUtilities::to_real_EVT_HDR_w1_flag |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_HDR_w1_l0id()
uint64_t FPGADataFormatUtilities::to_real_EVT_HDR_w1_l0id |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_HDR_w1_spare()
uint64_t FPGADataFormatUtilities::to_real_EVT_HDR_w1_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_HDR_w2_runnumber()
uint64_t FPGADataFormatUtilities::to_real_EVT_HDR_w2_runnumber |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_HDR_w2_time()
uint64_t FPGADataFormatUtilities::to_real_EVT_HDR_w2_time |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_HDR_w3_crc()
uint64_t FPGADataFormatUtilities::to_real_EVT_HDR_w3_crc |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_EVT_HDR_w3_status()
uint64_t FPGADataFormatUtilities::to_real_EVT_HDR_w3_status |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GHITZ_w1_last()
uint64_t FPGADataFormatUtilities::to_real_GHITZ_w1_last |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GHITZ_w1_lastofslice()
uint64_t FPGADataFormatUtilities::to_real_GHITZ_w1_lastofslice |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GHITZ_w1_lyr()
uint64_t FPGADataFormatUtilities::to_real_GHITZ_w1_lyr |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GHITZ_w1_phi()
double FPGADataFormatUtilities::to_real_GHITZ_w1_phi |
( |
const int64_t & |
in | ) |
|
|
inline |
◆ to_real_GHITZ_w1_rad()
double FPGADataFormatUtilities::to_real_GHITZ_w1_rad |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GHITZ_w1_spare()
uint64_t FPGADataFormatUtilities::to_real_GHITZ_w1_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GHITZ_w1_z()
double FPGADataFormatUtilities::to_real_GHITZ_w1_z |
( |
const int64_t & |
in | ) |
|
|
inline |
◆ to_real_GHITZ_w2_cluster1()
uint64_t FPGADataFormatUtilities::to_real_GHITZ_w2_cluster1 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GHITZ_w2_cluster2()
uint64_t FPGADataFormatUtilities::to_real_GHITZ_w2_cluster2 |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GHITZ_w2_row()
uint64_t FPGADataFormatUtilities::to_real_GHITZ_w2_row |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GHITZ_w2_spare()
uint64_t FPGADataFormatUtilities::to_real_GHITZ_w2_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GTRACK_HDR_w1_eta_region()
uint64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w1_eta_region |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GTRACK_HDR_w1_flag()
uint64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w1_flag |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GTRACK_HDR_w1_hough_x_bin()
uint64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w1_hough_x_bin |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_GTRACK_HDR_w1_hough_y_bin()
uint64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w1_hough_y_bin |
( |
const uint64_t & |
in | ) |
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|
inline |
◆ to_real_GTRACK_HDR_w1_layer_bitmask()
uint64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w1_layer_bitmask |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_GTRACK_HDR_w1_phi_region()
uint64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w1_phi_region |
( |
const uint64_t & |
in | ) |
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|
inline |
◆ to_real_GTRACK_HDR_w1_second_stage()
uint64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w1_second_stage |
( |
const uint64_t & |
in | ) |
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|
inline |
◆ to_real_GTRACK_HDR_w1_slice()
uint64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w1_slice |
( |
const uint64_t & |
in | ) |
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|
inline |
◆ to_real_GTRACK_HDR_w1_spare()
uint64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w1_spare |
( |
const uint64_t & |
in | ) |
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|
inline |
◆ to_real_GTRACK_HDR_w1_type()
uint64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w1_type |
( |
const uint64_t & |
in | ) |
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|
inline |
◆ to_real_GTRACK_HDR_w2_d0()
double FPGADataFormatUtilities::to_real_GTRACK_HDR_w2_d0 |
( |
const int64_t & |
in | ) |
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|
inline |
◆ to_real_GTRACK_HDR_w2_score()
double FPGADataFormatUtilities::to_real_GTRACK_HDR_w2_score |
( |
const uint64_t & |
in | ) |
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|
inline |
◆ to_real_GTRACK_HDR_w2_spare()
uint64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w2_spare |
( |
const uint64_t & |
in | ) |
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|
inline |
◆ to_real_GTRACK_HDR_w2_z0()
double FPGADataFormatUtilities::to_real_GTRACK_HDR_w2_z0 |
( |
const int64_t & |
in | ) |
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inline |
◆ to_real_GTRACK_HDR_w3_eta()
int64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w3_eta |
( |
const int64_t & |
in | ) |
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inline |
◆ to_real_GTRACK_HDR_w3_phi()
int64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w3_phi |
( |
const int64_t & |
in | ) |
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inline |
◆ to_real_GTRACK_HDR_w3_qoverpt()
int64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w3_qoverpt |
( |
const int64_t & |
in | ) |
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inline |
◆ to_real_GTRACK_HDR_w3_spare()
uint64_t FPGADataFormatUtilities::to_real_GTRACK_HDR_w3_spare |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_M_HDR_w1_flag()
uint64_t FPGADataFormatUtilities::to_real_M_HDR_w1_flag |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_M_HDR_w1_modhash()
uint64_t FPGADataFormatUtilities::to_real_M_HDR_w1_modhash |
( |
const uint64_t & |
in | ) |
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|
inline |
◆ to_real_M_HDR_w1_modid()
uint64_t FPGADataFormatUtilities::to_real_M_HDR_w1_modid |
( |
const uint64_t & |
in | ) |
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|
inline |
◆ to_real_M_HDR_w1_spare()
uint64_t FPGADataFormatUtilities::to_real_M_HDR_w1_spare |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_PIXEL_CLUSTER_centroid_col()
double FPGADataFormatUtilities::to_real_PIXEL_CLUSTER_centroid_col |
( |
const uint64_t & |
in | ) |
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|
inline |
◆ to_real_PIXEL_CLUSTER_centroid_row()
double FPGADataFormatUtilities::to_real_PIXEL_CLUSTER_centroid_row |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_PIXEL_CLUSTER_col()
uint64_t FPGADataFormatUtilities::to_real_PIXEL_CLUSTER_col |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_PIXEL_CLUSTER_last()
uint64_t FPGADataFormatUtilities::to_real_PIXEL_CLUSTER_last |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_PIXEL_CLUSTER_row()
uint64_t FPGADataFormatUtilities::to_real_PIXEL_CLUSTER_row |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_PIXEL_CLUSTER_spare()
uint64_t FPGADataFormatUtilities::to_real_PIXEL_CLUSTER_spare |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_PIXEL_EF_RDO_col()
uint64_t FPGADataFormatUtilities::to_real_PIXEL_EF_RDO_col |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_PIXEL_EF_RDO_last()
uint64_t FPGADataFormatUtilities::to_real_PIXEL_EF_RDO_last |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_PIXEL_EF_RDO_lvl1()
uint64_t FPGADataFormatUtilities::to_real_PIXEL_EF_RDO_lvl1 |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_PIXEL_EF_RDO_row()
uint64_t FPGADataFormatUtilities::to_real_PIXEL_EF_RDO_row |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_PIXEL_EF_RDO_spare()
uint64_t FPGADataFormatUtilities::to_real_PIXEL_EF_RDO_spare |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_PIXEL_EF_RDO_tot()
uint64_t FPGADataFormatUtilities::to_real_PIXEL_EF_RDO_tot |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_RD_HDR_w1_eta_region()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w1_eta_region |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_RD_HDR_w1_flag()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w1_flag |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_RD_HDR_w1_hough_x_bin()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w1_hough_x_bin |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_RD_HDR_w1_hough_y_bin()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w1_hough_y_bin |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_RD_HDR_w1_layer_bitmask()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w1_layer_bitmask |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_RD_HDR_w1_phi_region()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w1_phi_region |
( |
const uint64_t & |
in | ) |
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inline |
◆ to_real_RD_HDR_w1_second_stage()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w1_second_stage |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_RD_HDR_w1_slice()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w1_slice |
( |
const uint64_t & |
in | ) |
|
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inline |
◆ to_real_RD_HDR_w1_spare()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w1_spare |
( |
const uint64_t & |
in | ) |
|
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inline |
◆ to_real_RD_HDR_w1_type()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w1_type |
( |
const uint64_t & |
in | ) |
|
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inline |
◆ to_real_RD_HDR_w2_global_eta()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w2_global_eta |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_RD_HDR_w2_global_phi()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w2_global_phi |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_RD_HDR_w2_spare()
uint64_t FPGADataFormatUtilities::to_real_RD_HDR_w2_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_SLICE_HDR_w1_eta_region()
uint64_t FPGADataFormatUtilities::to_real_SLICE_HDR_w1_eta_region |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_SLICE_HDR_w1_flag()
uint64_t FPGADataFormatUtilities::to_real_SLICE_HDR_w1_flag |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_SLICE_HDR_w1_phi_region()
uint64_t FPGADataFormatUtilities::to_real_SLICE_HDR_w1_phi_region |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_SLICE_HDR_w1_sliceid()
uint64_t FPGADataFormatUtilities::to_real_SLICE_HDR_w1_sliceid |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_SLICE_HDR_w1_spare()
uint64_t FPGADataFormatUtilities::to_real_SLICE_HDR_w1_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_STRIP_CLUSTER_last()
uint64_t FPGADataFormatUtilities::to_real_STRIP_CLUSTER_last |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_STRIP_CLUSTER_nstrips()
uint64_t FPGADataFormatUtilities::to_real_STRIP_CLUSTER_nstrips |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_STRIP_CLUSTER_row()
uint64_t FPGADataFormatUtilities::to_real_STRIP_CLUSTER_row |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_STRIP_CLUSTER_spare()
uint64_t FPGADataFormatUtilities::to_real_STRIP_CLUSTER_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_STRIP_CLUSTER_strip_index()
uint64_t FPGADataFormatUtilities::to_real_STRIP_CLUSTER_strip_index |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_STRIP_EF_RDO_chipid()
uint64_t FPGADataFormatUtilities::to_real_STRIP_EF_RDO_chipid |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_STRIP_EF_RDO_cluster_map()
uint64_t FPGADataFormatUtilities::to_real_STRIP_EF_RDO_cluster_map |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_STRIP_EF_RDO_last()
uint64_t FPGADataFormatUtilities::to_real_STRIP_EF_RDO_last |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_STRIP_EF_RDO_spare()
uint64_t FPGADataFormatUtilities::to_real_STRIP_EF_RDO_spare |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ to_real_STRIP_EF_RDO_strip_num()
uint64_t FPGADataFormatUtilities::to_real_STRIP_EF_RDO_strip_num |
( |
const uint64_t & |
in | ) |
|
|
inline |
◆ EDM_PIXELCLUSTER_FLAG
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_FLAG = 0x77 |
◆ EDM_PIXELCLUSTER_W10_GLOBALPOSITION_Z_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W10_GLOBALPOSITION_Z_bits = 29 |
◆ EDM_PIXELCLUSTER_W10_GLOBALPOSITION_Z_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W10_GLOBALPOSITION_Z_lsb = 35 |
◆ EDM_PIXELCLUSTER_W10_GLOBALPOSITION_Z_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W10_GLOBALPOSITION_Z_mf = 65536. |
◆ EDM_PIXELCLUSTER_W10_LASTWORD_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W10_LASTWORD_bits = 1 |
◆ EDM_PIXELCLUSTER_W10_LASTWORD_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W10_LASTWORD_lsb = 25 |
◆ EDM_PIXELCLUSTER_W10_LASTWORD_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W10_LASTWORD_mf = 1. |
◆ EDM_PIXELCLUSTER_W10_SPARE_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W10_SPARE_bits = 25 |
◆ EDM_PIXELCLUSTER_W10_SPARE_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W10_SPARE_lsb = 0 |
◆ EDM_PIXELCLUSTER_W10_SPARE_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W10_SPARE_mf = 1. |
◆ EDM_PIXELCLUSTER_W10_TOTAL_TOT_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W10_TOTAL_TOT_bits = 9 |
◆ EDM_PIXELCLUSTER_W10_TOTAL_TOT_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W10_TOTAL_TOT_lsb = 26 |
◆ EDM_PIXELCLUSTER_W10_TOTAL_TOT_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W10_TOTAL_TOT_mf = 1. |
◆ EDM_PIXELCLUSTER_W1_FLAG_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W1_FLAG_bits = 8 |
◆ EDM_PIXELCLUSTER_W1_FLAG_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W1_FLAG_lsb = 56 |
◆ EDM_PIXELCLUSTER_W1_FLAG_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W1_FLAG_mf = 1. |
◆ EDM_PIXELCLUSTER_W1_ID_HASH_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W1_ID_HASH_bits = 32 |
◆ EDM_PIXELCLUSTER_W1_ID_HASH_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W1_ID_HASH_lsb = 24 |
◆ EDM_PIXELCLUSTER_W1_ID_HASH_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W1_ID_HASH_mf = 1. |
◆ EDM_PIXELCLUSTER_W1_Spare_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W1_Spare_bits = 24 |
◆ EDM_PIXELCLUSTER_W1_Spare_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W1_Spare_lsb = 0 |
◆ EDM_PIXELCLUSTER_W1_Spare_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W1_Spare_mf = 1. |
◆ EDM_PIXELCLUSTER_W2_IDENTIFIER_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W2_IDENTIFIER_bits = 64 |
◆ EDM_PIXELCLUSTER_W2_IDENTIFIER_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W2_IDENTIFIER_lsb = 0 |
◆ EDM_PIXELCLUSTER_W2_IDENTIFIER_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W2_IDENTIFIER_mf = 1. |
◆ EDM_PIXELCLUSTER_W3_RDO_LIST_W1_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W3_RDO_LIST_W1_bits = 64 |
◆ EDM_PIXELCLUSTER_W3_RDO_LIST_W1_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W3_RDO_LIST_W1_lsb = 0 |
◆ EDM_PIXELCLUSTER_W3_RDO_LIST_W1_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W3_RDO_LIST_W1_mf = 1. |
◆ EDM_PIXELCLUSTER_W4_RDO_LIST_W2_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W4_RDO_LIST_W2_bits = 64 |
◆ EDM_PIXELCLUSTER_W4_RDO_LIST_W2_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W4_RDO_LIST_W2_lsb = 0 |
◆ EDM_PIXELCLUSTER_W4_RDO_LIST_W2_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W4_RDO_LIST_W2_mf = 1. |
◆ EDM_PIXELCLUSTER_W5_RDO_LIST_W3_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W5_RDO_LIST_W3_bits = 64 |
◆ EDM_PIXELCLUSTER_W5_RDO_LIST_W3_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W5_RDO_LIST_W3_lsb = 0 |
◆ EDM_PIXELCLUSTER_W5_RDO_LIST_W3_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W5_RDO_LIST_W3_mf = 1. |
◆ EDM_PIXELCLUSTER_W6_RDO_LIST_W4_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W6_RDO_LIST_W4_bits = 64 |
◆ EDM_PIXELCLUSTER_W6_RDO_LIST_W4_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W6_RDO_LIST_W4_lsb = 0 |
◆ EDM_PIXELCLUSTER_W6_RDO_LIST_W4_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W6_RDO_LIST_W4_mf = 1. |
◆ EDM_PIXELCLUSTER_W7_CHANNELS_IN_ETA_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_CHANNELS_IN_ETA_bits = 8 |
◆ EDM_PIXELCLUSTER_W7_CHANNELS_IN_ETA_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_CHANNELS_IN_ETA_lsb = 8 |
◆ EDM_PIXELCLUSTER_W7_CHANNELS_IN_ETA_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_CHANNELS_IN_ETA_mf = 1. |
◆ EDM_PIXELCLUSTER_W7_CHANNELS_IN_PHI_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_CHANNELS_IN_PHI_bits = 8 |
◆ EDM_PIXELCLUSTER_W7_CHANNELS_IN_PHI_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_CHANNELS_IN_PHI_lsb = 16 |
◆ EDM_PIXELCLUSTER_W7_CHANNELS_IN_PHI_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_CHANNELS_IN_PHI_mf = 1. |
◆ EDM_PIXELCLUSTER_W7_LOCALPOSITION_X_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_LOCALPOSITION_X_bits = 20 |
◆ EDM_PIXELCLUSTER_W7_LOCALPOSITION_X_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_LOCALPOSITION_X_lsb = 44 |
◆ EDM_PIXELCLUSTER_W7_LOCALPOSITION_X_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_LOCALPOSITION_X_mf = 8192. |
◆ EDM_PIXELCLUSTER_W7_LOCALPOSITION_Y_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_LOCALPOSITION_Y_bits = 20 |
◆ EDM_PIXELCLUSTER_W7_LOCALPOSITION_Y_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_LOCALPOSITION_Y_lsb = 24 |
◆ EDM_PIXELCLUSTER_W7_LOCALPOSITION_Y_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_LOCALPOSITION_Y_mf = 8192. |
◆ EDM_PIXELCLUSTER_W7_SPARE_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_SPARE_bits = 2 |
◆ EDM_PIXELCLUSTER_W7_SPARE_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_SPARE_lsb = 0 |
◆ EDM_PIXELCLUSTER_W7_SPARE_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_SPARE_mf = 1. |
◆ EDM_PIXELCLUSTER_W7_WIDTH_IN_ETA_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_WIDTH_IN_ETA_bits = 6 |
◆ EDM_PIXELCLUSTER_W7_WIDTH_IN_ETA_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_WIDTH_IN_ETA_lsb = 2 |
◆ EDM_PIXELCLUSTER_W7_WIDTH_IN_ETA_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W7_WIDTH_IN_ETA_mf = 32. |
◆ EDM_PIXELCLUSTER_W8_LOCALCOVARIANCE_XX_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_LOCALCOVARIANCE_XX_bits = 20 |
◆ EDM_PIXELCLUSTER_W8_LOCALCOVARIANCE_XX_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_LOCALCOVARIANCE_XX_lsb = 44 |
◆ EDM_PIXELCLUSTER_W8_LOCALCOVARIANCE_XX_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_LOCALCOVARIANCE_XX_mf = 524288. |
◆ EDM_PIXELCLUSTER_W8_LOCALCOVARIANCE_YY_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_LOCALCOVARIANCE_YY_bits = 20 |
◆ EDM_PIXELCLUSTER_W8_LOCALCOVARIANCE_YY_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_LOCALCOVARIANCE_YY_lsb = 24 |
◆ EDM_PIXELCLUSTER_W8_LOCALCOVARIANCE_YY_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_LOCALCOVARIANCE_YY_mf = 524288. |
◆ EDM_PIXELCLUSTER_W8_OMEGA_X_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_OMEGA_X_bits = 10 |
◆ EDM_PIXELCLUSTER_W8_OMEGA_X_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_OMEGA_X_lsb = 14 |
◆ EDM_PIXELCLUSTER_W8_OMEGA_X_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_OMEGA_X_mf = 512. |
◆ EDM_PIXELCLUSTER_W8_OMEGA_Y_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_OMEGA_Y_bits = 10 |
◆ EDM_PIXELCLUSTER_W8_OMEGA_Y_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_OMEGA_Y_lsb = 4 |
◆ EDM_PIXELCLUSTER_W8_OMEGA_Y_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_OMEGA_Y_mf = 512. |
◆ EDM_PIXELCLUSTER_W8_SPARE_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_SPARE_bits = 4 |
◆ EDM_PIXELCLUSTER_W8_SPARE_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_SPARE_lsb = 0 |
◆ EDM_PIXELCLUSTER_W8_SPARE_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W8_SPARE_mf = 1. |
◆ EDM_PIXELCLUSTER_W9_GLOBALPOSITION_X_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W9_GLOBALPOSITION_X_bits = 26 |
◆ EDM_PIXELCLUSTER_W9_GLOBALPOSITION_X_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W9_GLOBALPOSITION_X_lsb = 38 |
◆ EDM_PIXELCLUSTER_W9_GLOBALPOSITION_X_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W9_GLOBALPOSITION_X_mf = 65536. |
◆ EDM_PIXELCLUSTER_W9_GLOBALPOSITION_Y_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W9_GLOBALPOSITION_Y_bits = 26 |
◆ EDM_PIXELCLUSTER_W9_GLOBALPOSITION_Y_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W9_GLOBALPOSITION_Y_lsb = 12 |
◆ EDM_PIXELCLUSTER_W9_GLOBALPOSITION_Y_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W9_GLOBALPOSITION_Y_mf = 65536. |
◆ EDM_PIXELCLUSTER_W9_SPARE_bits
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W9_SPARE_bits = 12 |
◆ EDM_PIXELCLUSTER_W9_SPARE_lsb
const int FPGADataFormatUtilities::EDM_PIXELCLUSTER_W9_SPARE_lsb = 0 |
◆ EDM_PIXELCLUSTER_W9_SPARE_mf
const float FPGADataFormatUtilities::EDM_PIXELCLUSTER_W9_SPARE_mf = 1. |
◆ EDM_STRIPCLUSTER_FLAG
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_FLAG = 0x66 |
◆ EDM_STRIPCLUSTER_W1_FLAG_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W1_FLAG_bits = 8 |
◆ EDM_STRIPCLUSTER_W1_FLAG_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W1_FLAG_lsb = 56 |
◆ EDM_STRIPCLUSTER_W1_FLAG_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W1_FLAG_mf = 1. |
◆ EDM_STRIPCLUSTER_W1_ID_HASH_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W1_ID_HASH_bits = 32 |
◆ EDM_STRIPCLUSTER_W1_ID_HASH_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W1_ID_HASH_lsb = 24 |
◆ EDM_STRIPCLUSTER_W1_ID_HASH_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W1_ID_HASH_mf = 1. |
◆ EDM_STRIPCLUSTER_W1_Spare_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W1_Spare_bits = 24 |
◆ EDM_STRIPCLUSTER_W1_Spare_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W1_Spare_lsb = 0 |
◆ EDM_STRIPCLUSTER_W1_Spare_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W1_Spare_mf = 1. |
◆ EDM_STRIPCLUSTER_W2_IDENTIFIER_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W2_IDENTIFIER_bits = 64 |
◆ EDM_STRIPCLUSTER_W2_IDENTIFIER_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W2_IDENTIFIER_lsb = 0 |
◆ EDM_STRIPCLUSTER_W2_IDENTIFIER_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W2_IDENTIFIER_mf = 1. |
◆ EDM_STRIPCLUSTER_W3_RDO_LIST_W1_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W3_RDO_LIST_W1_bits = 64 |
◆ EDM_STRIPCLUSTER_W3_RDO_LIST_W1_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W3_RDO_LIST_W1_lsb = 0 |
◆ EDM_STRIPCLUSTER_W3_RDO_LIST_W1_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W3_RDO_LIST_W1_mf = 1. |
◆ EDM_STRIPCLUSTER_W4_RDO_LIST_W2_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W4_RDO_LIST_W2_bits = 64 |
◆ EDM_STRIPCLUSTER_W4_RDO_LIST_W2_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W4_RDO_LIST_W2_lsb = 0 |
◆ EDM_STRIPCLUSTER_W4_RDO_LIST_W2_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W4_RDO_LIST_W2_mf = 1. |
◆ EDM_STRIPCLUSTER_W5_RDO_LIST_W3_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W5_RDO_LIST_W3_bits = 64 |
◆ EDM_STRIPCLUSTER_W5_RDO_LIST_W3_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W5_RDO_LIST_W3_lsb = 0 |
◆ EDM_STRIPCLUSTER_W5_RDO_LIST_W3_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W5_RDO_LIST_W3_mf = 1. |
◆ EDM_STRIPCLUSTER_W6_RDO_LIST_W4_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W6_RDO_LIST_W4_bits = 64 |
◆ EDM_STRIPCLUSTER_W6_RDO_LIST_W4_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W6_RDO_LIST_W4_lsb = 0 |
◆ EDM_STRIPCLUSTER_W6_RDO_LIST_W4_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W6_RDO_LIST_W4_mf = 1. |
◆ EDM_STRIPCLUSTER_W7_LOCALCOVARIANCE_XX_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W7_LOCALCOVARIANCE_XX_bits = 20 |
◆ EDM_STRIPCLUSTER_W7_LOCALCOVARIANCE_XX_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W7_LOCALCOVARIANCE_XX_lsb = 2 |
◆ EDM_STRIPCLUSTER_W7_LOCALCOVARIANCE_XX_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W7_LOCALCOVARIANCE_XX_mf = 524288. |
◆ EDM_STRIPCLUSTER_W7_LOCALPOSITION_X_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W7_LOCALPOSITION_X_bits = 21 |
◆ EDM_STRIPCLUSTER_W7_LOCALPOSITION_X_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W7_LOCALPOSITION_X_lsb = 43 |
◆ EDM_STRIPCLUSTER_W7_LOCALPOSITION_X_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W7_LOCALPOSITION_X_mf = 8192. |
◆ EDM_STRIPCLUSTER_W7_LOCALPOSITION_Y_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W7_LOCALPOSITION_Y_bits = 21 |
◆ EDM_STRIPCLUSTER_W7_LOCALPOSITION_Y_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W7_LOCALPOSITION_Y_lsb = 22 |
◆ EDM_STRIPCLUSTER_W7_LOCALPOSITION_Y_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W7_LOCALPOSITION_Y_mf = 8192. |
◆ EDM_STRIPCLUSTER_W7_SPARE_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W7_SPARE_bits = 2 |
◆ EDM_STRIPCLUSTER_W7_SPARE_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W7_SPARE_lsb = 0 |
◆ EDM_STRIPCLUSTER_W7_SPARE_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W7_SPARE_mf = 1. |
◆ EDM_STRIPCLUSTER_W8_CHANNELS_IN_PHI_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W8_CHANNELS_IN_PHI_bits = 6 |
◆ EDM_STRIPCLUSTER_W8_CHANNELS_IN_PHI_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W8_CHANNELS_IN_PHI_lsb = 4 |
◆ EDM_STRIPCLUSTER_W8_CHANNELS_IN_PHI_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W8_CHANNELS_IN_PHI_mf = 1. |
◆ EDM_STRIPCLUSTER_W8_GLOBALPOSITION_X_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W8_GLOBALPOSITION_X_bits = 27 |
◆ EDM_STRIPCLUSTER_W8_GLOBALPOSITION_X_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W8_GLOBALPOSITION_X_lsb = 37 |
◆ EDM_STRIPCLUSTER_W8_GLOBALPOSITION_X_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W8_GLOBALPOSITION_X_mf = 65536. |
◆ EDM_STRIPCLUSTER_W8_GLOBALPOSITION_Y_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W8_GLOBALPOSITION_Y_bits = 27 |
◆ EDM_STRIPCLUSTER_W8_GLOBALPOSITION_Y_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W8_GLOBALPOSITION_Y_lsb = 10 |
◆ EDM_STRIPCLUSTER_W8_GLOBALPOSITION_Y_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W8_GLOBALPOSITION_Y_mf = 65536. |
◆ EDM_STRIPCLUSTER_W8_SPARE_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W8_SPARE_bits = 4 |
◆ EDM_STRIPCLUSTER_W8_SPARE_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W8_SPARE_lsb = 0 |
◆ EDM_STRIPCLUSTER_W8_SPARE_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W8_SPARE_mf = 1. |
◆ EDM_STRIPCLUSTER_W9_GLOBALPOSITION_Z_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W9_GLOBALPOSITION_Z_bits = 29 |
◆ EDM_STRIPCLUSTER_W9_GLOBALPOSITION_Z_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W9_GLOBALPOSITION_Z_lsb = 35 |
◆ EDM_STRIPCLUSTER_W9_GLOBALPOSITION_Z_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W9_GLOBALPOSITION_Z_mf = 65536. |
◆ EDM_STRIPCLUSTER_W9_INDEX_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W9_INDEX_bits = 32 |
◆ EDM_STRIPCLUSTER_W9_INDEX_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W9_INDEX_lsb = 2 |
◆ EDM_STRIPCLUSTER_W9_INDEX_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W9_INDEX_mf = 1. |
◆ EDM_STRIPCLUSTER_W9_LASTWORD_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W9_LASTWORD_bits = 1 |
◆ EDM_STRIPCLUSTER_W9_LASTWORD_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W9_LASTWORD_lsb = 34 |
◆ EDM_STRIPCLUSTER_W9_LASTWORD_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W9_LASTWORD_mf = 1. |
◆ EDM_STRIPCLUSTER_W9_SPARE_bits
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W9_SPARE_bits = 2 |
◆ EDM_STRIPCLUSTER_W9_SPARE_lsb
const int FPGADataFormatUtilities::EDM_STRIPCLUSTER_W9_SPARE_lsb = 0 |
◆ EDM_STRIPCLUSTER_W9_SPARE_mf
const float FPGADataFormatUtilities::EDM_STRIPCLUSTER_W9_SPARE_mf = 1. |
◆ EVT_FTR_FLAG
const int FPGADataFormatUtilities::EVT_FTR_FLAG = 0xcd |
◆ EVT_FTR_W1_FLAG_bits
const int FPGADataFormatUtilities::EVT_FTR_W1_FLAG_bits = 8 |
◆ EVT_FTR_W1_FLAG_lsb
const int FPGADataFormatUtilities::EVT_FTR_W1_FLAG_lsb = 56 |
◆ EVT_FTR_W1_FLAG_mf
const float FPGADataFormatUtilities::EVT_FTR_W1_FLAG_mf = 1. |
◆ EVT_FTR_W1_HDR_CRC_bits
const int FPGADataFormatUtilities::EVT_FTR_W1_HDR_CRC_bits = 32 |
◆ EVT_FTR_W1_HDR_CRC_lsb
const int FPGADataFormatUtilities::EVT_FTR_W1_HDR_CRC_lsb = 0 |
◆ EVT_FTR_W1_HDR_CRC_mf
const float FPGADataFormatUtilities::EVT_FTR_W1_HDR_CRC_mf = 1. |
◆ EVT_FTR_W1_SPARE_bits
const int FPGADataFormatUtilities::EVT_FTR_W1_SPARE_bits = 24 |
◆ EVT_FTR_W1_SPARE_lsb
const int FPGADataFormatUtilities::EVT_FTR_W1_SPARE_lsb = 32 |
◆ EVT_FTR_W1_SPARE_mf
const float FPGADataFormatUtilities::EVT_FTR_W1_SPARE_mf = 1. |
◆ EVT_FTR_W2_ERROR_FLAGS_bits
const int FPGADataFormatUtilities::EVT_FTR_W2_ERROR_FLAGS_bits = 64 |
◆ EVT_FTR_W2_ERROR_FLAGS_lsb
const int FPGADataFormatUtilities::EVT_FTR_W2_ERROR_FLAGS_lsb = 0 |
◆ EVT_FTR_W2_ERROR_FLAGS_mf
const float FPGADataFormatUtilities::EVT_FTR_W2_ERROR_FLAGS_mf = 1. |
◆ EVT_FTR_W3_CRC_bits
const int FPGADataFormatUtilities::EVT_FTR_W3_CRC_bits = 32 |
◆ EVT_FTR_W3_CRC_lsb
const int FPGADataFormatUtilities::EVT_FTR_W3_CRC_lsb = 0 |
◆ EVT_FTR_W3_CRC_mf
const float FPGADataFormatUtilities::EVT_FTR_W3_CRC_mf = 1. |
◆ EVT_FTR_W3_WORD_COUNT_bits
const int FPGADataFormatUtilities::EVT_FTR_W3_WORD_COUNT_bits = 32 |
◆ EVT_FTR_W3_WORD_COUNT_lsb
const int FPGADataFormatUtilities::EVT_FTR_W3_WORD_COUNT_lsb = 32 |
◆ EVT_FTR_W3_WORD_COUNT_mf
const float FPGADataFormatUtilities::EVT_FTR_W3_WORD_COUNT_mf = 1. |
◆ EVT_HDR_FLAG
const int FPGADataFormatUtilities::EVT_HDR_FLAG = 0xab |
◆ EVT_HDR_W1_BCID_bits
const int FPGADataFormatUtilities::EVT_HDR_W1_BCID_bits = 12 |
◆ EVT_HDR_W1_BCID_lsb
const int FPGADataFormatUtilities::EVT_HDR_W1_BCID_lsb = 4 |
◆ EVT_HDR_W1_BCID_mf
const float FPGADataFormatUtilities::EVT_HDR_W1_BCID_mf = 1. |
◆ EVT_HDR_W1_FLAG_bits
const int FPGADataFormatUtilities::EVT_HDR_W1_FLAG_bits = 8 |
◆ EVT_HDR_W1_FLAG_lsb
const int FPGADataFormatUtilities::EVT_HDR_W1_FLAG_lsb = 56 |
◆ EVT_HDR_W1_FLAG_mf
const float FPGADataFormatUtilities::EVT_HDR_W1_FLAG_mf = 1. |
◆ EVT_HDR_W1_L0ID_bits
const int FPGADataFormatUtilities::EVT_HDR_W1_L0ID_bits = 40 |
◆ EVT_HDR_W1_L0ID_lsb
const int FPGADataFormatUtilities::EVT_HDR_W1_L0ID_lsb = 16 |
◆ EVT_HDR_W1_L0ID_mf
const float FPGADataFormatUtilities::EVT_HDR_W1_L0ID_mf = 1. |
◆ EVT_HDR_W1_SPARE_bits
const int FPGADataFormatUtilities::EVT_HDR_W1_SPARE_bits = 4 |
◆ EVT_HDR_W1_SPARE_lsb
const int FPGADataFormatUtilities::EVT_HDR_W1_SPARE_lsb = 0 |
◆ EVT_HDR_W1_SPARE_mf
const float FPGADataFormatUtilities::EVT_HDR_W1_SPARE_mf = 1. |
◆ EVT_HDR_W2_RUNNUMBER_bits
const int FPGADataFormatUtilities::EVT_HDR_W2_RUNNUMBER_bits = 32 |
◆ EVT_HDR_W2_RUNNUMBER_lsb
const int FPGADataFormatUtilities::EVT_HDR_W2_RUNNUMBER_lsb = 32 |
◆ EVT_HDR_W2_RUNNUMBER_mf
const float FPGADataFormatUtilities::EVT_HDR_W2_RUNNUMBER_mf = 1. |
◆ EVT_HDR_W2_TIME_bits
const int FPGADataFormatUtilities::EVT_HDR_W2_TIME_bits = 32 |
◆ EVT_HDR_W2_TIME_lsb
const int FPGADataFormatUtilities::EVT_HDR_W2_TIME_lsb = 0 |
◆ EVT_HDR_W2_TIME_mf
const float FPGADataFormatUtilities::EVT_HDR_W2_TIME_mf = 1. |
◆ EVT_HDR_W3_CRC_bits
const int FPGADataFormatUtilities::EVT_HDR_W3_CRC_bits = 32 |
◆ EVT_HDR_W3_CRC_lsb
const int FPGADataFormatUtilities::EVT_HDR_W3_CRC_lsb = 0 |
◆ EVT_HDR_W3_CRC_mf
const float FPGADataFormatUtilities::EVT_HDR_W3_CRC_mf = 1. |
◆ EVT_HDR_W3_STATUS_bits
const int FPGADataFormatUtilities::EVT_HDR_W3_STATUS_bits = 32 |
◆ EVT_HDR_W3_STATUS_lsb
const int FPGADataFormatUtilities::EVT_HDR_W3_STATUS_lsb = 32 |
◆ EVT_HDR_W3_STATUS_mf
const float FPGADataFormatUtilities::EVT_HDR_W3_STATUS_mf = 1. |
◆ GHITZ_W1_LAST_bits
const int FPGADataFormatUtilities::GHITZ_W1_LAST_bits = 1 |
◆ GHITZ_W1_LAST_lsb
const int FPGADataFormatUtilities::GHITZ_W1_LAST_lsb = 63 |
◆ GHITZ_W1_LAST_mf
const float FPGADataFormatUtilities::GHITZ_W1_LAST_mf = 1. |
◆ GHITZ_W1_LASTOFSLICE_bits
const int FPGADataFormatUtilities::GHITZ_W1_LASTOFSLICE_bits = 1 |
◆ GHITZ_W1_LASTOFSLICE_lsb
const int FPGADataFormatUtilities::GHITZ_W1_LASTOFSLICE_lsb = 2 |
◆ GHITZ_W1_LASTOFSLICE_mf
const float FPGADataFormatUtilities::GHITZ_W1_LASTOFSLICE_mf = 1. |
◆ GHITZ_W1_LYR_bits
const int FPGADataFormatUtilities::GHITZ_W1_LYR_bits = 6 |
◆ GHITZ_W1_LYR_lsb
const int FPGADataFormatUtilities::GHITZ_W1_LYR_lsb = 57 |
◆ GHITZ_W1_LYR_mf
const float FPGADataFormatUtilities::GHITZ_W1_LYR_mf = 1. |
◆ GHITZ_W1_PHI_bits
const int FPGADataFormatUtilities::GHITZ_W1_PHI_bits = 16 |
◆ GHITZ_W1_PHI_lsb
const int FPGADataFormatUtilities::GHITZ_W1_PHI_lsb = 23 |
◆ GHITZ_W1_PHI_mf
const float FPGADataFormatUtilities::GHITZ_W1_PHI_mf = 8192. |
◆ GHITZ_W1_RAD_bits
const int FPGADataFormatUtilities::GHITZ_W1_RAD_bits = 18 |
◆ GHITZ_W1_RAD_lsb
const int FPGADataFormatUtilities::GHITZ_W1_RAD_lsb = 39 |
◆ GHITZ_W1_RAD_mf
const float FPGADataFormatUtilities::GHITZ_W1_RAD_mf = 256. |
◆ GHITZ_W1_SPARE_bits
const int FPGADataFormatUtilities::GHITZ_W1_SPARE_bits = 2 |
◆ GHITZ_W1_SPARE_lsb
const int FPGADataFormatUtilities::GHITZ_W1_SPARE_lsb = 0 |
◆ GHITZ_W1_SPARE_mf
const float FPGADataFormatUtilities::GHITZ_W1_SPARE_mf = 1. |
◆ GHITZ_W1_Z_bits
const int FPGADataFormatUtilities::GHITZ_W1_Z_bits = 20 |
◆ GHITZ_W1_Z_lsb
const int FPGADataFormatUtilities::GHITZ_W1_Z_lsb = 3 |
◆ GHITZ_W1_Z_mf
const float FPGADataFormatUtilities::GHITZ_W1_Z_mf = 128. |
◆ GHITZ_W2_CLUSTER1_bits
const int FPGADataFormatUtilities::GHITZ_W2_CLUSTER1_bits = 19 |
◆ GHITZ_W2_CLUSTER1_lsb
const int FPGADataFormatUtilities::GHITZ_W2_CLUSTER1_lsb = 45 |
◆ GHITZ_W2_CLUSTER1_mf
const float FPGADataFormatUtilities::GHITZ_W2_CLUSTER1_mf = 1. |
◆ GHITZ_W2_CLUSTER2_bits
const int FPGADataFormatUtilities::GHITZ_W2_CLUSTER2_bits = 19 |
◆ GHITZ_W2_CLUSTER2_lsb
const int FPGADataFormatUtilities::GHITZ_W2_CLUSTER2_lsb = 26 |
◆ GHITZ_W2_CLUSTER2_mf
const float FPGADataFormatUtilities::GHITZ_W2_CLUSTER2_mf = 1. |
◆ GHITZ_W2_ROW_bits
const int FPGADataFormatUtilities::GHITZ_W2_ROW_bits = 6 |
◆ GHITZ_W2_ROW_lsb
const int FPGADataFormatUtilities::GHITZ_W2_ROW_lsb = 20 |
◆ GHITZ_W2_ROW_mf
const float FPGADataFormatUtilities::GHITZ_W2_ROW_mf = 1. |
◆ GHITZ_W2_SPARE_bits
const int FPGADataFormatUtilities::GHITZ_W2_SPARE_bits = 20 |
◆ GHITZ_W2_SPARE_lsb
const int FPGADataFormatUtilities::GHITZ_W2_SPARE_lsb = 0 |
◆ GHITZ_W2_SPARE_mf
const float FPGADataFormatUtilities::GHITZ_W2_SPARE_mf = 1. |
◆ GTRACK_HDR_FLAG
const int FPGADataFormatUtilities::GTRACK_HDR_FLAG = 0xee |
◆ GTRACK_HDR_W1_ETA_REGION_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W1_ETA_REGION_bits = 6 |
◆ GTRACK_HDR_W1_ETA_REGION_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W1_ETA_REGION_lsb = 46 |
◆ GTRACK_HDR_W1_ETA_REGION_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W1_ETA_REGION_mf = 1. |
◆ GTRACK_HDR_W1_FLAG_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W1_FLAG_bits = 8 |
◆ GTRACK_HDR_W1_FLAG_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W1_FLAG_lsb = 56 |
◆ GTRACK_HDR_W1_FLAG_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W1_FLAG_mf = 1. |
◆ GTRACK_HDR_W1_HOUGH_X_BIN_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W1_HOUGH_X_BIN_bits = 8 |
◆ GTRACK_HDR_W1_HOUGH_X_BIN_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W1_HOUGH_X_BIN_lsb = 27 |
◆ GTRACK_HDR_W1_HOUGH_X_BIN_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W1_HOUGH_X_BIN_mf = 1. |
◆ GTRACK_HDR_W1_HOUGH_Y_BIN_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W1_HOUGH_Y_BIN_bits = 8 |
◆ GTRACK_HDR_W1_HOUGH_Y_BIN_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W1_HOUGH_Y_BIN_lsb = 19 |
◆ GTRACK_HDR_W1_HOUGH_Y_BIN_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W1_HOUGH_Y_BIN_mf = 1. |
◆ GTRACK_HDR_W1_LAYER_BITMASK_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W1_LAYER_BITMASK_bits = 13 |
◆ GTRACK_HDR_W1_LAYER_BITMASK_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W1_LAYER_BITMASK_lsb = 5 |
◆ GTRACK_HDR_W1_LAYER_BITMASK_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W1_LAYER_BITMASK_mf = 1. |
◆ GTRACK_HDR_W1_PHI_REGION_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W1_PHI_REGION_bits = 6 |
◆ GTRACK_HDR_W1_PHI_REGION_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W1_PHI_REGION_lsb = 40 |
◆ GTRACK_HDR_W1_PHI_REGION_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W1_PHI_REGION_mf = 1. |
◆ GTRACK_HDR_W1_SECOND_STAGE_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W1_SECOND_STAGE_bits = 1 |
◆ GTRACK_HDR_W1_SECOND_STAGE_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W1_SECOND_STAGE_lsb = 18 |
◆ GTRACK_HDR_W1_SECOND_STAGE_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W1_SECOND_STAGE_mf = 1. |
◆ GTRACK_HDR_W1_SLICE_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W1_SLICE_bits = 5 |
◆ GTRACK_HDR_W1_SLICE_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W1_SLICE_lsb = 35 |
◆ GTRACK_HDR_W1_SLICE_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W1_SLICE_mf = 1. |
◆ GTRACK_HDR_W1_SPARE_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W1_SPARE_bits = 5 |
◆ GTRACK_HDR_W1_SPARE_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W1_SPARE_lsb = 0 |
◆ GTRACK_HDR_W1_SPARE_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W1_SPARE_mf = 1. |
◆ GTRACK_HDR_W1_TYPE_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W1_TYPE_bits = 4 |
◆ GTRACK_HDR_W1_TYPE_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W1_TYPE_lsb = 52 |
◆ GTRACK_HDR_W1_TYPE_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W1_TYPE_mf = 1. |
◆ GTRACK_HDR_W2_D0_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W2_D0_bits = 16 |
◆ GTRACK_HDR_W2_D0_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W2_D0_lsb = 32 |
◆ GTRACK_HDR_W2_D0_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W2_D0_mf = 4096. |
◆ GTRACK_HDR_W2_SCORE_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W2_SCORE_bits = 16 |
◆ GTRACK_HDR_W2_SCORE_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W2_SCORE_lsb = 48 |
◆ GTRACK_HDR_W2_SCORE_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W2_SCORE_mf = 2048. |
◆ GTRACK_HDR_W2_SPARE_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W2_SPARE_bits = 16 |
◆ GTRACK_HDR_W2_SPARE_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W2_SPARE_lsb = 0 |
◆ GTRACK_HDR_W2_SPARE_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W2_SPARE_mf = 1. |
◆ GTRACK_HDR_W2_Z0_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W2_Z0_bits = 16 |
◆ GTRACK_HDR_W2_Z0_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W2_Z0_lsb = 16 |
◆ GTRACK_HDR_W2_Z0_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W2_Z0_mf = 32. |
◆ GTRACK_HDR_W3_ETA_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W3_ETA_bits = 16 |
◆ GTRACK_HDR_W3_ETA_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W3_ETA_lsb = 16 |
◆ GTRACK_HDR_W3_ETA_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W3_ETA_mf = 8192. |
◆ GTRACK_HDR_W3_PHI_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W3_PHI_bits = 16 |
◆ GTRACK_HDR_W3_PHI_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W3_PHI_lsb = 32 |
◆ GTRACK_HDR_W3_PHI_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W3_PHI_mf = 8192. |
◆ GTRACK_HDR_W3_QOVERPT_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W3_QOVERPT_bits = 16 |
◆ GTRACK_HDR_W3_QOVERPT_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W3_QOVERPT_lsb = 48 |
◆ GTRACK_HDR_W3_QOVERPT_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W3_QOVERPT_mf = 32768. |
◆ GTRACK_HDR_W3_SPARE_bits
const int FPGADataFormatUtilities::GTRACK_HDR_W3_SPARE_bits = 16 |
◆ GTRACK_HDR_W3_SPARE_lsb
const int FPGADataFormatUtilities::GTRACK_HDR_W3_SPARE_lsb = 0 |
◆ GTRACK_HDR_W3_SPARE_mf
const float FPGADataFormatUtilities::GTRACK_HDR_W3_SPARE_mf = 1. |
◆ M_HDR_FLAG
const int FPGADataFormatUtilities::M_HDR_FLAG = 0x55 |
◆ M_HDR_W1_FLAG_bits
const int FPGADataFormatUtilities::M_HDR_W1_FLAG_bits = 8 |
◆ M_HDR_W1_FLAG_lsb
const int FPGADataFormatUtilities::M_HDR_W1_FLAG_lsb = 56 |
◆ M_HDR_W1_FLAG_mf
const float FPGADataFormatUtilities::M_HDR_W1_FLAG_mf = 1. |
◆ M_HDR_W1_MODHASH_bits
const int FPGADataFormatUtilities::M_HDR_W1_MODHASH_bits = 16 |
◆ M_HDR_W1_MODHASH_lsb
const int FPGADataFormatUtilities::M_HDR_W1_MODHASH_lsb = 8 |
◆ M_HDR_W1_MODHASH_mf
const float FPGADataFormatUtilities::M_HDR_W1_MODHASH_mf = 1. |
◆ M_HDR_W1_MODID_bits
const int FPGADataFormatUtilities::M_HDR_W1_MODID_bits = 32 |
◆ M_HDR_W1_MODID_lsb
const int FPGADataFormatUtilities::M_HDR_W1_MODID_lsb = 24 |
◆ M_HDR_W1_MODID_mf
const float FPGADataFormatUtilities::M_HDR_W1_MODID_mf = 1. |
◆ M_HDR_W1_SPARE_bits
const int FPGADataFormatUtilities::M_HDR_W1_SPARE_bits = 8 |
◆ M_HDR_W1_SPARE_lsb
const int FPGADataFormatUtilities::M_HDR_W1_SPARE_lsb = 0 |
◆ M_HDR_W1_SPARE_mf
const float FPGADataFormatUtilities::M_HDR_W1_SPARE_mf = 1. |
◆ PIXEL_CLUSTER_CENTROID_COL_bits
const int FPGADataFormatUtilities::PIXEL_CLUSTER_CENTROID_COL_bits = 12 |
◆ PIXEL_CLUSTER_CENTROID_COL_lsb
const int FPGADataFormatUtilities::PIXEL_CLUSTER_CENTROID_COL_lsb = 25 |
◆ PIXEL_CLUSTER_CENTROID_COL_mf
const float FPGADataFormatUtilities::PIXEL_CLUSTER_CENTROID_COL_mf = 16. |
◆ PIXEL_CLUSTER_CENTROID_ROW_bits
const int FPGADataFormatUtilities::PIXEL_CLUSTER_CENTROID_ROW_bits = 12 |
◆ PIXEL_CLUSTER_CENTROID_ROW_lsb
const int FPGADataFormatUtilities::PIXEL_CLUSTER_CENTROID_ROW_lsb = 13 |
◆ PIXEL_CLUSTER_CENTROID_ROW_mf
const float FPGADataFormatUtilities::PIXEL_CLUSTER_CENTROID_ROW_mf = 16. |
◆ PIXEL_CLUSTER_COL_bits
const int FPGADataFormatUtilities::PIXEL_CLUSTER_COL_bits = 13 |
◆ PIXEL_CLUSTER_COL_lsb
const int FPGADataFormatUtilities::PIXEL_CLUSTER_COL_lsb = 50 |
◆ PIXEL_CLUSTER_COL_mf
const float FPGADataFormatUtilities::PIXEL_CLUSTER_COL_mf = 1. |
◆ PIXEL_CLUSTER_LAST_bits
const int FPGADataFormatUtilities::PIXEL_CLUSTER_LAST_bits = 1 |
◆ PIXEL_CLUSTER_LAST_lsb
const int FPGADataFormatUtilities::PIXEL_CLUSTER_LAST_lsb = 63 |
◆ PIXEL_CLUSTER_LAST_mf
const float FPGADataFormatUtilities::PIXEL_CLUSTER_LAST_mf = 1. |
◆ PIXEL_CLUSTER_ROW_bits
const int FPGADataFormatUtilities::PIXEL_CLUSTER_ROW_bits = 13 |
◆ PIXEL_CLUSTER_ROW_lsb
const int FPGADataFormatUtilities::PIXEL_CLUSTER_ROW_lsb = 37 |
◆ PIXEL_CLUSTER_ROW_mf
const float FPGADataFormatUtilities::PIXEL_CLUSTER_ROW_mf = 1. |
◆ PIXEL_CLUSTER_SPARE_bits
const int FPGADataFormatUtilities::PIXEL_CLUSTER_SPARE_bits = 13 |
◆ PIXEL_CLUSTER_SPARE_lsb
const int FPGADataFormatUtilities::PIXEL_CLUSTER_SPARE_lsb = 0 |
◆ PIXEL_CLUSTER_SPARE_mf
const float FPGADataFormatUtilities::PIXEL_CLUSTER_SPARE_mf = 1. |
◆ PIXEL_EF_RDO_COL_bits
const int FPGADataFormatUtilities::PIXEL_EF_RDO_COL_bits = 10 |
◆ PIXEL_EF_RDO_COL_lsb
const int FPGADataFormatUtilities::PIXEL_EF_RDO_COL_lsb = 43 |
◆ PIXEL_EF_RDO_COL_mf
const float FPGADataFormatUtilities::PIXEL_EF_RDO_COL_mf = 1. |
◆ PIXEL_EF_RDO_LAST_bits
const int FPGADataFormatUtilities::PIXEL_EF_RDO_LAST_bits = 1 |
◆ PIXEL_EF_RDO_LAST_lsb
const int FPGADataFormatUtilities::PIXEL_EF_RDO_LAST_lsb = 63 |
◆ PIXEL_EF_RDO_LAST_mf
const float FPGADataFormatUtilities::PIXEL_EF_RDO_LAST_mf = 1. |
◆ PIXEL_EF_RDO_LVL1_bits
const int FPGADataFormatUtilities::PIXEL_EF_RDO_LVL1_bits = 1 |
◆ PIXEL_EF_RDO_LVL1_lsb
const int FPGADataFormatUtilities::PIXEL_EF_RDO_LVL1_lsb = 38 |
◆ PIXEL_EF_RDO_LVL1_mf
const float FPGADataFormatUtilities::PIXEL_EF_RDO_LVL1_mf = 1. |
◆ PIXEL_EF_RDO_ROW_bits
const int FPGADataFormatUtilities::PIXEL_EF_RDO_ROW_bits = 10 |
◆ PIXEL_EF_RDO_ROW_lsb
const int FPGADataFormatUtilities::PIXEL_EF_RDO_ROW_lsb = 53 |
◆ PIXEL_EF_RDO_ROW_mf
const float FPGADataFormatUtilities::PIXEL_EF_RDO_ROW_mf = 1. |
◆ PIXEL_EF_RDO_SPARE_bits
const int FPGADataFormatUtilities::PIXEL_EF_RDO_SPARE_bits = 38 |
◆ PIXEL_EF_RDO_SPARE_lsb
const int FPGADataFormatUtilities::PIXEL_EF_RDO_SPARE_lsb = 0 |
◆ PIXEL_EF_RDO_SPARE_mf
const float FPGADataFormatUtilities::PIXEL_EF_RDO_SPARE_mf = 1. |
◆ PIXEL_EF_RDO_TOT_bits
const int FPGADataFormatUtilities::PIXEL_EF_RDO_TOT_bits = 4 |
◆ PIXEL_EF_RDO_TOT_lsb
const int FPGADataFormatUtilities::PIXEL_EF_RDO_TOT_lsb = 39 |
◆ PIXEL_EF_RDO_TOT_mf
const float FPGADataFormatUtilities::PIXEL_EF_RDO_TOT_mf = 1. |
◆ RD_HDR_FLAG
const int FPGADataFormatUtilities::RD_HDR_FLAG = 0xbb |
◆ RD_HDR_W1_ETA_REGION_bits
const int FPGADataFormatUtilities::RD_HDR_W1_ETA_REGION_bits = 6 |
◆ RD_HDR_W1_ETA_REGION_lsb
const int FPGADataFormatUtilities::RD_HDR_W1_ETA_REGION_lsb = 46 |
◆ RD_HDR_W1_ETA_REGION_mf
const float FPGADataFormatUtilities::RD_HDR_W1_ETA_REGION_mf = 1. |
◆ RD_HDR_W1_FLAG_bits
const int FPGADataFormatUtilities::RD_HDR_W1_FLAG_bits = 8 |
◆ RD_HDR_W1_FLAG_lsb
const int FPGADataFormatUtilities::RD_HDR_W1_FLAG_lsb = 56 |
◆ RD_HDR_W1_FLAG_mf
const float FPGADataFormatUtilities::RD_HDR_W1_FLAG_mf = 1. |
◆ RD_HDR_W1_HOUGH_X_BIN_bits
const int FPGADataFormatUtilities::RD_HDR_W1_HOUGH_X_BIN_bits = 8 |
◆ RD_HDR_W1_HOUGH_X_BIN_lsb
const int FPGADataFormatUtilities::RD_HDR_W1_HOUGH_X_BIN_lsb = 27 |
◆ RD_HDR_W1_HOUGH_X_BIN_mf
const float FPGADataFormatUtilities::RD_HDR_W1_HOUGH_X_BIN_mf = 1. |
◆ RD_HDR_W1_HOUGH_Y_BIN_bits
const int FPGADataFormatUtilities::RD_HDR_W1_HOUGH_Y_BIN_bits = 8 |
◆ RD_HDR_W1_HOUGH_Y_BIN_lsb
const int FPGADataFormatUtilities::RD_HDR_W1_HOUGH_Y_BIN_lsb = 19 |
◆ RD_HDR_W1_HOUGH_Y_BIN_mf
const float FPGADataFormatUtilities::RD_HDR_W1_HOUGH_Y_BIN_mf = 1. |
◆ RD_HDR_W1_LAYER_BITMASK_bits
const int FPGADataFormatUtilities::RD_HDR_W1_LAYER_BITMASK_bits = 13 |
◆ RD_HDR_W1_LAYER_BITMASK_lsb
const int FPGADataFormatUtilities::RD_HDR_W1_LAYER_BITMASK_lsb = 5 |
◆ RD_HDR_W1_LAYER_BITMASK_mf
const float FPGADataFormatUtilities::RD_HDR_W1_LAYER_BITMASK_mf = 1. |
◆ RD_HDR_W1_PHI_REGION_bits
const int FPGADataFormatUtilities::RD_HDR_W1_PHI_REGION_bits = 6 |
◆ RD_HDR_W1_PHI_REGION_lsb
const int FPGADataFormatUtilities::RD_HDR_W1_PHI_REGION_lsb = 40 |
◆ RD_HDR_W1_PHI_REGION_mf
const float FPGADataFormatUtilities::RD_HDR_W1_PHI_REGION_mf = 1. |
◆ RD_HDR_W1_SECOND_STAGE_bits
const int FPGADataFormatUtilities::RD_HDR_W1_SECOND_STAGE_bits = 1 |
◆ RD_HDR_W1_SECOND_STAGE_lsb
const int FPGADataFormatUtilities::RD_HDR_W1_SECOND_STAGE_lsb = 18 |
◆ RD_HDR_W1_SECOND_STAGE_mf
const float FPGADataFormatUtilities::RD_HDR_W1_SECOND_STAGE_mf = 1. |
◆ RD_HDR_W1_SLICE_bits
const int FPGADataFormatUtilities::RD_HDR_W1_SLICE_bits = 5 |
◆ RD_HDR_W1_SLICE_lsb
const int FPGADataFormatUtilities::RD_HDR_W1_SLICE_lsb = 35 |
◆ RD_HDR_W1_SLICE_mf
const float FPGADataFormatUtilities::RD_HDR_W1_SLICE_mf = 1. |
◆ RD_HDR_W1_SPARE_bits
const int FPGADataFormatUtilities::RD_HDR_W1_SPARE_bits = 5 |
◆ RD_HDR_W1_SPARE_lsb
const int FPGADataFormatUtilities::RD_HDR_W1_SPARE_lsb = 0 |
◆ RD_HDR_W1_SPARE_mf
const float FPGADataFormatUtilities::RD_HDR_W1_SPARE_mf = 1. |
◆ RD_HDR_W1_TYPE_bits
const int FPGADataFormatUtilities::RD_HDR_W1_TYPE_bits = 4 |
◆ RD_HDR_W1_TYPE_lsb
const int FPGADataFormatUtilities::RD_HDR_W1_TYPE_lsb = 52 |
◆ RD_HDR_W1_TYPE_mf
const float FPGADataFormatUtilities::RD_HDR_W1_TYPE_mf = 1. |
◆ RD_HDR_W2_GLOBAL_ETA_bits
const int FPGADataFormatUtilities::RD_HDR_W2_GLOBAL_ETA_bits = 16 |
◆ RD_HDR_W2_GLOBAL_ETA_lsb
const int FPGADataFormatUtilities::RD_HDR_W2_GLOBAL_ETA_lsb = 32 |
◆ RD_HDR_W2_GLOBAL_ETA_mf
const float FPGADataFormatUtilities::RD_HDR_W2_GLOBAL_ETA_mf = 1. |
◆ RD_HDR_W2_GLOBAL_PHI_bits
const int FPGADataFormatUtilities::RD_HDR_W2_GLOBAL_PHI_bits = 16 |
◆ RD_HDR_W2_GLOBAL_PHI_lsb
const int FPGADataFormatUtilities::RD_HDR_W2_GLOBAL_PHI_lsb = 48 |
◆ RD_HDR_W2_GLOBAL_PHI_mf
const float FPGADataFormatUtilities::RD_HDR_W2_GLOBAL_PHI_mf = 1. |
◆ RD_HDR_W2_SPARE_bits
const int FPGADataFormatUtilities::RD_HDR_W2_SPARE_bits = 32 |
◆ RD_HDR_W2_SPARE_lsb
const int FPGADataFormatUtilities::RD_HDR_W2_SPARE_lsb = 0 |
◆ RD_HDR_W2_SPARE_mf
const float FPGADataFormatUtilities::RD_HDR_W2_SPARE_mf = 1. |
◆ SLICE_HDR_FLAG
const int FPGADataFormatUtilities::SLICE_HDR_FLAG = 0x88 |
◆ SLICE_HDR_W1_ETA_REGION_bits
const int FPGADataFormatUtilities::SLICE_HDR_W1_ETA_REGION_bits = 6 |
◆ SLICE_HDR_W1_ETA_REGION_lsb
const int FPGADataFormatUtilities::SLICE_HDR_W1_ETA_REGION_lsb = 39 |
◆ SLICE_HDR_W1_ETA_REGION_mf
const float FPGADataFormatUtilities::SLICE_HDR_W1_ETA_REGION_mf = 1. |
◆ SLICE_HDR_W1_FLAG_bits
const int FPGADataFormatUtilities::SLICE_HDR_W1_FLAG_bits = 8 |
◆ SLICE_HDR_W1_FLAG_lsb
const int FPGADataFormatUtilities::SLICE_HDR_W1_FLAG_lsb = 56 |
◆ SLICE_HDR_W1_FLAG_mf
const float FPGADataFormatUtilities::SLICE_HDR_W1_FLAG_mf = 1. |
◆ SLICE_HDR_W1_PHI_REGION_bits
const int FPGADataFormatUtilities::SLICE_HDR_W1_PHI_REGION_bits = 6 |
◆ SLICE_HDR_W1_PHI_REGION_lsb
const int FPGADataFormatUtilities::SLICE_HDR_W1_PHI_REGION_lsb = 33 |
◆ SLICE_HDR_W1_PHI_REGION_mf
const float FPGADataFormatUtilities::SLICE_HDR_W1_PHI_REGION_mf = 1. |
◆ SLICE_HDR_W1_SLICEID_bits
const int FPGADataFormatUtilities::SLICE_HDR_W1_SLICEID_bits = 11 |
◆ SLICE_HDR_W1_SLICEID_lsb
const int FPGADataFormatUtilities::SLICE_HDR_W1_SLICEID_lsb = 45 |
◆ SLICE_HDR_W1_SLICEID_mf
const float FPGADataFormatUtilities::SLICE_HDR_W1_SLICEID_mf = 1. |
◆ SLICE_HDR_W1_SPARE_bits
const int FPGADataFormatUtilities::SLICE_HDR_W1_SPARE_bits = 33 |
◆ SLICE_HDR_W1_SPARE_lsb
const int FPGADataFormatUtilities::SLICE_HDR_W1_SPARE_lsb = 0 |
◆ SLICE_HDR_W1_SPARE_mf
const float FPGADataFormatUtilities::SLICE_HDR_W1_SPARE_mf = 1. |
◆ STRIP_CLUSTER_LAST_bits
const int FPGADataFormatUtilities::STRIP_CLUSTER_LAST_bits = 1 |
◆ STRIP_CLUSTER_LAST_lsb
const int FPGADataFormatUtilities::STRIP_CLUSTER_LAST_lsb = 31 |
◆ STRIP_CLUSTER_LAST_mf
const float FPGADataFormatUtilities::STRIP_CLUSTER_LAST_mf = 1. |
◆ STRIP_CLUSTER_NSTRIPS_bits
const int FPGADataFormatUtilities::STRIP_CLUSTER_NSTRIPS_bits = 8 |
◆ STRIP_CLUSTER_NSTRIPS_lsb
const int FPGADataFormatUtilities::STRIP_CLUSTER_NSTRIPS_lsb = 22 |
◆ STRIP_CLUSTER_NSTRIPS_mf
const float FPGADataFormatUtilities::STRIP_CLUSTER_NSTRIPS_mf = 1. |
◆ STRIP_CLUSTER_ROW_bits
const int FPGADataFormatUtilities::STRIP_CLUSTER_ROW_bits = 1 |
◆ STRIP_CLUSTER_ROW_lsb
const int FPGADataFormatUtilities::STRIP_CLUSTER_ROW_lsb = 30 |
◆ STRIP_CLUSTER_ROW_mf
const float FPGADataFormatUtilities::STRIP_CLUSTER_ROW_mf = 1. |
◆ STRIP_CLUSTER_SPARE_bits
const int FPGADataFormatUtilities::STRIP_CLUSTER_SPARE_bits = 10 |
◆ STRIP_CLUSTER_SPARE_lsb
const int FPGADataFormatUtilities::STRIP_CLUSTER_SPARE_lsb = 0 |
◆ STRIP_CLUSTER_SPARE_mf
const float FPGADataFormatUtilities::STRIP_CLUSTER_SPARE_mf = 1. |
◆ STRIP_CLUSTER_STRIP_INDEX_bits
const int FPGADataFormatUtilities::STRIP_CLUSTER_STRIP_INDEX_bits = 12 |
◆ STRIP_CLUSTER_STRIP_INDEX_lsb
const int FPGADataFormatUtilities::STRIP_CLUSTER_STRIP_INDEX_lsb = 10 |
◆ STRIP_CLUSTER_STRIP_INDEX_mf
const float FPGADataFormatUtilities::STRIP_CLUSTER_STRIP_INDEX_mf = 1. |
◆ STRIP_EF_RDO_CHIPID_bits
const int FPGADataFormatUtilities::STRIP_EF_RDO_CHIPID_bits = 4 |
◆ STRIP_EF_RDO_CHIPID_lsb
const int FPGADataFormatUtilities::STRIP_EF_RDO_CHIPID_lsb = 27 |
◆ STRIP_EF_RDO_CHIPID_mf
const float FPGADataFormatUtilities::STRIP_EF_RDO_CHIPID_mf = 1. |
◆ STRIP_EF_RDO_CLUSTER_MAP_bits
const int FPGADataFormatUtilities::STRIP_EF_RDO_CLUSTER_MAP_bits = 3 |
◆ STRIP_EF_RDO_CLUSTER_MAP_lsb
const int FPGADataFormatUtilities::STRIP_EF_RDO_CLUSTER_MAP_lsb = 16 |
◆ STRIP_EF_RDO_CLUSTER_MAP_mf
const float FPGADataFormatUtilities::STRIP_EF_RDO_CLUSTER_MAP_mf = 1. |
◆ STRIP_EF_RDO_LAST_bits
const int FPGADataFormatUtilities::STRIP_EF_RDO_LAST_bits = 1 |
◆ STRIP_EF_RDO_LAST_lsb
const int FPGADataFormatUtilities::STRIP_EF_RDO_LAST_lsb = 31 |
◆ STRIP_EF_RDO_LAST_mf
const float FPGADataFormatUtilities::STRIP_EF_RDO_LAST_mf = 1. |
◆ STRIP_EF_RDO_SPARE_bits
const int FPGADataFormatUtilities::STRIP_EF_RDO_SPARE_bits = 16 |
◆ STRIP_EF_RDO_SPARE_lsb
const int FPGADataFormatUtilities::STRIP_EF_RDO_SPARE_lsb = 0 |
◆ STRIP_EF_RDO_SPARE_mf
const float FPGADataFormatUtilities::STRIP_EF_RDO_SPARE_mf = 1. |
◆ STRIP_EF_RDO_STRIP_NUM_bits
const int FPGADataFormatUtilities::STRIP_EF_RDO_STRIP_NUM_bits = 8 |
◆ STRIP_EF_RDO_STRIP_NUM_lsb
const int FPGADataFormatUtilities::STRIP_EF_RDO_STRIP_NUM_lsb = 19 |
◆ STRIP_EF_RDO_STRIP_NUM_mf
const float FPGADataFormatUtilities::STRIP_EF_RDO_STRIP_NUM_mf = 1. |
Scalar phi() const
phi method
Scalar eta() const
pseudorapidity method
setEventNumber setTimeStamp bcid
def time(flags, cells_name, *args, **kw)