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gFexInputByteStreamTool.cxx
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1/*
2 Copyright (C) 2002-2026 CERN for the benefit of the ATLAS collaboration
3*/
4
5//***************************************************************************
6// gFexInputByteStreamTool - This tool decodes Run3 gFEX input data!
7// -------------------
8// begin : 10 08 2022
9// email : cecilia.tosciri@cern.ch
10// ***************************************************************************/
11
12#include "gFexInputByteStreamTool.h"
13#include "eformat/SourceIdentifier.h"
14#include "eformat/Status.h"
15
16#include <span>
17#include <fstream>
18
19using ROBF = OFFLINE_FRAGMENTS_NAMESPACE::ROBFragment;
20using WROBF = OFFLINE_FRAGMENTS_NAMESPACE_WRITE::ROBFragment;
21
22namespace gPos = LVL1::gFEXPos;
23
24
25gFexInputByteStreamTool::gFexInputByteStreamTool(const std::string& type,
26 const std::string& name,
27 const IInterface* parent)
28 : base_class(type, name, parent) {}
29
30StatusCode gFexInputByteStreamTool::initialize() {
31
32 ATH_MSG_DEBUG(" ROB IDs: " << MSG::hex << m_robIds.value() << MSG::dec);
33
34 // Conversion mode for gTowers
35 ConversionMode gTowersmode = getConversionMode(m_gTowersReadKey, m_gTowersWriteKey, msg());
36 ATH_CHECK(gTowersmode!=ConversionMode::Undefined);
37 ATH_CHECK(ReadFibersfromFile(PathResolver::find_calib_file(m_FiberMapping)));
38 ATH_CHECK(m_gTowersWriteKey.initialize(gTowersmode==ConversionMode::Decoding));
39 ATH_CHECK(m_gTowers50WriteKey.initialize(SG::AllowEmpty));
40 ATH_CHECK(m_gTowers200WriteKey.initialize(SG::AllowEmpty));
41 ATH_CHECK(m_gTowersReadKey.initialize(gTowersmode==ConversionMode::Encoding));
42 ATH_MSG_DEBUG((gTowersmode==ConversionMode::Encoding ? "Encoding" : "Decoding") << " gTowers ");
43
44 // Initialize monitoring tool if not empty
45 if (!m_monTool.empty()) {
46 ATH_CHECK(m_monTool.retrieve());
47 ATH_MSG_INFO("Logging errors to " << m_monTool.name() << " monitoring tool");
48 m_UseMonitoring = true;
49 }
50
51 return StatusCode::SUCCESS;
52}
53
54// BS->xAOD conversion
55StatusCode gFexInputByteStreamTool::convertFromBS(const std::vector<const ROBF*>& vrobf, const EventContext& ctx) const {
56
57 //WriteHandle for gFEX EDMs
58
59 //---gTower EDM
60 xAOD::gFexTowerContainer* gTowers200ContainerPtr = nullptr;
61 SG::WriteHandle<xAOD::gFexTowerContainer> gTowersContainer = (!m_gTowers200WriteKey.empty()) ? SG::WriteHandle<xAOD::gFexTowerContainer>(m_gTowers200WriteKey, ctx) : SG::WriteHandle<xAOD::gFexTowerContainer>();
62 if(!m_gTowers200WriteKey.empty()) {
63 ATH_CHECK(gTowersContainer.record(std::make_unique<xAOD::gFexTowerContainer>(),
64 std::make_unique<xAOD::gFexTowerAuxContainer>()));
65 ATH_MSG_DEBUG(
66 "Recorded gFexTowerContainer (200 MeV resolution, default) with key " << m_gTowers200WriteKey.key());
67 gTowers200ContainerPtr = &*gTowersContainer;
68 }
69
70 xAOD::gFexTowerContainer* gTowers50ContainerPtr = nullptr;
71 SG::WriteHandle<xAOD::gFexTowerContainer> gTowers50Container = (!m_gTowers50WriteKey.empty()) ? SG::WriteHandle<xAOD::gFexTowerContainer>(m_gTowers50WriteKey, ctx) : SG::WriteHandle<xAOD::gFexTowerContainer>();
72 if(!m_gTowers50WriteKey.empty()) {
73 ATH_CHECK(gTowers50Container.record(std::make_unique<xAOD::gFexTowerContainer>(),
74 std::make_unique<xAOD::gFexTowerAuxContainer>()));
75 ATH_MSG_DEBUG("Recorded gFexTower50Container (50 MeV resolution) with key " << gTowers50Container.key());
76 gTowers50ContainerPtr = &*gTowers50Container;
77 }
78
79 SG::WriteHandle<xAOD::gFexTowerContainer> gFexDataTowersContainer(m_gTowersWriteKey, ctx);
80 ATH_CHECK(gFexDataTowersContainer.record(std::make_unique<xAOD::gFexTowerContainer>(), std::make_unique<xAOD::gFexTowerAuxContainer>()));
81 ATH_MSG_DEBUG("Recorded main gFexDataTowerContainer with key " << gFexDataTowersContainer.key());
82
83 // Iterate over ROBFragments to decode
84 for (const ROBF* rob : vrobf) {
85 // Iterate over ROD words and decode
86
87
88 ATH_MSG_DEBUG("Starting to decode " << rob->rod_ndata() << " ROD words from ROB 0x" << std::hex << rob->rob_source_id());
89 //There is no data to decode.. not even the ROD trailers
90 if(rob->rod_ndata() <= 0){
91 continue;
92 }
93
94 const auto dataArray = std::span{rob->rod_data(), rob->rod_ndata()};
95
96 // Starting to loop over the gFEX words
97
98 unsigned int n_words = rob->rod_ndata();
99
100 int fpga = -99; //FPGA number 0,1,2 -> A,B,C
101 int fpgaPosition = -99; //Position of the FPGA header in the dataframe
102
103 // Preparing input fiber arrays to be used as input to the routine
104 // for converting fiber information into towers
105 gfiber Afiber = {{{0}}};
106 gfiber Bfiber = {{{0}}};
107 gfiber Cfiber = {{{0}}};
108
109 gfiber AMapped = {{{0}}};
110 gfiber BMapped = {{{0}}};
111 gfiber CMapped = {{{0}}};
112
113 int rows = Afiber.size();
114 int cols = Afiber[0].size();
115
116 // Loop over the 32-bit words to extract words relative to each FPGA
117 // Put 100x7 words available for each FPGA in corresponding arrays
118 for(unsigned int iWord=0; iWord<n_words; iWord++) {
119 if (dataArray[iWord] == gPos::FPGA_A_INPUT_HEADER){
120 fpga = 0;
121 fpgaPosition = iWord;
122 }
123 else if (dataArray[iWord] == gPos::FPGA_B_INPUT_HEADER) {
124 fpga = 1;
125 fpgaPosition = iWord;
126 }
127 else if (dataArray[iWord] == gPos::FPGA_C_INPUT_HEADER) {
128 fpga = 2;
129 fpgaPosition = iWord;
130 }
131 else continue;
132
133
134 if (fpga == 0){
135 for (int irow = 0; irow < rows; irow++){
136 for (int icol = 0; icol < cols; icol++){
137 Afiber[irow][icol] = dataArray[fpgaPosition + (7*irow) + 1 + icol];
138 }
139 }
140 }
141
142 if (fpga == 1){
143 for (int irow = 0; irow < rows; irow++){
144 for (int icol = 0; icol < cols; icol++){
145 Bfiber[irow][icol] = dataArray[fpgaPosition + (7*irow) + 1 + icol];
146 }
147 }
148 }
149
150 if (fpga == 2){
151 for (int irow = 0; irow < rows; irow++){
152 for (int icol = 0; icol < cols; icol++){
153 Cfiber[irow][icol] = dataArray[fpgaPosition + (7*irow) + 1 + icol];
154 }
155 }
156 }
157 }
158
159 // For each FPGA we resemble the fibers->gTowers used in hardware
160 // Atwr, Btwr, Ctwr will contain towers for each FPGA
161 gtFPGA Atwr = {{{0}}};
162 gtFPGA Btwr = {{{0}}};
163 gtFPGA Ctwr = {{{0}}};
164
165 gtFPGA AtwrF = {{{0}}};
166 gtFPGA BtwrF = {{{0}}};
167 gtFPGA CtwrF = {{{0}}};
168
169 gtFPGA Asatur = {{{0}}};
170 gtFPGA Bsatur = {{{0}}};
171 gtFPGA Csatur = {{{0}}};
172
173 a_gtrx_map(Afiber, AMapped);
174
175 int fpgaA = 0;
176 int fBcidA = -1;
177 int do_lconv = 1;
178
179 std::array<int, (gPos::AB_FIBERS*gPos::MAX_E_FIELDS)> FiberTowerA = {};
180 std::array<int, (gPos::AB_FIBERS*gPos::MAX_E_FIELDS)> FiberTowerB = {};
181 std::array<int, (gPos::AB_FIBERS*gPos::MAX_E_FIELDS)> FiberTowerC = {}; // slightly larger than needed
182
183 std::array<int, (gPos::AB_FIBERS*gPos::MAX_E_FIELDS)> FiberTowerAsatur = {0};
184 std::array<int, (gPos::AB_FIBERS*gPos::MAX_E_FIELDS)> FiberTowerBsatur = {0};
185 std::array<int, (gPos::AB_FIBERS*gPos::MAX_E_FIELDS)> FiberTowerCsatur = {0};
186
187 gtReconstructABC(fpgaA,
188 AMapped, // input fibers AB_FIBER = 80 > C fibers
189 gPos::AB_FIBERS,
190 AtwrF,
191 Atwr,
192 &fBcidA,
193 do_lconv, // flag to indicate multilinear conversion
194 gPos::AMPD_NFI,
195 gPos::ACALO_TYPE,
196 gPos::AMPD_GTRN_ARR,
197 gPos::AMPD_DSTRT_ARR,
198 gPos::AMPD_DTYP_ARR,
199 gPos::AMSK,
200 Asatur,
201 FiberTowerA,
202 FiberTowerAsatur);
203
204
205
206 b_gtrx_map(Bfiber, BMapped);
207
208 int fpgaB = 1;
209 int fBcidB = -1;
210
211 gtReconstructABC( fpgaB,
212 BMapped, gPos::AB_FIBERS,
213 BtwrF,
214 Btwr,
215 &fBcidB,
216 do_lconv,
217 gPos::BMPD_NFI,
218 gPos::BCALO_TYPE,
219 gPos::BMPD_GTRN_ARR,
220 gPos::BMPD_DSTRT_ARR,
221 gPos::BMPD_DTYP_ARR,
222 gPos::BMSK,
223 Bsatur,
224 FiberTowerB,
225 FiberTowerBsatur);
226
227
228 c_gtrx_map(Cfiber, CMapped);
229
230 int fpgaC = 2;
231 int fBcidC = -1;
232
233 gtReconstructABC( fpgaC,
234 CMapped, gPos::C_FIBERS,
235 CtwrF,
236 Ctwr,
237 &fBcidC,
238 do_lconv,
239 gPos::CMPD_NFI,
240 gPos::CCALO_TYPE,
241 gPos::CMPD_GTRN_ARR,
242 gPos::CMPD_DSTRT_ARR,
243 gPos::CMPD_DTYP_ARR,
244 gPos::CMSK,
245 Csatur,
246 FiberTowerC,
247 FiberTowerCsatur);
248
249
250 // Fill the gTower EDM with the corresponding towers
251 int iEta = 0;
252 int iPhi = 0;
253 float Eta = 0;
254 float Phi = 0;
255 int Et = 0;
256 int EtF = 0;
257 int Fpga = 0;
258 char IsSaturated = 0;
259 int towerID = 0;
260
261 // Assign ID based on FPGA (FPGA-A 0->0; FPGA-B 1->10000, FPGA-C 2->20000) and gTower number assigned as per firmware convention
262
263
264 int twr_rows = Atwr.size();
265 int twr_cols = Atwr[0].size();
266
267 Fpga = 0;
268
269 // Save towers from FPGA A in gTower EDM
270 for (int irow = 0; irow < twr_rows; irow++){
271 for (int icol = 0; icol < twr_cols; icol++){
272 iEta = icol + 8;
273 iPhi = irow;
274 Et = Atwr[irow][icol];
275 EtF = AtwrF[irow][icol];
276 IsSaturated = Asatur[irow][icol];
277
278 getEtaPhi(Eta, Phi, iEta, iPhi, towerID);
279 if(gTowers200ContainerPtr) {
280 gTowers200ContainerPtr->push_back( std::make_unique<xAOD::gFexTower>() );
281 gTowers200ContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
282 }
283 if(gTowers50ContainerPtr) {
284 gTowers50ContainerPtr->push_back(std::make_unique<xAOD::gFexTower>());
285 gTowers50ContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, EtF, Fpga, IsSaturated, towerID);
286 }
287 towerID += 1;
288
289 }
290 }
291
292 // Save towers from FPGA B in gTower EDM
293 Fpga = 1;
294 towerID = 10000;
295 // Save towers from FPGA B in gTower EDM
296 for (int irow = 0; irow < twr_rows; irow++){
297 for (int icol = 0; icol < twr_cols; icol++){
298 iEta = icol + 20;
299 iPhi = irow;
300 Et = Btwr[irow][icol];
301 EtF = BtwrF[irow][icol];
302 IsSaturated = Bsatur[irow][icol];
303 getEtaPhi(Eta, Phi, iEta, iPhi, towerID);
304 if(gTowers200ContainerPtr) {
305 gTowers200ContainerPtr->push_back( std::make_unique<xAOD::gFexTower>() );
306 gTowers200ContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
307 }
308 if(gTowers50ContainerPtr) {
309 gTowers50ContainerPtr->push_back(std::make_unique<xAOD::gFexTower>());
310 gTowers50ContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, EtF, Fpga, IsSaturated, towerID);
311 }
312 towerID += 1;
313
314 }
315 }
316
317 // Save towers from FPGA C in gTower EDM
318 Fpga = 2;
319 towerID = 20000;
320 for (int irow = 0; irow < twr_rows; irow++){
321 for (int icol = 0; icol < twr_cols/2; icol++){
322 iEta = icol + 2;
323 iPhi = irow;
324 Et = Ctwr[irow][icol];
325 EtF = CtwrF[irow][icol];
326 IsSaturated = Csatur[irow][icol];
327 getEtaPhi(Eta, Phi, iEta, iPhi, towerID);
328 if(gTowers200ContainerPtr) {
329 gTowers200ContainerPtr->push_back( std::make_unique<xAOD::gFexTower>() );
330 gTowers200ContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
331 }
332 if(gTowers50ContainerPtr) {
333 gTowers50ContainerPtr->push_back(std::make_unique<xAOD::gFexTower>());
334 gTowers50ContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, EtF, Fpga, IsSaturated, towerID);
335 }
336 towerID += 1;
337 }
338 for (int icol = twr_cols/2; icol < twr_cols; icol++){
339 iEta = icol + 26;
340 iPhi = irow;
341 Et = Ctwr[irow][icol];
342 EtF = CtwrF[irow][icol];
343 IsSaturated = Csatur[irow][icol];
344 getEtaPhi(Eta, Phi, iEta, iPhi, towerID);
345 if(gTowers200ContainerPtr) {
346 gTowers200ContainerPtr->push_back( std::make_unique<xAOD::gFexTower>() );
347 gTowers200ContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
348 }
349 if(gTowers50ContainerPtr) {
350 gTowers50ContainerPtr->push_back(std::make_unique<xAOD::gFexTower>());
351 gTowers50ContainerPtr->back()->initialize(iEta, iPhi, Eta, Phi, EtF, Fpga, IsSaturated, towerID);
352 }
353 towerID += 1;
354
355 }
356 }
357 // Save the Fiber towers (DataTowers)
358 unsigned int n_fiber_twrs = FiberTowerA.size();
359 Fpga = 0;
360 towerID = 0;
361 for (unsigned int i = 0; i < n_fiber_twrs; i++){
362 iEta = i; // iEta and iPhi not so much meaning for fiber towers
363 iPhi = i;
364 Eta = m_Firm2Tower_map.at(towerID)[1]; // eta from the mapping
365 Phi = m_Firm2Tower_map.at(towerID)[2]; // phi from the mapping
366 Et = FiberTowerA[i];
367 IsSaturated = FiberTowerAsatur[i];
368 gFexDataTowersContainer->push_back( std::make_unique<xAOD::gFexTower>() );
369 gFexDataTowersContainer->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
370 towerID += 1;
371 }
372 Fpga = 1;
373 towerID = 10000;
374 for (unsigned int i = 0; i < n_fiber_twrs; i++){
375 iEta = i;
376 iPhi = i;
377 Eta = m_Firm2Tower_map.at(towerID)[1];
378 Phi = m_Firm2Tower_map.at(towerID)[2];
379 Et = FiberTowerB[i];
380 IsSaturated = FiberTowerBsatur[i];
381 gFexDataTowersContainer->push_back( std::make_unique<xAOD::gFexTower>() );
382 gFexDataTowersContainer->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
383 towerID += 1;
384 }
385 // FPGA C has fewer fibers, fill only those
386 unsigned int n_fiber_twrsC = gPos::C_FIBERS*gPos::MAX_E_FIELDS;
387 Fpga = 2;
388 towerID = 20000;
389 for (unsigned int i = 0; i < n_fiber_twrsC; i++){
390 iEta = i;
391 iPhi = i;
392 Eta = m_Firm2Tower_map.at(towerID)[1];
393 Phi = m_Firm2Tower_map.at(towerID)[2];
394 Et = FiberTowerC[i];
395 IsSaturated = FiberTowerCsatur[i];
396 gFexDataTowersContainer->push_back( std::make_unique<xAOD::gFexTower>() );
397 gFexDataTowersContainer->back()->initialize(iEta, iPhi, Eta, Phi, Et, Fpga, IsSaturated, towerID);
398 towerID += 1;
399 }
400 }
401 return StatusCode::SUCCESS;
402}
403
404
405void gFexInputByteStreamTool::a_gtrx_map( const gfiber &inputData, gfiber &jf_lar_rx_data) const{
406
407 int rows = inputData.size();
408 int cols = inputData[0].size();
409
410 for(int i = 0; i < rows; i++){
411 for (int j=0; j< cols; j++){
412 if(i < 80) {
413 jf_lar_rx_data[i][j] = inputData[gPos::GTRX_MAP_A_IND[i]][j];
414 }
415 else if (j<cols-1){
416 jf_lar_rx_data[i][j] = 0;
417 }
418 else {
419 jf_lar_rx_data[i][j] = (inputData[0][0] & 0x03F0000);
420 }
421 }
422 }
423}
424
425
426void gFexInputByteStreamTool::b_gtrx_map( const gfiber &inputData, gfiber &jf_lar_rx_data) const{
427
428 int rows = inputData.size();
429 int cols = inputData[0].size();
430
431 for(int i =0; i< rows; i++){
432 for (int j=0; j< cols; j++){
433 if( i< 80) {
434 jf_lar_rx_data[i][j] = inputData[gPos::GTRX_MAP_B_IND[i]][j];
435 }
436 else if (j<cols-1){
437 jf_lar_rx_data[i][j] = 0;
438 }
439 else {
440 jf_lar_rx_data[i][j] = (inputData[0][0] & 0x03F0000);
441 }
442 }
443 }
444}
445
446
447void gFexInputByteStreamTool::c_gtrx_map( const gfiber &inputData, gfiber &outputData) const{
448
449 int rows = inputData.size();
450 int cols = inputData[0].size();
451
452 for(int i =0; i< rows; i++){
453 for (int j=0; j< cols; j++){
454 if( i< 50) {
455 outputData[i][j] = inputData[gPos::GTRX_MAP_C_IND[i]][j];
456 }
457 else if( j< cols-1 ) {
458 outputData[i][j] = 0;
459 }
460 else {
461 outputData[i][j] = ( inputData[0][0] & 0x03F0000);
462 }
463 }
464 }
465}
466
467
468void gFexInputByteStreamTool::gtReconstructABC(int XFPGA,
469 const gfiber &Xfiber, int Xin,
470 gtFPGA &XgtF, gtFPGA &Xgt,
471 int *BCIDptr,
472 int do_lconv,
473 const std::array<int, gPos::MAX_FIBERS> &XMPD_NFI,
474 const std::array<int, gPos::MAX_FIBERS> &XCALO_TYPE,
475 const gCaloTwr & XMPD_GTRN_ARR,
476 const gType & XMPD_DSTRT_ARR,
477 gTypeChar XMPD_DTYP_ARR,
478 const std::array<int, gPos::MAX_FIBERS> &XMSK,
479 gtFPGA &Xsaturation,
480 std::array<int, (gPos::AB_FIBERS*gPos::MAX_E_FIELDS)> &FiberTower,
481 std::array<int, (gPos::AB_FIBERS*gPos::MAX_E_FIELDS)> &FiberTowerSatur) const{
482
483// Output is uncalibrated gTowers with 50MeV LSB
484// Xfiber -- 80 fibers, each with seven words, 32 bits per word
485// Xin -- usually 80 -- number of fibers actually used, is 50 for EMEC/HEC FPGAC
486// XgtF -- 12*32 = 384 towers -- 50 MeV LSB
487// Xgt -- 12*32 = 384 towers -- given as integers
488
489
490// XMPD_NFI -- gives the fiber type 0, 1, 2, 3 (A & B only use types 0,1,2)
491// XMPD_DTYP_ARR -- gives the detector type for the 20 fields on a fiber
492// XMPD_D_STRT -- gives the starting bit out of 224 for 20 fields that can be on a fiber
493// XMPD_GTRN_ARR -- maps the first 16 of 20 fields onto one of the 384 towers
494
495// In the firmware Xfiber is an array of 32 bit words and on each of seven clocks new data for a BC comes in.
496
497 // gtFPGA Xsaturation;
498
499 //loop over fibers --
500 for(int irow=0; irow<gPos::ABC_ROWS; irow++){
501 for(int icolumn=0; icolumn<gPos::AB_COLUMNS; icolumn++){
502 Xgt[irow][icolumn] = 0;
503 XgtF[irow][icolumn] = 0;
504 Xsaturation[irow][icolumn] = 0;
505 }
506 }
507
508 FiberTower.fill(0);
509 FiberTowerSatur.fill(0);
510
511 // detector (data field type) type :
512 // -- "0000" - EMB, EMB/EMEC -> EM contribution 0
513 // -- "0001" - TREX,HEC - Had contribution 1
514 // -- "0010" - extended region ( EMEC) 2
515 // -- "0011" - extended region ( HEC) 3
516 // -- "0100" - position info (for EMB, EMB/EMEC)
517 // -- "0101" - CRC
518 // -- "0110" - overlaping HEC - gTower will be sum of EMEC + TREX + overlaping HEC input) 6
519 // -- "1000" - saturation flags for inputs 7-0
520 // -- "1001" - saturation flags for inputs 15-8
521 // -- "1010" - BCID_LOW
522 // -- "1111" - unused field
523
524 // use fiber 0 for BCID
525 *BCIDptr = (Xfiber[0][gPos::W280-1]&0x007F0000) >>16;
526
527 //200 MeV towers
528 std::array<int, gPos::AB_TOWERS> etowerData{};
529 std::array<int, gPos::AB_TOWERS> htowerData{};
530 std::array<int, gPos::ABC_ROWS> xetowerData{};
531 std::array<int, gPos::ABC_ROWS> xhtowerData{};
532 std::array<int, gPos::ABC_ROWS> ohtowerData{};
533
534 //50 MeV towers
535 std::array<int, gPos::AB_TOWERS> etowerDataF{};
536 std::array<int, gPos::AB_TOWERS> htowerDataF{};
537 std::array<int, gPos::ABC_ROWS> xetowerDataF{};
538 std::array<int, gPos::ABC_ROWS> xhtowerDataF{};
539 std::array<int, gPos::ABC_ROWS> ohtowerDataF{};
540
541
542
543 // save values from fiber fields for monitoring (50 MeV towers)
544
545 gFields fiberFields{{}};
546 gFields fiberFieldsUndecoded{{}};
547 gSatur fiberSaturation{{}};
548 // storing the saturation per fiber and field
549 gFields fiberFieldsSatur{{}};
550
551
552
553 for(unsigned int i=0; i<100; i++){
554
555 if (XMPD_NFI[i] < 0) continue;
556
557 if( ( Xfiber[i][gPos::W280-1] & 0x000000FF ) == 0x000000BC ) {
558
559 fiberFields[i][16] = 1;
560 }
561 else {
562 fiberFields[i][16] = 0;
563 }
564
565
566 fiberFields[i][18] = ( Xfiber[i][gPos::W280-1] & 0x007F0000) >>16 ;
567 fiberFields[i][19] = ( Xfiber[i][gPos::W280-1] & 0xFF800000) >>23 ;
568
569 if (XMPD_DTYP_ARR[ XMPD_NFI[i] ][17] == 8) {
570
571 fiberFields[i][17] = ( Xfiber[i][gPos::W280-1] & 0x0000FF00) >>8 ;
572 // TODO: Temporary fix to match FW saturation behaviour.
573 // Only propagate saturation to the lower fields (2*k for EM, k for HAD).
574 // The original code also set fiberFieldsSatur[i][k+8]=1 for HAD towers,
575 // which created phantom saturation in the second phi row of EMEC/HEC
576 // fibers. The firmware has no SAT_HIGH field, so only fields 0-7 carry
577 // saturation. Revert this (re-add k+8 propagation) if the FW is updated.
578 //
579 // TODO: Additional fix for FPGA-B (XFPGA==1).
580 // In tbuilder_mapper.vhd pFPGA_B, SAT_LOW_HEC checks "0001" (TREX)
581 // instead of "1011" (HEC regular), so saturation is never propagated
582 // for HEC regular towers in FPGA-B hardware. Skip setting
583 // fiberFieldsSatur for HEC regular fields (type 11) when XFPGA==1
584 // to match the FW bug. Revert when FW is fixed.
585 for(unsigned int k=0; k<8; k++){
586 if( fiberFields[i][17] & (1<<k) ) {
587 fiberSaturation[i][k] = 1;
588 // EM towers - multiply by two
589 // HAD towers (avoid Tile) - copy the field with +8
590 if ( XMPD_DTYP_ARR[XMPD_NFI[i]][2*k] == 0) {
591 //std::cout << "saturation EM " << i << " " << k << std::endl;
592 fiberFieldsSatur[i][2*k] = 1;
593 } else if ( XMPD_DTYP_ARR[XMPD_NFI[i]][k] != 1) {
594 // Skip HEC regular (type 11) saturation for FPGA-B
595 // due to FW bug in tbuilder_mapper.vhd SAT_LOW_HEC
596 if (!(XFPGA == 1 && XMPD_DTYP_ARR[XMPD_NFI[i]][k] == 11)) {
597 fiberFieldsSatur[i][k] = 1;
598 }
599 }
600 }
601 }
602 }
603 //overlap and extended region for FPGAa-(0) & FPGAb-(1) - NEWSAT
604 for (unsigned int k=0; k<8; ++k){
605 int krow = XMPD_GTRN_ARR[i][k]/12;
606 int kcolumn = XMPD_GTRN_ARR[i][k]%12; //columns 0-11
607
608 int korow = XMPD_GTRN_ARR[i][k];
609 int kxrow = XMPD_GTRN_ARR[i][k];
610
611 int kocolumn = 4;
612 int kxcolumn = 0;
613
614 // note that they are different in FPGA a and FPGA b
615 if (XFPGA == 0){
616 kocolumn = 4;
617 kxcolumn = 0;
618 } else if (XFPGA == 1){
619 kocolumn = 7;
620 kxcolumn = 11;
621 }
622
623 if (fiberSaturation[i][k] == 1){
624 //etowers
625 if ( ( XMPD_DTYP_ARR[XMPD_NFI[i]][2*k] == 0 ) && ( XMPD_GTRN_ARR[i][2*k] > -1 ) ){
626 int krow2 = XMPD_GTRN_ARR[i][2*k]/12;
627 int kcolumn2 = XMPD_GTRN_ARR[i][2*k]%12;
628 Xsaturation[krow2][kcolumn2] = 1;
629 }
630 //htowers - XMPD_DTYP_ARR = 11 (0b1011) only defined for FPGAa and FPGAb
631 // TODO: Temporary fix to match FW bug in tbuilder_mapper.vhd pFPGA_B.
632 // FPGA-A SAT_LOW_HEC checks "1011" (HEC regular) — correct.
633 // FPGA-B SAT_LOW_HEC checks "0001" (TREX) — wrong, never matches
634 // any EMEC/HEC fiber field, so bit 12 of htower_data is never set
635 // and saturation is never propagated for HEC regular towers.
636 // Skip this condition for FPGA-B to match the actual FW behaviour.
637 // Revert this (remove XFPGA!=1 guard) when the FW is fixed.
638 if( (XFPGA != 1) && (XMPD_DTYP_ARR[ XMPD_NFI[i] ][k] == 11 ) && ( XMPD_GTRN_ARR[i][k] > -1 ) ){
639 Xsaturation[ krow][kcolumn] = 1;
640 }
641
642 // Applying condition for extended and overlap regions in fpga a&b
643
644 if (XFPGA < 2) {
645 // FPGA a and FPGA b - extended region condition
646 if( (XMPD_DTYP_ARR[ XMPD_NFI[i] ][k] == 3 ) && ( XMPD_GTRN_ARR[i][k] > -1 ) ){
647 Xsaturation[ kxrow][kxcolumn] = 1;
648 }
649 //extended region for FPGAa and FPGAb
650 if( (XMPD_DTYP_ARR[ XMPD_NFI[i] ][k] == 2 ) && ( XMPD_GTRN_ARR[i][k] > -1 ) ){
651 Xsaturation[ kxrow][kxcolumn] = 1;
652 }
653 //overlap region for FPGAa and FPGAb - no equivalent for FPGAc
654 if( (XMPD_DTYP_ARR[ XMPD_NFI[i] ][k] == 6 ) && ( XMPD_GTRN_ARR[i][k] > -1 ) ){
655 Xsaturation[ korow][kocolumn] = 1;
656 }
657 } else {
658 // FPGAc -- all channels type 3 & 2
659 if( (XMPD_DTYP_ARR[ XMPD_NFI[i] ][k] == 3 ) && ( XMPD_GTRN_ARR[i][k] > -1 ) ){
660 Xsaturation[ krow][kcolumn] = 1;
661 }
662 if( (XMPD_DTYP_ARR[ XMPD_NFI[i] ][k] == 2 ) && ( XMPD_GTRN_ARR[i][k] > -1 ) ){
663 Xsaturation[ krow][kcolumn] = 1;
664 }
665 }
666 // TODO: Temporary fix to match FW saturation behaviour.
667 // No k+8 propagation: the firmware has no SAT_HIGH ("1001")
668 // field for any fiber type -- the saturation byte only covers
669 // the lower 8 data channels (fields 0-7). See tbuilder_mapper.vhd
670 // SAT_GEN_8_A and fiber_map_pkg.vhd AMPD_DET_TYPE.
671 // The original code propagated saturation to fiberFieldsSatur[i][k+8]
672 // and then mapped those phantom flags into the second phi row of
673 // EMEC/HEC towers, causing false saturation in simulation.
674 // Revert this (re-add k+8 propagation) if the FW is updated to
675 // include a SAT_HIGH field.
676 }// close fiberSaturation loop
677 } // k (max 8) loop close
678 } // i (max 100) loop close
679
680 //Loop over fibers
681 for(int iFiber = 0; iFiber < Xin; iFiber++) {
682 // first do CRC check
683 std::array<uint32_t, 6> tmp;
684 for(int i = 0; i < 6; i++){ tmp[i] = Xfiber[iFiber][i]; };
685 // coverity[uninit_use_in_cal : FALSE]
686 uint32_t CRC = crc9d32(tmp, 6, 1);
687 int withoutComma = Xfiber[iFiber][6] & 0xFFFFFF00 ;
688 CRC = crc9d23(withoutComma, CRC, 1 );
689 uint32_t StoredCRC = ( (Xfiber[iFiber][6]>>23) & 0x000001FF);
690 if( (CRC != StoredCRC) && (StoredCRC != 0 ) ) {
691
692 std::stringstream sdetail;
693 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: Fiber " << iFiber << "of Xin " << Xin << ": BAD New CRC: " << CRC << "Stored CRC "<< StoredCRC ;
694 std::stringstream slocation;
695 slocation << "Fiber " << iFiber << "of Xin " << Xin;
696 std::stringstream stitle;
697 stitle << "Bad CRC" ;
698 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
699
700 }
701
702 // now check if CRC lower bits are correct in the trailer
703 int fiber_type = XMPD_NFI[iFiber];
704 // each fiber has 20 pieces of information -- called iDatum here
705 for(int iDatum = 0; iDatum < 16; iDatum++) {
706 // tells where the data is coming from -- see data field type above
707 int dataType = XMPD_DTYP_ARR[fiber_type][iDatum];
708 // tower number 0 - 383
709 int ntower = XMPD_GTRN_ARR[iFiber][iDatum];
710 if( ntower == -1 ){
711 ATH_MSG_DEBUG("[gFexInputByteStreamTool::gtReconstructABC: unused location iFiber "<< iFiber << ", calo type "<< XCALO_TYPE[iFiber]<<", data type "<< dataType <<", iDatum " << iDatum << "tower " << ntower);
712 }
713 else if( (ntower < 0) || (ntower >383) ){
714
715 std::stringstream sdetail;
716 sdetail << "[gFexInputByteStreamTool::gtReconstructABC: bad value of ntower: iFiber "<< iFiber<< ", calo type"<< XCALO_TYPE[iFiber]<< ", data type "<< dataType<< ", iDatum "<< iDatum<< "tower "<< ntower ;
717 std::stringstream slocation;
718 slocation << "iFiber "<< iFiber<< ", calo type"<< XCALO_TYPE[iFiber];
719 std::stringstream stitle;
720 stitle << "Bad value of ntower" ;
721 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
722
723 }
724
725 // bit number in the 32*7 = 234 bits transmitted in one BC
726 // word refers to the 7 32 bits words transmitted in each BC
727 int ihigh = XMPD_DSTRT_ARR[fiber_type][iDatum];
728 int ihword = ihigh/32;
729 int ihbit = ihigh%32;
730
731 int ilow = 0;
732 int ilword = 0;
733 int ilbit = 0;
734
735 int hTREXval = 0;
736 int lTREXval = 0;
737 int hHECval = 0;
738 int lHECval = 0;
739
740 // need to be sure to skip positon data!
741 int mask = 0;
742 int lmask = 0;
743 int hmask = 0;
744
745 if( XMSK[iFiber] != 1 ) {
746 dataType = 99;
747 }
748
749 //Different kinds of data type
750 if( (XCALO_TYPE[iFiber] < 3) && (ntower>-1) && (ntower<384) ) {
751 switch(dataType){
752 case 0:
753 ilow = ihigh - 11;
754 ilword = ilow/32;
755 ilbit = ilow%32;
756 if(ilword == ihword){
757 mask = 0x00000FFF;
758 mask = mask << (ilbit);
759 etowerData[ntower] = etowerData[ntower] | ( (Xfiber[iFiber][ihword] & mask) >> ilbit );
760 // undo multilinear decoding
761 if( do_lconv){
762 fiberFieldsUndecoded[iFiber][iDatum] = etowerData[ntower];
763 undoMLE( etowerData[ntower] );
764 etowerDataF[ntower] = etowerData[ntower];
765 fiberFields[iFiber][iDatum] = etowerData[ntower];
766
767 }
768 else {
769 // sign extend etower data
770 if( etowerData[ntower] & 0x00000800 ){ etowerData[ntower] = (etowerData[ntower] | 0xFFFFF000) ;}
771 etowerData[ntower] = etowerData[ntower]*4;
772 etowerDataF[ntower] = etowerData[ntower];
773 }
774 }
775 else {
776
777 std::stringstream sdetail;
778 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: wrongly packed data "<< fiber_type<< ", "<<dataType<< ", "<<ilword<< ", " <<ihword ;
779 std::stringstream slocation;
780 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
781 std::stringstream stitle;
782 stitle << "Wrongly packed data" ;
783 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
784
785 }
786 break;
787
788 case 1:
789 ilow = ihigh - 11;
790 ilword = ilow/32;
791 ilbit = ilow%32;
792
793 hTREXval = Xfiber[iFiber][ihword];
794 lTREXval = Xfiber[iFiber][ilword];
795 mask =0;
796 lmask =0;
797 hmask =0;
798
799 if(ilword == ihword){
800 mask = 0x00000FFF;
801 mask = mask << ilbit;
802 htowerData[ntower] = htowerData[ntower] | ( (hTREXval & mask) >> (ilbit) );
803 }
804 else if ( ihbit == 7 ) {
805 mask = 0x0000000F;
806 hmask = 0x000000FF;
807 htowerData[ntower] = htowerData[ntower] | ( (hTREXval & hmask) << 4);
808 lmask = 0xF0000000;
809 htowerData[ntower] = htowerData[ntower] | ( ( (lTREXval & lmask) >> 28)&mask) ;
810 }
811 else if ( ihbit == 3) {
812 mask = 0x000000FF;
813 hmask = 0x0000000F;
814 htowerData[ntower] = htowerData[ntower] | ( ( hTREXval & hmask) << 8);
815 lmask = 0xFF000000;
816 htowerData[ntower] = htowerData[ntower] | ( ( (lTREXval & lmask) >> 24) &mask) ;
817 }
818 else {
819
820 std::stringstream sdetail;
821 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: wrongly packed data "<< fiber_type<< ", "<<dataType<< ", "<<ilword<< ", " <<ihword ;
822 std::stringstream slocation;
823 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
824 std::stringstream stitle;
825 stitle << "Wrongly packed data" ;
826 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
827
828 }
829
830 // mulitply by 20 to make 50 MeV LSB
831 if( (Xin > 50) ) {
832 // include this here before mulitplicaiton by 20
833 fiberFieldsUndecoded[iFiber][iDatum] = htowerData[ntower];
834 htowerData[ntower] = 20*htowerData[ntower];
835 htowerDataF[ntower] = htowerData[ntower];
836 fiberFields[iFiber][iDatum] = htowerData[ntower];
837 }
838 else {
839 if( do_lconv){
840 fiberFieldsUndecoded[iFiber][1] = htowerData[ntower];
841 undoMLE( htowerData[ntower] );
842 htowerDataF[ntower] = htowerData[ntower];
843 fiberFields[iFiber][1] = htowerData[ntower];
844 }
845 else {
846 // sign extend etower data
847 if( htowerData[ntower] & 0x00000800 ){ htowerData[ntower] = (htowerData[ntower] | 0xFFFFF000) ;}
848 htowerData[ntower] = htowerData[ntower]*4;
849 htowerDataF[ntower] = htowerData[ntower];
850 }
851 }
852 break;
853
854 case 2:
855 ilow = ihigh - 11;
856 ilword = ilow/32;
857 ilbit = ilow%32;
858 if( (ntower > 32) || (ntower < 0) ){
859
860 std::stringstream sdetail;
861 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: bad value of nTower for extended region 2.4 - 2.5 in eta" ;
862 std::stringstream slocation;
863 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
864 std::stringstream stitle;
865 stitle << "Bad value of nTower in extended eta" ;
866 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
867
868 }
869 if(ilword == ihword){
870 int mask = 0x00000FFF;
871 mask = mask << ilbit;
872 xetowerData[ntower] = xetowerData[ntower] | ( (Xfiber[iFiber][ihword]&mask) >> (ilbit) );
873 }
874 else if ( ihbit == 7 ) {
875 mask = 0x0000000F;
876 hmask = 0x000000FF;
877 xetowerData[ntower] = xetowerData[ntower] | ( (Xfiber[iFiber][ihword]&hmask) << 4);
878 lmask = 0xF0000000;
879 xetowerData[ntower] = xetowerData[ntower] | ( ( (Xfiber[iFiber][ilword]&lmask) >> 28)&mask) ;
880 }
881 else if ( ihbit == 3) {
882 mask = 0x000000FF;
883 hmask = 0x000000F;
884 xetowerData[ntower] = xetowerData[ntower] | ( (Xfiber[iFiber][ihword]&hmask) << 8);
885 lmask = 0xFF000000;
886 xetowerData[ntower] = xetowerData[ntower] | ( ( (Xfiber[iFiber][ilword]&lmask) >> 24)&mask) ;
887 }
888 else {
889
890 std::stringstream sdetail;
891 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: wrongly packed data "<< fiber_type<< ", "<<dataType<< ", "<<ilword<< ", " <<ihword ;
892 std::stringstream slocation;
893 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
894 std::stringstream stitle;
895 stitle << "Wrongly packed data" ;
896 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
897
898 }
899 // undo multilinear decoding
900 if( do_lconv){
901 fiberFieldsUndecoded[iFiber][iDatum] = xetowerData[ntower];
902 undoMLE( xetowerData[ntower] );
903 xetowerDataF[ntower] = xetowerData[ntower];
904 fiberFields[iFiber][iDatum] = xetowerData[ntower];
905
906 }
907 else {
908 // sign extend etower data
909 if( xetowerData[ntower] & 0x00000800 ){ xetowerData[ntower] = (xetowerData[ntower] | 0xFFFFF000) ;}
910 xetowerData[ntower] = xetowerData[ntower]*4;
911 xetowerDataF[ntower] = xetowerData[ntower];
912 }
913 break;
914
915 case 3:
916 ilow = ihigh - 11;
917 ilword = ilow/32;
918 ilbit = ilow%32;
919 if(ilword == ihword){
920 mask = 0x00000FFF;
921 mask = mask << ilbit;
922 xhtowerData[ntower] = xhtowerData[ntower] | ( (Xfiber[iFiber][ihword]&mask) >> (ilbit) );
923 }
924 else if ( ihbit == 7 ) {
925 mask = 0x0000000F;
926 hmask = 0x000000FF;
927 xhtowerData[ntower] = xhtowerData[ntower] | ( (Xfiber[iFiber][ihword]&hmask) << 4);
928 lmask = 0xF0000000;
929 xhtowerData[ntower] = xhtowerData[ntower] | ( ( (Xfiber[iFiber][ilword]&lmask) >> 28)&mask) ;
930 }
931 else if ( ihbit == 3) {
932 mask = 0x000000FF;
933 hmask = 0x0000000F;
934 xhtowerData[ntower] = xhtowerData[ntower] | ( (Xfiber[iFiber][ihword]&hmask) << 8);
935 lmask = 0xFF000000;
936 xhtowerData[ntower] = xhtowerData[ntower] | ( ( (Xfiber[iFiber][ilword]&lmask) >> 24)&mask) ;
937 }
938 else {
939
940 std::stringstream sdetail;
941 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: wrongly packed data "<< fiber_type<< ", "<<dataType<< ", "<<ilword<< ", " <<ihword ;
942 std::stringstream slocation;
943 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
944 std::stringstream stitle;
945 stitle << "Wrongly packed data" ;
946 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
947
948 }
949 if( ntower > 32 ){
950
951 std::stringstream sdetail;
952 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: bad value of nTower for extended region 2.4 - 2.5 in eta" ;
953 std::stringstream slocation;
954 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
955 std::stringstream stitle;
956 stitle << "Bad value of nTower in extended eta" ;
957 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
958
959 }
960 // undo multilinear decoding
961 if( do_lconv){
962 fiberFieldsUndecoded[iFiber][iDatum] = xhtowerData[ntower];
963 undoMLE( xhtowerData[ntower] );
964 xhtowerDataF[ntower] = xhtowerData[ntower];
965 fiberFields[iFiber][iDatum] = xhtowerData[ntower];
966 }
967 else {
968 // sign extend etower data
969 if( xhtowerData[ntower] & 0x00000800 ){ xhtowerData[ntower] = (xhtowerData[ntower] | 0xFFFFF000) ;}
970 xhtowerData[ntower] = xhtowerData[ntower]*4;
971 xhtowerDataF[ntower] = xhtowerData[ntower];
972 }
973 break;
974
975 case 6:
976 ilow = ihigh - 11;
977 ilword = ilow/32;
978 ilbit = ilow%32;
979 if(ilword == ihword){
980 mask = 0x00000FFF;
981 mask = mask << ilbit;
982 ohtowerData[ntower] = ohtowerData[ntower] | ( (Xfiber[iFiber][ihword]&mask) >> (ilbit) );
983 }
984 else if ( ihbit == 7 ) {
985 mask = 0x0000000F;
986 hmask = 0x000000FF;
987 ohtowerData[ntower] = ohtowerData[ntower] | ( (Xfiber[iFiber][ihword]&hmask) << 4);
988 lmask = 0xF0000000;
989 ohtowerData[ntower] = ohtowerData[ntower] | ( ( (Xfiber[iFiber][ilword]&lmask) >> 28)&mask) ;
990 }
991 else if ( ihbit == 3) {
992 mask = 0x000000FF;
993 hmask = 0x0000000F;
994 ohtowerData[ntower] = ohtowerData[ntower] | ( (Xfiber[iFiber][ihword]&hmask) << 8);
995 lmask = 0xFF000000;
996 ohtowerData[ntower] = ohtowerData[ntower] | ( ( (Xfiber[iFiber][ilword]&lmask) >> 24)&mask) ;
997 }
998 else {
999
1000 std::stringstream sdetail;
1001 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: wrongly packed data "<< fiber_type<< ", "<<dataType<< ", "<<ilword<< ", " <<ihword ;
1002 std::stringstream slocation;
1003 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
1004 std::stringstream stitle;
1005 stitle << "Wrongly packed data" ;
1006 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
1007
1008 }
1009 if( ntower > 32 ){
1010
1011 std::stringstream sdetail;
1012 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: bad value of nTower for extended region 2.4 - 2.5 in eta" ;
1013 std::stringstream slocation;
1014 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
1015 std::stringstream stitle;
1016 stitle << "Bad value of nTower in extended eta" ;
1017 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
1018
1019 }
1020 if( do_lconv){
1021 fiberFieldsUndecoded[iFiber][iDatum] = ohtowerData[ntower];
1022 undoMLE( ohtowerData[ntower] );
1023 ohtowerDataF[ntower] = ohtowerData[ntower];
1024 fiberFields[iFiber][iDatum] = ohtowerData[ntower];
1025 }
1026 else {
1027 // sign extend etower data
1028 if( ohtowerData[ntower] & 0x00000800 ){ ohtowerData[ntower] = (ohtowerData[ntower] | 0xFFFFF000) ;}
1029 ohtowerData[ntower] = ohtowerData[ntower]*4;
1030 ohtowerDataF[ntower] = ohtowerData[ntower];
1031 }
1032 break;
1033
1034 case 11:
1035 ilow = ihigh - 11;
1036 ilword = ilow/32;
1037 ilbit = ilow%32;
1038
1039 hHECval = Xfiber[iFiber][ihword];
1040 lHECval = Xfiber[iFiber][ilword];
1041 if(ilword == ihword){
1042 mask = 0x00000FFF;
1043 mask = mask << ilbit;
1044 htowerData[ntower] = htowerData[ntower] | ( (hHECval & mask) >> (ilbit) );
1045 }
1046 else if ( ihbit == 7 ) {
1047 mask = 0x0000000F;
1048 hmask = 0x000000FF;
1049 htowerData[ntower] = htowerData[ntower] | ( (hHECval & hmask) << 4);
1050 lmask = 0xFF000000;
1051 htowerData[ntower] = htowerData[ntower] | ( ( (lHECval & lmask) >> 28)&mask) ;
1052 }
1053 else if ( ihbit == 3) {
1054 mask = 0x000000FF;
1055 hmask = 0x0000000F;
1056 htowerData[ntower] = htowerData[ntower] | ( ( hHECval & hmask) << 8);
1057 lmask = 0xFF000000;
1058 htowerData[ntower] = htowerData[ntower] | ( ( (lHECval & lmask) >> 24) &mask) ;
1059 }
1060 else {
1061
1062 std::stringstream sdetail;
1063 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: wrongly packed data "<< fiber_type<< ", "<<dataType<< ", "<<ilword<< ", " <<ihword ;
1064 std::stringstream slocation;
1065 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
1066 std::stringstream stitle;
1067 stitle << "Wrongly packed data" ;
1068 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
1069
1070 }
1071 if( do_lconv){
1072 fiberFieldsUndecoded[iFiber][iDatum] = htowerData[ntower];
1073 undoMLE( htowerData[ntower] );
1074 htowerDataF[ntower] = htowerData[ntower];
1075 fiberFields[iFiber][iDatum] = htowerData[ntower];
1076 }
1077 else {
1078 // sign extend etower data
1079 if( htowerData[ntower] & 0x00000800 ){ htowerData[ntower] = (htowerData[ntower] | 0xFFFFF000) ;}
1080 htowerData[ntower] = htowerData[ntower]*4;
1081 htowerDataF[ntower] = htowerData[ntower];
1082 }
1083 break;
1084 }
1085 // FPGA C EMEC/HEC + FCAL
1086 // These all have same dataType as extended ECAL and extended HCAL
1087 }
1088 else if ( (ntower>-1) && (ntower<384) ){
1089 // this is FPGA C
1090 // only types 2 and 3 exist in FPGA C
1091
1092 switch(dataType){
1093 case 2:
1094 ilow = ihigh - 11;
1095 ilword = ilow/32;
1096 ilbit = ilow%32;
1097
1098 if( etowerData[ntower] != 0 ) {
1099
1100 std::stringstream sdetail;
1101 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: etowerData[nTower] is not zero, inconsistent constants! "<< etowerData[ntower] ;
1102 std::stringstream slocation;
1103 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
1104 std::stringstream stitle;
1105 stitle << "etowerData not zero" ;
1106 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
1107
1108 } else {
1109
1110 if(ilword == ihword){
1111 int mask = 0x00000FFF;
1112 mask = mask << ilbit;
1113 etowerData[ntower] = etowerData[ntower] | ( (Xfiber[iFiber][ihword]&mask) >> (ilbit) );
1114 }
1115 else if ( ihbit == 7 ) {
1116 mask = 0x0000000F;
1117 hmask = 0x000000FF;
1118 etowerData[ntower] = etowerData[ntower] | ( (Xfiber[iFiber][ihword]&hmask) << 4);
1119 lmask = 0xF0000000;
1120 etowerData[ntower] = etowerData[ntower] | ( ( (Xfiber[iFiber][ilword]&lmask) >> 28)&mask) ;
1121 }
1122 else if ( ihbit == 3) {
1123 mask = 0x000000FF;
1124 hmask = 0x000000F;
1125 etowerData[ntower] = etowerData[ntower] | ( (Xfiber[iFiber][ihword]&hmask) << 8);
1126 lmask = 0xFF000000;
1127 etowerData[ntower] = etowerData[ntower] | ( ( (Xfiber[iFiber][ilword]&lmask) >> 24)&mask) ;
1128 }
1129 else {
1130
1131 std::stringstream sdetail;
1132 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: wrongly packed data "<< fiber_type<< ", "<<dataType<< ", "<<ilword<< ", " <<ihword ;
1133 std::stringstream slocation;
1134 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
1135 std::stringstream stitle;
1136 stitle << "Wrongly packed data" ;
1137 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
1138
1139 }
1140 // undo multilinear decoding
1141 if( do_lconv){
1142 fiberFieldsUndecoded[iFiber][iDatum] = etowerData[ntower];
1143 undoMLE( etowerData[ntower] );
1144 etowerDataF[ntower] = etowerData[ntower];
1145 fiberFields[iFiber][iDatum] = etowerData[ntower];
1146 }
1147 else {
1148 // sign extend etower data
1149 if( etowerData[ntower] & 0x00000800 ){ etowerData[ntower] = (etowerData[ntower] | 0xFFFFF000) ;}
1150 etowerData[ntower] = etowerData[ntower]*4;
1151 etowerDataF[ntower] = etowerData[ntower];
1152 }
1153 }
1154 break;
1155
1156 case 3:
1157 ilow = ihigh - 11;
1158 ilword = ilow/32;
1159 ilbit = ilow%32;
1160
1161 if( htowerData[ntower] != 0 ) {
1162 std::stringstream sdetail;
1163 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: etowerData[nTower] is not zero, inconsistent constants! "<< etowerData[ntower] ;
1164 std::stringstream slocation;
1165 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
1166 std::stringstream stitle;
1167 stitle << "etowerData not zero" ;
1168 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
1169
1170 } else {
1171
1172 if(ilword == ihword){
1173 mask = 0x00000FFF;
1174 mask = mask << ilbit;
1175 htowerData[ntower] = htowerData[ntower] | ( (Xfiber[iFiber][ihword]&mask) >> (ilbit) );
1176 }
1177 else if ( ihbit == 7 ) {
1178 mask = 0x0000000F;
1179 hmask = 0x000000FF;
1180 htowerData[ntower] = htowerData[ntower] | ( (Xfiber[iFiber][ihword]&hmask) << 4);
1181 lmask = 0xF0000000;
1182 htowerData[ntower] = htowerData[ntower] | ( ( (Xfiber[iFiber][ilword]&lmask) >> 28)&mask) ;
1183 }
1184 else if ( ihbit == 3) {
1185 mask = 0x000000FF;
1186 hmask = 0x0000000F;
1187 htowerData[ntower] = htowerData[ntower] | ( (Xfiber[iFiber][ihword]&hmask) << 8);
1188 lmask = 0xFF000000;
1189 htowerData[ntower] = htowerData[ntower] | ( ( (Xfiber[iFiber][ilword]&lmask) >> 24)&mask) ;
1190 }
1191 else {
1192
1193 std::stringstream sdetail;
1194 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: wrongly packed data "<< fiber_type<< ", "<<dataType<< ", "<<ilword<< ", " <<ihword ;
1195 std::stringstream slocation;
1196 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
1197 std::stringstream stitle;
1198 stitle << "Wrongly packed data" ;
1199 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
1200
1201 }
1202 // undo multilinear decoding
1203 if( do_lconv){
1204 fiberFieldsUndecoded[iFiber][iDatum] = htowerData[ntower];
1205 undoMLE( htowerData[ntower] );
1206 htowerDataF[ntower] = htowerData[ntower];
1207 fiberFields[iFiber][iDatum] = htowerData[ntower];
1208 }
1209 else {
1210 // sign extend etower data
1211 if( htowerData[ntower] & 0x00000800 ){ htowerData[ntower] = (htowerData[ntower] | 0xFFFFF000) ;}
1212 htowerData[ntower] = htowerData[ntower]*4;
1213 htowerDataF[ntower] = htowerData[ntower];
1214 }
1215 }
1216 break;
1217
1218 case 15:
1219 break;
1220
1221 case 99:
1222 break;
1223
1224 default:
1225
1226 std::stringstream sdetail;
1227 sdetail << "[gFexInputByteStreamTool::gtReconstructABC]: wrong detector type "<< dataType ;
1228 std::stringstream slocation;
1229 slocation << "Fiber type "<< fiber_type<< " and data type"<< dataType;
1230 std::stringstream stitle;
1231 stitle << "Wrong detector type" ;
1232 printError(slocation.str(),stitle.str(),MSG::DEBUG,sdetail.str());
1233
1234 } // end of case statement for FPGAC
1235 } // end of | eta | > 2,5
1236 } // end of loop over words
1237 } // end of loop over fibers
1238
1239
1240 // no need for xdtower, xhtower and ohtower in FPGA C -- but these will all be zero in that case.
1241 if( XFPGA == 0 ) {
1242 for(int itower=0;itower<384;itower++){
1243 int icolumn = itower%12;
1244 int irow = itower/12;
1245
1246 // 50 MeV towers
1247 int xF = etowerDataF[itower] + htowerDataF[itower];
1248 // 200 MeV towers
1249 int x = ( (etowerData[itower]>>2) + (htowerData[itower]>>2) );
1250
1251 signExtend(&xF,18);
1252 signExtend(&x,18);
1253
1254 Xgt[irow][icolumn] = x;
1255 XgtF[irow][icolumn] = xF;
1256
1257 // etra region in FPGA A (eta ~ -2.5)
1258 if ( icolumn == 0) {
1259 int xx = ( (xetowerData[irow]>>2) + (xhtowerData[irow]>>2) );
1260 signExtend(&xx,18);
1261 Xgt[irow][icolumn] = Xgt[irow][icolumn] + xx;
1262 }
1263 if ( icolumn == 4) {
1264 // 200 MeV towers
1265 int ox = (ohtowerData[irow] >> 2 ) ;
1266 signExtend(&ox,18);
1267 Xgt[irow][icolumn] = Xgt[irow][icolumn] + ox ;
1268 }
1269 }
1270 }
1271 else if ( XFPGA == 1 ) {
1272 for(int itower=0;itower<384;itower++){
1273 int icolumn = itower%12;
1274 int irow = itower/12;
1275
1276 // 50 MeV towers
1277 int xF = etowerDataF[itower] + htowerDataF[itower] ;
1278 // 200 MeV towers
1279 int x = ( (etowerData[itower]>>2) + (htowerData[itower] >> 2) );
1280
1281 signExtend(&xF,18);
1282 signExtend(&x,18);
1283
1284 Xgt[irow][icolumn] = x;
1285 XgtF[irow][icolumn] = xF;
1286
1287 // extra region FPGA B (eta ~ 2.5)
1288 if ( icolumn == 11) {
1289 // 50 MeV towers
1290 // int xxF = xetower_dataF[irow] + xhtower_dataF[irow] ;
1291 // 200 MeV towers
1292 int xx = ( (xetowerData[irow]>>2) + (xhtowerData[irow]>>2) );
1293 // signExtend(&xxF,18);
1294 signExtend(&xx,18);
1295 Xgt[irow][icolumn] = Xgt[irow][icolumn] + xx;
1296 }
1297 if ( icolumn == 7 ) {
1298 // 200 MeV towers
1299 // int xoF = ohtowerData[irow];
1300 int xo = ohtowerData[irow]>>2;
1301 // signExtend(&xoF,18);
1302 signExtend(&xo,18);
1303 Xgt[irow][icolumn] = Xgt[irow][icolumn] + xo;
1304 }
1305 }
1306 }
1307 else if ( XFPGA == 2 ) {
1308 for(int itower=0;itower<384;itower++){
1309 int icolumn = itower%12;
1310 int irow = itower/12;
1311
1312 // 50 MeV towers
1313 int xF = etowerDataF[itower] + htowerDataF[itower] ;
1314 // 200 MeV towers
1315 int x = ( (etowerData[itower]>>2 ) + (htowerData[itower]>>2));
1316 signExtend(&xF,18);
1317 signExtend(&x,18);
1318
1319 Xgt[irow][icolumn] = x;
1320 XgtF[irow][icolumn] = xF;
1321 }
1322 }
1323 else {
1324 ATH_MSG_DEBUG("[gFexInputByteStreamTool::gtReconstructABC]: Bad FPGA # "<< XFPGA);
1325 }
1326 //
1327
1328 // MLE fiber data
1329 for(int iFiber = 0; iFiber < Xin; ++iFiber) {
1330 for(int iDatum = 0; iDatum < 16; ++iDatum) {
1331 int codedData = fiberFieldsUndecoded[iFiber][iDatum];
1332 int saturData = fiberFieldsSatur[iFiber][iDatum];
1333 unsigned int index = (16*iFiber) + iDatum;
1334 FiberTower[index] = codedData;
1335 FiberTowerSatur[index] = saturData;
1336 }
1337 }
1338}
1339
1340
1341
1342int gFexInputByteStreamTool::crc9d32(const std::array<uint32_t, 6> &inWords,int numWords,int reverse) const{
1343 // calculate this for reversed bits
1344
1345 std::array<uint32_t, 32> dIn;
1346 std::array<uint32_t, 9> crc_s;
1347 std::array<uint32_t, 9> crc_r;
1348
1349 crc_s.fill(1);
1350 crc_r.fill(1);
1351
1352 int crc_word = 0x000;
1353 unsigned int mask = 0x00000001;
1354
1355 for(int k =0; k < numWords; k++) {
1356 if( reverse == 1 ) {
1357 for (int i =0 ; i < 32; i++ ) {
1358 dIn[31-i] = (inWords[k] & (mask << i));
1359 dIn[31-i] = ((dIn[31-i] >> i) & 0x00000001);
1360 }
1361 }
1362 else {
1363 for (int i =0 ; i<32; i++ ) {
1364 dIn[i] = inWords[k] & (mask << i);
1365 dIn[i] = ((dIn[i] >> i) & 0x0000001);
1366 }
1367 }
1368 for(int j=0; j<9; j++){
1369 crc_s[j] = crc_r[j];
1370 }
1371
1372 crc_r[0] = crc_s[0] ^ crc_s[2] ^ crc_s[3] ^ crc_s[6] ^ crc_s[8] ^ dIn[0] ^ dIn[2] ^ dIn[3] ^ dIn[5] ^ dIn[6] ^ dIn[7] ^ dIn[8] ^ dIn[9] ^ dIn[10] ^ dIn[11] ^ dIn[15] ^ dIn[18] ^ dIn[19] ^ dIn[20] ^ dIn[21] ^ dIn[22] ^ dIn[23] ^ dIn[25] ^ dIn[26] ^ dIn[29] ^ dIn[31];
1373
1374 crc_r[1] = crc_s[1] ^ crc_s[2] ^ crc_s[4] ^ crc_s[6] ^ crc_s[7] ^ crc_s[8] ^ dIn[0] ^ dIn[1] ^ dIn[2] ^ dIn[4] ^ dIn[5] ^ dIn[12] ^ dIn[15] ^ dIn[16] ^ dIn[18] ^ dIn[24] ^ dIn[25] ^ dIn[27] ^ dIn[29] ^ dIn[30] ^ dIn[31];
1375
1376 crc_r[2] = crc_s[2] ^ crc_s[3] ^ crc_s[5] ^ crc_s[7] ^ crc_s[8] ^ dIn[1] ^ dIn[2] ^ dIn[3] ^ dIn[5] ^ dIn[6] ^ dIn[13] ^ dIn[16] ^ dIn[17] ^ dIn[19] ^ dIn[25] ^ dIn[26] ^ dIn[28] ^ dIn[30] ^ dIn[31];
1377
1378 crc_r[3] = crc_s[0] ^ crc_s[2] ^ crc_s[4] ^ dIn[0] ^ dIn[4] ^ dIn[5] ^ dIn[8] ^ dIn[9] ^ dIn[10] ^ dIn[11] ^ dIn[14] ^ dIn[15] ^ dIn[17] ^ dIn[19] ^ dIn[21] ^ dIn[22] ^ dIn[23] ^ dIn[25] ^ dIn[27];
1379
1380 crc_r[4] = crc_s[1] ^ crc_s[2] ^ crc_s[5] ^ crc_s[6] ^ crc_s[8] ^ dIn[0] ^ dIn[1] ^ dIn[2] ^ dIn[3] ^ dIn[7] ^ dIn[8] ^ dIn[12] ^ dIn[16] ^ dIn[19] ^ dIn[21] ^ dIn[24] ^ dIn[25] ^ dIn[28] ^ dIn[29] ^ dIn[31];
1381
1382 crc_r[5] = crc_s[0] ^ crc_s[7] ^ crc_s[8] ^ dIn[0] ^ dIn[1] ^ dIn[4] ^ dIn[5] ^ dIn[6] ^ dIn[7] ^ dIn[10] ^ dIn[11] ^ dIn[13] ^ dIn[15] ^ dIn[17] ^ dIn[18] ^ dIn[19] ^ dIn[21] ^ dIn[23] ^ dIn[30] ^ dIn[31];
1383
1384 crc_r[6] = crc_s[0] ^ crc_s[1] ^ crc_s[2] ^ crc_s[3] ^ crc_s[6] ^ dIn[0] ^ dIn[1] ^ dIn[3] ^ dIn[9] ^ dIn[10] ^ dIn[12] ^ dIn[14] ^ dIn[15] ^ dIn[16] ^ dIn[21] ^ dIn[23] ^ dIn[24] ^ dIn[25] ^ dIn[26] ^ dIn[29];
1385
1386 crc_r[7] = crc_s[0] ^ crc_s[1] ^ crc_s[4] ^ crc_s[6] ^ crc_s[7] ^ crc_s[8] ^ dIn[0] ^ dIn[1] ^ dIn[3] ^ dIn[4] ^ dIn[5] ^ dIn[6] ^ dIn[7] ^ dIn[8] ^ dIn[9] ^ dIn[13] ^ dIn[16] ^ dIn[17] ^ dIn[18] ^ dIn[19] ^ dIn[20] ^ dIn[21] ^ dIn[23] ^ dIn[24] ^ dIn[27] ^ dIn[29] ^ dIn[30] ^ dIn[31];
1387
1388 crc_r[8] = crc_s[1] ^ crc_s[2] ^ crc_s[5] ^ crc_s[7] ^ crc_s[8] ^ dIn[1] ^ dIn[2] ^ dIn[4] ^ dIn[5] ^ dIn[6] ^ dIn[7] ^ dIn[8] ^ dIn[9] ^ dIn[10] ^ dIn[14] ^ dIn[17] ^ dIn[18] ^ dIn[19] ^ dIn[20] ^ dIn[21] ^ dIn[22] ^ dIn[24] ^ dIn[25] ^ dIn[28] ^ dIn[30] ^ dIn[31];
1389
1390 }
1391
1392 if ( reverse == 1){
1393 for (int i = 0; i < 9; i++) {
1394 crc_word = crc_word | (crc_r[8-i] << i) ;
1395 }
1396 }
1397 else {
1398 for(int i = 0; i < 9; i++ ){
1399 crc_word = crc_word | (crc_r[i] << i);
1400 }
1401 }
1402 return crc_word;
1403}
1404
1405
1406uint32_t gFexInputByteStreamTool::crc9d23(uint32_t inword, uint32_t in_crc, int reverse ) const{
1407
1408 int mask = 0x00000001;
1409 //#dIn is a '23-bit input word'
1410 std::array<uint32_t, 23> dIn;
1411
1412 std::array<uint32_t, 9> crc_r;
1413 std::array<uint32_t, 9> crc_in_s;
1414
1415 crc_r.fill(1);
1416 crc_in_s.fill(1);
1417
1418 int crc_word = 0x000;
1419
1420 //32-bit word crc calculation
1421
1422 if (reverse == 1) {
1423 for(int i = 0; i < 23;i++){
1424 dIn[22-i] = ( inword & (mask << i));
1425 dIn[22-i] = ( dIn[22-i] >> i);
1426 }
1427 for(int i = 0; i < 9;i++){
1428 crc_in_s[8-i] = ( in_crc & (mask << i) );
1429 crc_in_s[8-i] = ( crc_in_s[8-i] >> i );
1430 }
1431 }
1432 else{
1433 for(int i = 0; i < 23; i++) {
1434 dIn[i] = ( inword & (mask << i) );
1435 dIn[i] = (dIn[i] >> i);
1436 }
1437 for(int i=0; i<9; i++){
1438 crc_in_s[i] = ( in_crc & (mask << i));
1439 crc_in_s[i] = (crc_in_s[i] >> i);
1440 }
1441 }
1442
1443 crc_r[0] = crc_in_s[1] ^ crc_in_s[4] ^ crc_in_s[5] ^ crc_in_s[6] ^ crc_in_s[7] ^ crc_in_s[8] ^ dIn[0] ^ dIn[2] ^ dIn[3] ^ dIn[5] ^ dIn[6] ^ dIn[7] ^ dIn[8] ^ dIn[9] ^ dIn[10] ^ dIn[11] ^ dIn[15] ^ dIn[18] ^ dIn[19] ^ dIn[20] ^ dIn[21] ^ dIn[22];
1444 crc_r[1] = crc_in_s[1] ^ crc_in_s[2] ^ crc_in_s[4] ^ dIn[0] ^ dIn[1] ^ dIn[2] ^ dIn[4] ^ dIn[5] ^ dIn[12] ^ dIn[15] ^ dIn[16] ^ dIn[18];
1445 crc_r[2] = crc_in_s[2] ^ crc_in_s[3] ^ crc_in_s[5] ^ dIn[1] ^ dIn[2] ^ dIn[3] ^ dIn[5] ^ dIn[6] ^ dIn[13] ^ dIn[16] ^ dIn[17] ^ dIn[19];
1446 crc_r[3] = crc_in_s[0] ^ crc_in_s[1] ^ crc_in_s[3] ^ crc_in_s[5] ^ crc_in_s[7] ^ crc_in_s[8] ^ dIn[0] ^ dIn[4] ^ dIn[5] ^ dIn[8] ^ dIn[9] ^ dIn[10] ^ dIn[11] ^ dIn[14] ^ dIn[15] ^ dIn[17] ^ dIn[19] ^ dIn[21] ^ dIn[22];
1447 crc_r[4] = crc_in_s[2] ^ crc_in_s[5] ^ crc_in_s[7] ^ dIn[0] ^ dIn[1] ^ dIn[2] ^ dIn[3] ^ dIn[7] ^ dIn[8] ^ dIn[12] ^ dIn[16] ^ dIn[19] ^ dIn[21];
1448 crc_r[5] = crc_in_s[1] ^ crc_in_s[3] ^ crc_in_s[4] ^ crc_in_s[5] ^ crc_in_s[7] ^ dIn[0] ^ dIn[1] ^ dIn[4] ^ dIn[5] ^ dIn[6] ^ dIn[7] ^ dIn[10] ^ dIn[11] ^ dIn[13] ^ dIn[15] ^ dIn[17] ^ dIn[18] ^ dIn[19] ^ dIn[21];
1449 crc_r[6] = crc_in_s[0] ^ crc_in_s[1] ^ crc_in_s[2] ^ crc_in_s[7] ^ dIn[0] ^ dIn[1] ^ dIn[3] ^ dIn[9] ^ dIn[10] ^ dIn[12] ^ dIn[14] ^ dIn[15] ^ dIn[16] ^ dIn[21];
1450 crc_r[7] = crc_in_s[2] ^ crc_in_s[3] ^ crc_in_s[4] ^ crc_in_s[5] ^ crc_in_s[6] ^ crc_in_s[7] ^ dIn[0] ^ dIn[1] ^ dIn[3] ^ dIn[4] ^ dIn[5] ^ dIn[6] ^ dIn[7] ^ dIn[8] ^ dIn[9] ^ dIn[13] ^ dIn[16] ^ dIn[17] ^ dIn[18] ^ dIn[19] ^ dIn[20] ^ dIn[21];
1451 crc_r[8] = crc_in_s[0] ^ crc_in_s[3] ^ crc_in_s[4] ^ crc_in_s[5] ^ crc_in_s[6] ^ crc_in_s[7] ^ crc_in_s[8] ^ dIn[1] ^ dIn[2] ^ dIn[4] ^ dIn[5] ^ dIn[6] ^ dIn[7] ^ dIn[8] ^ dIn[9] ^ dIn[10] ^ dIn[14] ^ dIn[17] ^ dIn[18] ^ dIn[19] ^ dIn[20] ^ dIn[21] ^ dIn[22];
1452
1453 crc_word = 0x000;
1454 if (reverse == 1){
1455 for(int i = 0; i < 9; i++) {
1456 crc_word = ( crc_word | (crc_r[8-i] << i));
1457 }
1458 }
1459 else{
1460 for(int i = 0; i < 9; i++) {
1461 crc_word = ( crc_word | (crc_r[i] << i) );
1462 }
1463 }
1464 return (crc_word);
1465}
1466
1467void gFexInputByteStreamTool::undoMLE(int &datumPtr ) const{
1468 // limit input to 12 bits to avoid accidental sign extension
1469 int din = (0x00000FFF & datumPtr );
1470 // map all special cases to zero for now
1471 // limit negative values
1472 if( (din > 0) && ( din < 962 ) ) din = 962;
1473 //zeroZero
1474 if( din == 0) din = 0x4EE;
1475
1476 int dout = 0;
1477
1478 int FPGA_CONVLIN_TH1 = 5;
1479 int FPGA_CONVLIN_TH2 = 749;
1480 int FPGA_CONVLIN_TH3 = 1773;
1481 int FPGA_CONVLIN_TH4 = 2541;
1482 int FPGA_CONVLIN_TH5 = 4029;
1483 int FPGA_CONVLIN_TH6 = 4062;
1484
1485 //These variables are unused
1486 //int FPGA_CONVLIN_OF0 = -5072;
1487 //int FPGA_CONVLIN_OF1 = -2012;
1488 int FPGA_CONVLIN_OF2 = -1262;
1489 int FPGA_CONVLIN_OF3 = -3036;
1490 int FPGA_CONVLIN_OF4 = -8120;
1491 int FPGA_CONVLIN_OF5 = -4118720;
1492
1493 int oth0 = 0;
1494 int oth1 = 0;
1495 int oth2 = 0;
1496 int oth3 = 0;
1497 int oth4 = 0;
1498 int oth5 = 0;
1499 int oth6 = 0;
1500 //these variables are unused
1501 //int r1shv = 0;
1502 //int r2shv = 0;
1503 int r3shv = 0;
1504 int r4shv = 0;
1505 int r5shv = 0;
1506 int r6shv = 0;
1507 // int trxv = 0;
1508
1509
1510 unsigned int r3conv = 0;
1511 unsigned int r4conv = 0;
1512 unsigned int r5conv = 0;
1513 unsigned int r6conv = 0;
1514 // int r3offs = 0;
1515
1516 //r1shv = ((din & 0x0000007F) << 9 ) & 0x0000FE00 ;
1517 //r2shv = ((din & 0x00000FFF) << 1 ) & 0x00001FFE ;
1518 r3shv = (din & 0x00000FFF) ;
1519 r4shv = ((din & 0x00000FFF) << 1 ) & 0x00001FFE ;
1520 r5shv = ((din & 0x00000FFF) << 2 ) & 0x00003FFC ;
1521 r6shv = ((din & 0x00000FFF) << 10 ) & 0x003FFC00 ;
1522
1523 //r1conv = r1shv + FPGA_CONVLIN_OF0;
1524 //r2conv = r2shv + FPGA_CONVLIN_OF1;
1525 r3conv = r3shv + FPGA_CONVLIN_OF2;
1526 r4conv = r4shv + FPGA_CONVLIN_OF3;
1527 r5conv = r5shv + FPGA_CONVLIN_OF4;
1528 r6conv = r6shv + FPGA_CONVLIN_OF5;
1529
1530 if( din > 0 ) {
1531 oth0 = 1;
1532 }
1533 else{
1534 oth0 = 0;
1535 }
1536 if ( din > FPGA_CONVLIN_TH1 ){
1537 oth1 = 1;
1538 }
1539 else{
1540 oth1 = 0;
1541 }
1542 if ( din > FPGA_CONVLIN_TH2 ){
1543 oth2 = 1;
1544 }else{
1545 oth2 = 0;
1546 }
1547 if ( din > FPGA_CONVLIN_TH3 ){
1548 oth3 = 1;
1549 }else{
1550 oth3 = 0;
1551 }
1552 if ( din > FPGA_CONVLIN_TH4 ){
1553 oth4 = 1;
1554 }else{
1555 oth4 = 0;
1556 }
1557 if ( din > FPGA_CONVLIN_TH5 ){
1558 oth5 = 1;
1559 }
1560 else{
1561 oth5 = 0;
1562 }
1563 if ( din > FPGA_CONVLIN_TH6 ){
1564 oth6 = 1;
1565 }
1566 else{
1567 oth6 = 0;
1568 }
1569
1570
1571 // divide by 2 to 50 MeV LSB
1572
1573 if( (! oth0) & (! oth1 ) & (! oth2 ) & (! oth3 ) & (! oth4 ) & (! oth5 ) & (! oth6 ) ) {
1574 dout = 0;
1575 }
1576 /* These cases are logically unreachable, given preceding conditions
1577 else if( ( oth0) & (! oth1 ) & (! oth2 ) & (! oth3 ) & (! oth4 ) & (! oth5 ) & (! oth6 ) ) {
1578 dout = r1conv >>1;
1579 }
1580 else if( ( oth0) & ( oth1 ) & (! oth2 ) & (! oth3 ) & (! oth4 ) & (! oth5 ) & (! oth6 ) ) {
1581 dout = r2conv >>1;
1582 }
1583 */
1584 else if( ( oth0) & ( oth1 ) & ( oth2 ) & (! oth3 ) & (! oth4 ) & (! oth5 ) & (! oth6 ) ) {
1585 dout = r3conv >>1;
1586 }
1587 else if( ( oth0) & ( oth1 ) & ( oth2 ) & ( oth3 ) & (! oth4 ) & (! oth5 ) & (! oth6 ) ) {
1588 dout = r4conv >>1;
1589 }
1590 else if( ( oth0) & ( oth1 ) & ( oth2 ) & ( oth3 ) & ( oth4 ) & (! oth5 ) & (! oth6 ) ) {
1591 dout = r5conv >>1;
1592 }
1593 else if( ( oth0) & ( oth1 ) & ( oth2 ) & ( oth3 ) & ( oth4 ) & ( oth5 ) & (! oth6 ) ) {
1594 dout = r6conv >>1;
1595 }
1596 else if( ( oth0) & ( oth1 ) & ( oth2 ) & ( oth3 ) & ( oth4 ) & ( oth5 ) & ( oth6 ) ) {
1597 dout = 0;
1598 }
1599 /* logically unreachable
1600 else {
1601 dout = 0;
1602 }
1603 */
1604 signExtend(&dout,15);
1605
1606 datumPtr = dout;
1607}
1608
1609
1610void gFexInputByteStreamTool::getEtaPhi ( float &Eta, float &Phi, int iEta, int iPhi, int gFEXtowerID) const{
1611
1612 float s_centralPhiWidth = (2*M_PI)/32; //In central region, gFex has 32 bins in phi
1613 float s_forwardPhiWidth = (2*M_PI)/16; //In forward region, gFex has 16 bins in phi (before rearranging bins)
1614
1615 const std::vector<float> s_EtaCenter = { -4.5, -3.8, -3.38, -3.18, -3.15, -3,
1616 -2.8, -2.6, -2.35, -2.1, -1.9, -1.7, -1.5, -1.3, -1.1, -0.9,
1617 -0.7, -0.5, -0.3, -0.1, 0.1, 0.3, 0.5, 0.7, 0.9, 1.1,
1618 1.3, 1.5, 1.7, 1.9, 2.1, 2.35, 2.6, 2.8, 3.0,
1619 3.15, 3.18, 3.38, 3.8, 4.5};
1620
1621 // Transform Eta and Phi indices for the most forward towers into the "original" indices,
1622 // as before rearranging the towers such that the forward region is 12(ieta)x32(iphi).
1623 // The FPGA-C has now the same format (12*32) as FPGA-A and FPGA-B.
1624 // This is the result of a transformation in the firmware.
1625 // Note that for the most forward towers, the Phi index and Eta index have been considered accordingly,
1626 // so in order to get the correct float values of Phi and Eta we need to retrieve the "original" indices.
1627 int towerID_base = 20000;
1628 int iEtaOld=0, iPhiOld=0;
1629
1630 if (iEta == 2){
1631 if (iPhi == ((gFEXtowerID - towerID_base)/24)*2){
1632 iEtaOld = 0;
1633 iPhiOld = iPhi/2;
1634 }
1635 if (iPhi == (((gFEXtowerID - towerID_base - 12)/24)*2) + 1){
1636 iEtaOld = 1;
1637 iPhiOld = (iPhi-1)/2;
1638 }
1639 }
1640
1641 else if (iEta == 3){
1642 if (iPhi == ((gFEXtowerID - towerID_base - 1)/24)*2){
1643 iEtaOld = 2;
1644 iPhiOld = iPhi/2;
1645 }
1646 if (iPhi == (((gFEXtowerID - towerID_base - 13)/24)*2) + 1){
1647 iEtaOld = 3;
1648 iPhiOld = (iPhi-1)/2;
1649 }
1650 }
1651
1652 else if (iEta == 36){
1653 if (iPhi == (((gFEXtowerID - towerID_base - 22)/24)*2) + 1){
1654 iEtaOld = 36;
1655 iPhiOld = (iPhi-1)/2;
1656 }
1657 if (iPhi == ((gFEXtowerID - towerID_base - 10)/24)*2){
1658 iEtaOld = 37;
1659 iPhiOld = iPhi/2;
1660 }
1661 }
1662
1663 else if (iEta == 37){
1664 if (iPhi == (((gFEXtowerID - towerID_base - 23)/24)*2) + 1){
1665 iEtaOld = 38;
1666 iPhiOld = (iPhi-1)/2;
1667 }
1668 if (iPhi == ((gFEXtowerID - towerID_base - 11)/24)*2){
1669 iEtaOld = 39;
1670 iPhiOld = iPhi/2;
1671 }
1672 }
1673
1674 else {
1675 iEtaOld = iEta;
1676 iPhiOld = iPhi;
1677 }
1678
1679 Eta = s_EtaCenter[iEtaOld];
1680
1681 float Phi_gFex = -99;
1682
1683 if (( iEtaOld <= 3 ) || ( (iEtaOld >= 36) )){
1684 Phi_gFex = ( (iPhiOld * s_forwardPhiWidth) + s_forwardPhiWidth/2);
1685 }
1686 else {
1687 Phi_gFex = ( (iPhiOld * s_centralPhiWidth) + s_centralPhiWidth/2);
1688 }
1689
1690 if (Phi_gFex < M_PI) {
1691 Phi = Phi_gFex;
1692 }
1693 else {
1694 Phi = (Phi_gFex - 2*M_PI);
1695 }
1696}
1697
1698void gFexInputByteStreamTool::signExtend(int *xptr, int upto) const{
1699
1700 // sign extend x to 32 bits assuming a hardware word length upto+1 bits (e.g. for 16 bit word upto should be 15 as in firmware)
1701 // xptr pointer to input datum
1702 // word length in hardware
1703 int x = *xptr;
1704 //printf("before %x \n", x);
1705 //printf("masks %x %x \n", (0x00000001<<upto) , (0xFFFFFFFF<<(upto+1)) );
1706 if( x & (0x00000001<<upto) ) {
1707 x = ( x | (0xFFFFFFFF<<(upto+1)) );
1708 } else {
1709 // for now assume 17 bits -- but could be up to 18 bits
1710 x = ( x & 0x000FFFF);
1711 }
1712 *xptr = x;
1713
1714}
1715
1716void gFexInputByteStreamTool::gtCalib(gtFPGA &gtf, int towerLSB, int fpga, unsigned int offset ) const{
1717 // does calibration of input gTowers according the fpga and the
1718
1719 int ABCrows = gtf.size();
1720 int ABcolumns = gtf[0].size();
1721 // check on fpga number to fool compiler into not giving a warning.
1722 // eventually will use for possilbe look up table modification
1723 if(fpga <0 || fpga >2 ) printf("*E: gtCalib FPGA number %d out of range\n",fpga);
1724
1725 // regular towers 200 MeV towers
1726 // for now just do and undo offset and simulate tuncation effect
1727
1728 for(int irow=0; irow<ABCrows; irow++){
1729 for( int icolumn=0; icolumn<ABcolumns; icolumn++){
1730
1731 // 200 MEV Towers
1732 if( towerLSB == 200 ) {
1733 gtf[irow][icolumn] = gtf[irow][icolumn] + offset;
1734
1735 if( gtf[irow][icolumn] > 2047 ) {
1736 gtf[irow][icolumn] = 2047;
1737 } else if( gtf[irow][icolumn] < 0 ){
1738 gtf[irow][icolumn] = 0;
1739 }
1740 gtf[irow][icolumn] = gtf[irow][icolumn] - offset;
1741
1742 } else {
1743
1744 gtf[irow][icolumn] = gtf[irow][icolumn] + offset;
1745
1746 if( gtf[irow][icolumn] > 1023 ){
1747 gtf[irow][icolumn] = 1023;
1748 } else if ( gtf[irow][icolumn] < 0 ){
1749 gtf[irow][icolumn] = 0;
1750 }
1751 gtf[irow][icolumn] = gtf[irow][icolumn] - offset;
1752
1753 }
1754 }
1755 }
1756}
1757
1758StatusCode gFexInputByteStreamTool::ReadFibersfromFile(const std::string& fileName) {
1759 // opening file with ifstream
1760 std::ifstream file(fileName);
1761
1762 if (!file.is_open()) {
1763 ATH_MSG_ERROR("Could not open file:" << fileName);
1764 return StatusCode::FAILURE;
1765 }
1766 std::string line;
1767 // loading the mapping information
1768 while (std::getline(file, line)) {
1769 // removing the header of the file (it is just information!)
1770 if (line[0] == '#') continue;
1771
1772 // Splitting line in different substrings
1773 std::stringstream oneLine(line);
1774 // reading elements
1775 std::vector<float> elements;
1776 std::string element;
1777 while (std::getline(oneLine, element, ' ')) {
1778 elements.push_back(std::stof(element));
1779 }
1780
1781 // It should have 5 elements
1782 // ordered as: towerID fpga source eta phi
1783
1784 if (elements.size() != 5) {
1785 ATH_MSG_ERROR(
1786 "Unexpected number of elements (5 expected) in file: " << fileName);
1787 return StatusCode::FAILURE;
1788 }
1789
1790 // building array of <fpga, eta, phi, source>
1791 std::array<float, 4> aux_arr{{elements.at(1), elements.at(3),
1792 elements.at(4), elements.at(2)}};
1793
1794 // filling the map, key is towerID
1795 m_Firm2Tower_map[elements.at(0)] = aux_arr;
1796 }
1797
1798 file.close();
1799
1800 return StatusCode::SUCCESS;
1801 }
1802
1804StatusCode gFexInputByteStreamTool::convertToBS(std::vector<WROBF*>& /*vrobf*/, const EventContext& /*eventContext*/) {
1805
1806 return StatusCode::SUCCESS;
1807}
1808
1809void gFexInputByteStreamTool::printError(const std::string& location, const std::string& title, MSG::Level type, const std::string& detail) const{
1810
1811 if(m_UseMonitoring){
1812 Monitored::Group(m_monTool,
1813 Monitored::Scalar("gfexDecoderErrorLocation",location.empty() ? std::string("UNKNOWN") : location),
1814 Monitored::Scalar("gfexDecoderErrorTitle" ,title.empty() ? std::string("UNKNOWN") : title)
1815 );
1816 }
1817 else {
1818 msg() << type << detail << endmsg;
1819 }
1820}
M_PI
#define M_PI
Definition ActiveFraction.h:11
endmsg
#define endmsg
Definition AnalysisConfig_Ntuple.cxx:63
ATH_CHECK
#define ATH_CHECK
Evaluate an expression and check for errors.
Definition AthCheckMacros.h:40
ATH_MSG_ERROR
#define ATH_MSG_ERROR(x)
Definition AthMsgStreamMacros.h:33
ATH_MSG_INFO
#define ATH_MSG_INFO(x)
Definition AthMsgStreamMacros.h:31
ATH_MSG_DEBUG
#define ATH_MSG_DEBUG(x)
Definition AthMsgStreamMacros.h:29
ROBF
OFFLINE_FRAGMENTS_NAMESPACE_WRITE::ROBFragment ROBF
Definition ByteStreamMergeOutputSvc.cxx:16
printError
void printError()
Definition CalibrateIBL.cxx:1359
x
#define x
DataVector::back
const T * back() const
Access the last element in the collection as an rvalue.
DataVector::push_back
value_type push_back(value_type pElem)
Add an element to the end of the collection.
Monitored::Group
Group of local monitoring quantities and retain correlation when filling histograms
Definition MonitoredGroup.h:53
Monitored::Scalar
Declare a monitored scalar variable.
Definition MonitoredScalar.h:34
PathResolver::find_calib_file
static std::string find_calib_file(const std::string &logical_file_name)
Definition PathResolver.cxx:272
SG::VarHandleBase::key
virtual const std::string & key() const override final
Return the StoreGate ID for the referenced object.
Definition AthToolSupport/AsgDataHandles/Root/VarHandleBase.cxx:64
SG::WriteHandle::record
StatusCode record(std::unique_ptr< T > data)
Record a const object to the store.
gFexInputByteStreamTool::signExtend
virtual void signExtend(int *xptr, int upto) const
Definition gFexInputByteStreamTool.cxx:1698
gFexInputByteStreamTool::m_Firm2Tower_map
std::unordered_map< unsigned int, std::array< float, 4 > > m_Firm2Tower_map
Definition gFexInputByteStreamTool.h:81
gFexInputByteStreamTool::m_gTowersWriteKey
SG::WriteHandleKey< xAOD::gFexTowerContainer > m_gTowersWriteKey
Definition gFexInputByteStreamTool.h:87
gFexInputByteStreamTool::gtReconstructABC
virtual void gtReconstructABC(int XFPGA, const gfiber &Xfiber, int Xin, gtFPGA &XgtF, gtFPGA &Xgt, int *BCIDptr, int do_lconv, const std::array< int, gPos::MAX_FIBERS > &XMPD_NFI, const std::array< int, gPos::MAX_FIBERS > &XCALO_TYPE, const gCaloTwr &XMPD_GTRN_ARR, const gType &XMPD_DSTRT_ARR, gTypeChar XMPD_DTYP_ARR, const std::array< int, gPos::MAX_FIBERS > &XMSK, gtFPGA &Xsatur, std::array< int,(gPos::AB_FIBERS *gPos::MAX_E_FIELDS)> &FiberTower, std::array< int,(gPos::AB_FIBERS *gPos::MAX_E_FIELDS)> &FiberTowerSatur) const
Definition gFexInputByteStreamTool.cxx:468
gFexInputByteStreamTool::m_gTowersReadKey
SG::ReadHandleKey< xAOD::gFexTowerContainer > m_gTowersReadKey
Definition gFexInputByteStreamTool.h:92
gFexInputByteStreamTool::crc9d23
uint32_t crc9d23(uint32_t inword, uint32_t in_crc, int reverse) const
Definition gFexInputByteStreamTool.cxx:1406
gFexInputByteStreamTool::b_gtrx_map
virtual void b_gtrx_map(const gfiber &inputData, gfiber &jf_lar_rx_data) const
Definition gFexInputByteStreamTool.cxx:426
gFexInputByteStreamTool::gFexInputByteStreamTool
gFexInputByteStreamTool(const std::string &type, const std::string &name, const IInterface *parent)
Definition gFexInputByteStreamTool.cxx:25
gFexInputByteStreamTool::m_robIds
Gaudi::Property< std::vector< uint32_t > > m_robIds
{map index(towerid), {fpga, eta, phi, source}}
Definition gFexInputByteStreamTool.h:84
gFexInputByteStreamTool::gfiber
std::array< std::array< uint32_t, 7 >, 100 > gfiber
Definition gFexInputByteStreamTool.h:42
gFexInputByteStreamTool::c_gtrx_map
virtual void c_gtrx_map(const gfiber &inputData, gfiber &outputData) const
Definition gFexInputByteStreamTool.cxx:447
gFexInputByteStreamTool::convertFromBS
virtual StatusCode convertFromBS(const std::vector< const OFFLINE_FRAGMENTS_NAMESPACE::ROBFragment * > &vrobf, const EventContext &eventContext) const override
BS->xAOD conversion.
Definition gFexInputByteStreamTool.cxx:55
gFexInputByteStreamTool::a_gtrx_map
virtual void a_gtrx_map(const gfiber &inputData, gfiber &jf_lar_rx_data) const
Definition gFexInputByteStreamTool.cxx:405
gFexInputByteStreamTool::initialize
virtual StatusCode initialize() override
Definition gFexInputByteStreamTool.cxx:30
gFexInputByteStreamTool::gtFPGA
std::array< std::array< int, 12 >, 32 > gtFPGA
Definition gFexInputByteStreamTool.h:44
gFexInputByteStreamTool::gCaloTwr
std::array< std::array< int, 16 >, 100 > gCaloTwr
Definition gFexInputByteStreamTool.h:46
gFexInputByteStreamTool::gtCalib
virtual void gtCalib(gtFPGA &gtf, int towerLSB, int fpga, unsigned int offset) const
Definition gFexInputByteStreamTool.cxx:1716
gFexInputByteStreamTool::undoMLE
virtual void undoMLE(int &datumPtr) const
Definition gFexInputByteStreamTool.cxx:1467
gFexInputByteStreamTool::m_gTowers200WriteKey
SG::WriteHandleKey< xAOD::gFexTowerContainer > m_gTowers200WriteKey
Definition gFexInputByteStreamTool.h:89
gFexInputByteStreamTool::gSatur
std::array< std::array< int, 8 >, 100 > gSatur
Definition gFexInputByteStreamTool.h:47
gFexInputByteStreamTool::ReadFibersfromFile
StatusCode ReadFibersfromFile(const std::string &)
Definition gFexInputByteStreamTool.cxx:1758
gFexInputByteStreamTool::m_monTool
ToolHandle< GenericMonitoringTool > m_monTool
Definition gFexInputByteStreamTool.h:72
gFexInputByteStreamTool::printError
void printError(const std::string &location, const std::string &title, MSG::Level type, const std::string &detail) const
Definition gFexInputByteStreamTool.cxx:1809
gFexInputByteStreamTool::m_gTowers50WriteKey
SG::WriteHandleKey< xAOD::gFexTowerContainer > m_gTowers50WriteKey
Definition gFexInputByteStreamTool.h:88
gFexInputByteStreamTool::gTypeChar
std::array< std::array< char, 20 >, 4 > gTypeChar
Definition gFexInputByteStreamTool.h:50
gFexInputByteStreamTool::convertToBS
virtual StatusCode convertToBS(std::vector< OFFLINE_FRAGMENTS_NAMESPACE_WRITE::ROBFragment * > &vrobf, const EventContext &eventContext) override
xAOD->BS conversion
Definition gFexInputByteStreamTool.cxx:1804
gFexInputByteStreamTool::gType
std::array< std::array< int, 20 >, 4 > gType
Definition gFexInputByteStreamTool.h:49
gFexInputByteStreamTool::crc9d32
virtual int crc9d32(const std::array< uint32_t, 6 > &inWords, int numWords, int reverse) const
Definition gFexInputByteStreamTool.cxx:1342
gFexInputByteStreamTool::gFields
std::array< std::array< int, 20 >, 100 > gFields
Definition gFexInputByteStreamTool.h:45
gFexInputByteStreamTool::m_FiberMapping
Gaudi::Property< std::string > m_FiberMapping
Definition gFexInputByteStreamTool.h:76
gFexInputByteStreamTool::getEtaPhi
virtual void getEtaPhi(float &Eta, float &Phi, int iEta, int iPhi, int gFEXtowerID) const
Definition gFexInputByteStreamTool.cxx:1610
xAOD::gFexTower_v1::initialize
void initialize(const uint8_t IEta, const uint8_t IPhi)
setter for the above
Definition gFexTower_v1.cxx:23
WROBF
OFFLINE_FRAGMENTS_NAMESPACE_WRITE::ROBFragment WROBF
Definition eFexByteStreamTool.cxx:27
LVL1::gFEXPos::AMPD_GTRN_ARR
constexpr std::array< std::array< int, 16 >, 100 > AMPD_GTRN_ARR
Definition gFexPos.h:124
LVL1::gFEXPos::CMPD_DTYP_ARR
constexpr std::array< std::array< char, 20 >, 4 > CMPD_DTYP_ARR
Definition gFexPos.h:494
LVL1::gFEXPos::CMPD_NFI
constexpr std::array< int, 100 > CMPD_NFI
Definition gFexPos.h:375
LVL1::gFEXPos::CMPD_DSTRT_ARR
constexpr std::array< std::array< int, 20 >, 4 > CMPD_DSTRT_ARR
Definition gFexPos.h:486
LVL1::gFEXPos::GTRX_MAP_A_IND
constexpr std::array< unsigned int, 80 > GTRX_MAP_A_IND
Definition gFexPos.h:74
LVL1::gFEXPos::C_FIBERS
constexpr int C_FIBERS
Definition gFexPos.h:60
LVL1::gFEXPos::AMPD_DSTRT_ARR
constexpr std::array< std::array< int, 20 >, 4 > AMPD_DSTRT_ARR
Definition gFexPos.h:208
LVL1::gFEXPos::MAX_E_FIELDS
constexpr int MAX_E_FIELDS
Definition gFexPos.h:61
LVL1::gFEXPos::FPGA_B_INPUT_HEADER
constexpr uint32_t FPGA_B_INPUT_HEADER
Definition gFexPos.h:55
LVL1::gFEXPos::FPGA_C_INPUT_HEADER
constexpr uint32_t FPGA_C_INPUT_HEADER
Definition gFexPos.h:56
LVL1::gFEXPos::CMPD_GTRN_ARR
constexpr std::array< std::array< int, 16 >, 100 > CMPD_GTRN_ARR
Definition gFexPos.h:397
LVL1::gFEXPos::FPGA_A_INPUT_HEADER
constexpr uint32_t FPGA_A_INPUT_HEADER
Definition gFexPos.h:54
LVL1::gFEXPos::AB_COLUMNS
constexpr int AB_COLUMNS
Definition gFexPos.h:64
LVL1::gFEXPos::CMSK
constexpr std::array< int, 100 > CMSK
Definition gFexPos.h:507
LVL1::gFEXPos::ACALO_TYPE
constexpr std::array< int, 100 > ACALO_TYPE
Definition gFexPos.h:114
LVL1::gFEXPos::ABC_ROWS
constexpr int ABC_ROWS
Definition gFexPos.h:63
LVL1::gFEXPos::AMPD_DTYP_ARR
constexpr std::array< std::array< char, 20 >, 4 > AMPD_DTYP_ARR
Definition gFexPos.h:216
LVL1::gFEXPos::BMPD_DTYP_ARR
constexpr std::array< std::array< char, 20 >, 4 > BMPD_DTYP_ARR
Definition gFexPos.h:351
LVL1::gFEXPos::BCALO_TYPE
constexpr std::array< int, 100 > BCALO_TYPE
Definition gFexPos.h:249
LVL1::gFEXPos::GTRX_MAP_B_IND
constexpr std::array< unsigned int, 80 > GTRX_MAP_B_IND
Definition gFexPos.h:83
LVL1::gFEXPos::BMPD_DSTRT_ARR
constexpr std::array< std::array< int, 20 >, 4 > BMPD_DSTRT_ARR
Definition gFexPos.h:342
LVL1::gFEXPos::W280
constexpr int W280
Definition gFexPos.h:66
LVL1::gFEXPos::CCALO_TYPE
constexpr std::array< int, 100 > CCALO_TYPE
Definition gFexPos.h:389
LVL1::gFEXPos::AMSK
constexpr std::array< int, 100 > AMSK
Definition gFexPos.h:233
LVL1::gFEXPos::AMPD_NFI
constexpr std::array< int, 100 > AMPD_NFI
Definition gFexPos.h:105
LVL1::gFEXPos::GTRX_MAP_C_IND
constexpr std::array< unsigned int, 50 > GTRX_MAP_C_IND
Definition gFexPos.h:92
LVL1::gFEXPos::BMPD_NFI
constexpr std::array< int, 100 > BMPD_NFI
Definition gFexPos.h:241
LVL1::gFEXPos::BMPD_GTRN_ARR
constexpr std::array< std::array< int, 16 >, 100 > BMPD_GTRN_ARR
Definition gFexPos.h:257
LVL1::gFEXPos::AB_FIBERS
constexpr int AB_FIBERS
Definition gFexPos.h:59
LVL1::gFEXPos::BMSK
constexpr std::array< int, 100 > BMSK
Definition gFexPos.h:367
OFFLINE_FRAGMENTS_NAMESPACE_WRITE::ROBFragment
eformat::write::ROBFragment ROBFragment
Definition RawEvent.h:33
OFFLINE_FRAGMENTS_NAMESPACE::ROBFragment
eformat::ROBFragment< PointerType > ROBFragment
Definition RawEvent.h:27
index
Definition index.py:1
xAOD::gFexTowerContainer
gFexTowerContainer_v1 gFexTowerContainer
Define the latest version of the TriggerTower container.
Definition gFexTowerContainer.h:14
type
msg
MsgStream & msg
Definition testRead.cxx:32
file
TFile * file
Definition tile_monitor.h:29
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