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FPGADataFormatTool Class Reference

#include <FPGADataFormatTool.h>

Inheritance diagram for FPGADataFormatTool:
Collaboration diagram for FPGADataFormatTool:

Public Member Functions

virtual StatusCode initialize () override
 
virtual StatusCode convertPixelHitsToFPGADataFormat (const PixelRDO_Container &pixelRDO, std::vector< uint64_t > &encodedData, const std::vector< IdentifierHash > &hashList, const EventContext &ctx) const override
 Covert the Pixel RDOs to the test vector format as requited by FPGA EF tracking alogrithms. More...
 
virtual StatusCode convertStripHitsToFPGADataFormat (const SCT_RDO_Container &stripRDO, std::vector< uint64_t > &encodedData, const std::vector< IdentifierHash > &hashList, const EventContext &ctx) const override
 Covert the Strip RDOs to the test vector format as requited by FPGA EF tracking alogrithms. More...
 
virtual StatusCode convertFPGATracksToFPGADataFormat (const FPGATrackSimTrackCollection *tracks, std::vector< uint64_t > &encodedData, const EventContext &ctx) const override
 
virtual StatusCode convertFPGASliceToFPGADataFormat (const FPGATrackSimHitCollection *hitsInSlices, bool doPixel, bool doStrip, std::vector< uint64_t > &encodedData, const EventContext &ctx) const override
 
virtual StatusCode convertFPGAHitsToFPGADataFormat (const FPGATrackSimHitCollection *allHits, bool doPixel, bool doStrip, std::vector< uint64_t > &encodedData, const EventContext &ctx) const override
 

Private Member Functions

StatusCode convertPixelRDO (const PixelRDO_Container &pixelRDO, std::vector< uint64_t > &encodedData, const std::vector< IdentifierHash > &hashList, const EventContext &ctx) const
 
StatusCode convertStripRDO (const SCT_RDO_Container &stripRDO, std::vector< uint64_t > &encodedData, const std::vector< IdentifierHash > &hashList, const EventContext &ctx) const
 
StatusCode convertFPGATracks (const FPGATrackSimTrackCollection *tracks, std::vector< uint64_t > &encodedData, const EventContext &ctx) const
 
StatusCode convertFPGASlices (const FPGATrackSimHitCollection *hitsInSlices, bool doPixel, bool doStrip, std::vector< uint64_t > &encodedData, const EventContext &ctx) const
 
StatusCode convertFPGAHits (const FPGATrackSimHitCollection *hits, bool doPixel, bool doStrip, std::vector< uint64_t > &encodedData, const EventContext &ctx) const
 
StatusCode fillHeader (std::vector< uint64_t > &encodedData) const
 
StatusCode fillFooter (std::vector< uint64_t > &encodedData) const
 
StatusCode fillModuleHeader (const InDetDD::SiDetectorElement *sielement, std::vector< uint64_t > &encodedData) const
 
void fillHit (const FPGATrackSimHit *hit, bool isLast, bool isLastofSlice, std::vector< uint64_t > &encodedData) const
 

Private Attributes

const PixelID * m_pixelId = nullptr
 
const SCT_ID * m_sctId = nullptr
 
const InDetDD::SiDetectorManager * m_PIX_mgr = nullptr
 
const InDetDD::SiDetectorManager * m_SCT_mgr = nullptr
 

Detailed Description

Definition at line 21 of file FPGADataFormatTool.h.

Member Function Documentation

◆ convertFPGAHits()

StatusCode FPGADataFormatTool::convertFPGAHits ( const FPGATrackSimHitCollection *  hits,
bool  doPixel,
bool  doStrip,
std::vector< uint64_t > &  encodedData,
const EventContext &  ctx 
) const
private

Definition at line 152 of file FPGADataFormatTool.cxx.

158  {
159 
160  ATH_MSG_DEBUG("Encodings Hits: ");
161 
162  // first organize maps with hits group in module
163  std::map<unsigned int, std::vector<const FPGATrackSimHit*> > organizedHits;
164 
165  for (size_t i = 0; i < allHits->size(); i++)
166  {
167  const FPGATrackSimHit& hit = allHits->at(i);
168 
169  if((doPixel && hit.isPixel()) || (doStrip && hit.isStrip()))
170  organizedHits[hit.getIdentifier()].push_back(&hit);
171  }
172 
173  // encode the hits
174  for (const auto& hits: organizedHits)
175  {
176  const auto& firstHit = hits.second[0];
177  auto mod_w1 = FPGADataFormatUtilities::fill_M_HDR_w1 (FPGADataFormatUtilities::M_HDR_FLAG, firstHit->getIdentifier(), firstHit->getIdentifierHash(), 0);
178  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_M_HDR_w1(mod_w1));
179 
180  unsigned int counter = 0;
181  for(const auto& hit: hits.second)
182  {
183  bool isLast = (counter + 1 == hits.second.size());
184  fillHit(hit, isLast, false, encodedData);
185  counter++;
186  }
187  }
188  return StatusCode::SUCCESS;
189 
190 }

◆ convertFPGAHitsToFPGADataFormat()

StatusCode FPGADataFormatTool::convertFPGAHitsToFPGADataFormat ( const FPGATrackSimHitCollection *  allHits,
bool  doPixel,
bool  doStrip,
std::vector< uint64_t > &  encodedData,
const EventContext &  ctx 
) const
overridevirtual

Definition at line 130 of file FPGADataFormatTool.cxx.

135  {
136 
137  // Fill the event header
138  ATH_CHECK(fillHeader(encodedData));
139 
140  // Convert Slices
141  ATH_CHECK(convertFPGAHits(allHits, doPixel, doStrip, encodedData, ctx));
142 
143  // Fill the event footer
144  ATH_CHECK(fillFooter(encodedData));
145 
146 
147  return StatusCode::SUCCESS;
148 }

◆ convertFPGASlices()

StatusCode FPGADataFormatTool::convertFPGASlices ( const FPGATrackSimHitCollection *  hitsInSlices,
bool  doPixel,
bool  doStrip,
std::vector< uint64_t > &  encodedData,
const EventContext &  ctx 
) const
private

Definition at line 82 of file FPGADataFormatTool.cxx.

88  {
89 
90  ATH_MSG_DEBUG("Encoded Slices: ");
91 
92  auto sliceWord_w1 = FPGADataFormatUtilities::fill_SLICE_HDR_w1(FPGADataFormatUtilities::SLICE_HDR_FLAG, 34, 0, 0, 0);
93  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_SLICE_HDR_w1(sliceWord_w1));
94 
95  std::map<unsigned int, std::vector<const FPGATrackSimHit*> > organizedHits;
96 
97  for (size_t i = 0; i < hitsinSlice->size(); i++)
98  {
99  const FPGATrackSimHit& hit = hitsinSlice->at(i);
100 
101  if((doPixel && hit.isPixel()) || (doStrip && hit.isStrip()))
102  organizedHits[hit.getIdentifier()].push_back(&hit);
103  }
104 
105  // encode the hits
106  unsigned int moduleCounter = 0;
107  for (const auto& hits: organizedHits)
108  {
109  const auto& firstHit = hits.second[0];
110  auto mod_w1 = FPGADataFormatUtilities::fill_M_HDR_w1 (FPGADataFormatUtilities::M_HDR_FLAG, firstHit->getIdentifier(), firstHit->getIdentifierHash(), 0);
111  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_M_HDR_w1(mod_w1));
112 
113  unsigned int counter = 0;
114  for(const auto& hit: hits.second)
115  {
116  bool isLast = (counter + 1 == hits.second.size());
117  bool isLastofSlice = isLast && (moduleCounter + 1 == organizedHits.size()); // Since we are only doing once slice at a time
118  fillHit(hit, isLast, isLastofSlice, encodedData);
119  counter++;
120  }
121  moduleCounter++;
122  }
123 
124  return StatusCode::SUCCESS;
125 
126 }

◆ convertFPGASliceToFPGADataFormat()

StatusCode FPGADataFormatTool::convertFPGASliceToFPGADataFormat ( const FPGATrackSimHitCollection *  hitsInSlices,
bool  doPixel,
bool  doStrip,
std::vector< uint64_t > &  encodedData,
const EventContext &  ctx 
) const
overridevirtual

Definition at line 60 of file FPGADataFormatTool.cxx.

65  {
66 
67  // Fill the event header
68  ATH_CHECK(fillHeader(encodedData));
69 
70  // Convert Slices
71  ATH_CHECK(convertFPGASlices(slices, doPixel, doStrip, encodedData, ctx));
72 
73  // Fill the event footer
74  ATH_CHECK(fillFooter(encodedData));
75 
76 
77  return StatusCode::SUCCESS;
78 }

◆ convertFPGATracks()

StatusCode FPGADataFormatTool::convertFPGATracks ( const FPGATrackSimTrackCollection *  tracks,
std::vector< uint64_t > &  encodedData,
const EventContext &  ctx 
) const
private

Definition at line 214 of file FPGADataFormatTool.cxx.

218  {
219 
220  for (const FPGATrackSimTrack& track : *tracks)
221  {
222  int bitmask = 0;
223  for(const auto& hit: track.getFPGATrackSimHits())
224  {
225  bitmask |= 2 << hit.getLayer();
226  }
227 
228  ATH_MSG_DEBUG("Encoded GTrack: ");
229  ATH_MSG_DEBUG("\tetaregion: " << track.getHoughY());
230  ATH_MSG_DEBUG("\tphiregion: " << track.getHoughX());
231  ATH_MSG_DEBUG("\tlayerbitmask: " << bitmask);
232  ATH_MSG_DEBUG("\td0: " << track.getD0());
233  ATH_MSG_DEBUG("\tz0: " << track.getZ0());
234  ATH_MSG_DEBUG("\tqoverpt: " << track.getQOverPt());
235  ATH_MSG_DEBUG("\tphi: " << track.getPhi());
236  ATH_MSG_DEBUG("\teta: " << track.getEta());
237 
238  auto gtrackWord_w1 = FPGADataFormatUtilities::fill_GTRACK_HDR_w1(
239  0xee,
240  0,
241  track.getHoughY(),
242  track.getHoughX(),
243  0,
244  0,
245  0,
246  bitmask);
247  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_GTRACK_HDR_w1(gtrackWord_w1));
248 
249  auto gtrackWord_w2 = FPGADataFormatUtilities::fill_GTRACK_HDR_w2(
250  0,
251  track.getD0(),
252  track.getZ0(),
253  0);
254  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_GTRACK_HDR_w2(gtrackWord_w2));
255 
256  auto gtrackWord_w3 = FPGADataFormatUtilities::fill_GTRACK_HDR_w3(
257  track.getQOverPt(),
258  track.getPhi(),
259  track.getEta(),
260  0);
261  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_GTRACK_HDR_w3(gtrackWord_w3));
262 
263  auto hits = track.getFPGATrackSimHits();
264  hits.erase(
265  std::remove_if(hits.begin(), hits.end(),
266  [](const FPGATrackSimHit& hit) { return !hit.isReal(); }),
267  hits.end());
268 
269  for(unsigned int i = 0 ; i < hits.size(); i++)
270  {
271  const auto& hit = hits[i];
272  bool isLast = (i+1 == hits.size());
273  fillHit(&hit, isLast, false, encodedData);
274  }
275 
276 
277  }
278 
279 
280  return StatusCode::SUCCESS;
281 }

◆ convertFPGATracksToFPGADataFormat()

StatusCode FPGADataFormatTool::convertFPGATracksToFPGADataFormat ( const FPGATrackSimTrackCollection *  tracks,
std::vector< uint64_t > &  encodedData,
const EventContext &  ctx 
) const
overridevirtual

Definition at line 196 of file FPGADataFormatTool.cxx.

199  {
200 
201  // Fill the event header
202  ATH_CHECK(fillHeader(encodedData));
203 
204  // Convert the strip RDO
205  ATH_CHECK(convertFPGATracks(tracks, encodedData, ctx));
206 
207  // Fill the event footer
208  ATH_CHECK(fillFooter(encodedData));
209 
210 
211  return StatusCode::SUCCESS;
212 }

◆ convertPixelHitsToFPGADataFormat()

StatusCode FPGADataFormatTool::convertPixelHitsToFPGADataFormat ( const PixelRDO_Container &  pixelRDO,
std::vector< uint64_t > &  encodedData,
const std::vector< IdentifierHash > &  hashList,
const EventContext &  ctx 
) const
overridevirtual

Covert the Pixel RDOs to the test vector format as requited by FPGA EF tracking alogrithms.

Definition at line 20 of file FPGADataFormatTool.cxx.

24  {
25 
26  // Fill the event header
27  ATH_CHECK(fillHeader(encodedData));
28 
29  // Convert the strip RDO
30  ATH_CHECK(convertPixelRDO(pixelRDO, encodedData, hashList, ctx));
31 
32  // Fill the event footer
33  ATH_CHECK(fillFooter(encodedData));
34 
35 
36  return StatusCode::SUCCESS;
37 }

◆ convertPixelRDO()

StatusCode FPGADataFormatTool::convertPixelRDO ( const PixelRDO_Container &  pixelRDO,
std::vector< uint64_t > &  encodedData,
const std::vector< IdentifierHash > &  hashList,
const EventContext &  ctx 
) const
private

Definition at line 285 of file FPGADataFormatTool.cxx.

290  {
291 
292  bool filledHeader = false;
293  for (const InDetRawDataCollection<PixelRDORawData>* pixel_rdoCollection : pixelRDO)
294  {
295  if (pixel_rdoCollection == nullptr) { continue; }
296 
297  // loop on all RDOs
298  for (const PixelRDORawData* pixelRawData : *pixel_rdoCollection)
299  {
300  Identifier rdoId = pixelRawData->identify();
301  // get the det element from the det element collection
302  const InDetDD::SiDetectorElement* sielement = m_PIX_mgr->getDetectorElement(rdoId);
303  // if hash list has elements, check if the current Si in the list otherwise, continue
304  if(hashList.size() > 0)
305  {
306  if(std::find(hashList.begin(), hashList.end(), sielement->identifyHash()) == hashList.end()) continue;
307  }
308 
309  // Fill the module header
310  if(!filledHeader)
311  {
312  ATH_CHECK(fillModuleHeader(sielement, encodedData));
313  filledHeader = true;
314  }
315 
316  // Get the pixel word
317  auto pixelWord = FPGADataFormatUtilities::fill_PIXEL_EF_RDO (
318  (pixelRawData == pixel_rdoCollection->back()), // last
319  m_pixelId->phi_index(rdoId), // ROW
320  m_pixelId->eta_index(rdoId), // COL
321  pixelRawData->getToT(), // TOT
322  pixelRawData->getLVL1A(), // Lvl!
323  0x0F0F0F // Spare
324  );
325 
326  // Push the word into the vector
327  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_PIXEL_EF_RDO(pixelWord));
328  //}
329  } // end for each RDO in the collection
330 
331  // reset the header
332  filledHeader = false;
333 
334 } // for each pixel RDO collection
335 
336 return StatusCode::SUCCESS;
337 }

◆ convertStripHitsToFPGADataFormat()

StatusCode FPGADataFormatTool::convertStripHitsToFPGADataFormat ( const SCT_RDO_Container &  stripRDO,
std::vector< uint64_t > &  encodedData,
const std::vector< IdentifierHash > &  hashList,
const EventContext &  ctx 
) const
overridevirtual

Covert the Strip RDOs to the test vector format as requited by FPGA EF tracking alogrithms.

Definition at line 39 of file FPGADataFormatTool.cxx.

43  {
44 
45  // Fill the event header
46  ATH_CHECK(fillHeader(encodedData));
47 
48  // Convert the strip RDO
49  ATH_CHECK(convertStripRDO(stripRDO, encodedData, hashList, ctx));
50 
51  // Fill the event footer
52  ATH_CHECK(fillFooter(encodedData));
53 
54  return StatusCode::SUCCESS;
55 }

◆ convertStripRDO()

StatusCode FPGADataFormatTool::convertStripRDO ( const SCT_RDO_Container &  stripRDO,
std::vector< uint64_t > &  encodedData,
const std::vector< IdentifierHash > &  hashList,
const EventContext &  ctx 
) const
private

Definition at line 339 of file FPGADataFormatTool.cxx.

344  {
345  constexpr int MaxChannelinStripRow = 128;
346  long unsigned int stripNumber = 0;
347  bool filledHeader = false;
348 
349  uint64_t packedWord = 0;
350  bool firstClusterFilled = false;
351 
352  for (const InDetRawDataCollection<SCT_RDORawData>* SCT_Collection : stripRDO) {
353  if (SCT_Collection == nullptr) { continue; }
354 
355  std::map<int, bool> firedStrips;
356  std::map<int, const SCT_RDORawData*> firedStripsToRDO;
357 
358  // Preprocess the SCT collection hits to get information for encoding strip in ITK format
359  // All fired strips are stored in a map to get an overview of the full module that should be
360  // used to encode the data into the ITk format.
361  for (const SCT_RDORawData* sctRawData : *SCT_Collection) {
362  const Identifier rdoId = sctRawData->identify();
363  const int baseLineStrip{m_sctId->strip(rdoId)};
364  for (int i = 0; i < sctRawData->getGroupSize(); i++) {
365  firedStrips[baseLineStrip + i] = true;
366  firedStripsToRDO[baseLineStrip + i] = sctRawData;
367  }
368  }
369  // Loop over the fired hits and encode them in the ITk strips hit map
370  // Finds unique hits in the list that can be encoded and don't overlap
371  std::map<int, int> stripEncodingForITK;
372  std::map<int, const SCT_RDORawData* > stripEncodingForITKToRDO;
373  for (const auto& [stripID, fired] : firedStrips) {
374  // Skip strips that have already been used in a cluster
375  if (!fired) continue;
376 
377  // Check the next 3 hits if they exist and have a hit in them
378  std::bitset<3> hitMap;
379  int currChipID = stripID / MaxChannelinStripRow;
380  int maxStripIDForCurrChip = (currChipID + 1) * MaxChannelinStripRow;
381 
382  for (int i = 0; i < 3; i++) {
383  // Do not cluster strips that are outside the range of this chip
384  if ((stripID + 1 + i) >= maxStripIDForCurrChip) continue;
385  if (firedStrips.find(stripID + 1 + i) != firedStrips.end()) {
386  if (firedStrips.at(stripID + 1 + i)) {
387  hitMap[2 - i] = 1;
388  firedStrips[stripID + 1 + i] = false;
389  } else {
390  hitMap[2 - i] = 0;
391  }
392  }
393  }
394 
395  // Encode the hit map into an integer
396  stripEncodingForITK[stripID] = static_cast<int>(hitMap.to_ulong());
397  stripEncodingForITKToRDO[stripID] = firedStripsToRDO[stripID];
398  }
399 
400  stripNumber = 0;
401  firstClusterFilled = false;
402 
403  // Process each fired strip and encode it
404  for (const auto& [stripID, encoding] : stripEncodingForITK) {
405  const SCT_RDORawData* sctRawData = stripEncodingForITKToRDO[stripID];
406  const Identifier rdoId = sctRawData->identify();
407  const InDetDD::SiDetectorElement* sielement = m_SCT_mgr->getDetectorElement(rdoId);
408 
409  // if hash list has elements, check if the current Si in the list otherwise, continue
410  if(hashList.size() > 0)
411  {
412  if(std::find(hashList.begin(), hashList.end(), sielement->identifyHash()) == hashList.end()) continue;
413  }
414 
415  // Fill the module header if not already filled
416  if (!filledHeader) {
417  if (!fillModuleHeader(sielement, encodedData)) return StatusCode::FAILURE;
418  filledHeader = true;
419  }
420 
421  // Compute chip ID and ITk strip ID
422  int chipID = stripID / MaxChannelinStripRow;
423  int ITkStripID = stripID % MaxChannelinStripRow;
424 
425  // Adjust for row offset based on the eta module index
426  int offset = m_sctId->eta_module(rdoId) % 2;
427  if (m_sctId->barrel_ec(rdoId) == 0) {
428  offset = (std::abs(m_sctId->eta_module(rdoId)) - 1) % 2;
429  }
430  ITkStripID += offset * MaxChannelinStripRow;
431  stripNumber++;
432  // Determine if this is the last cluster in the module
433  bool lastBit = (stripNumber == stripEncodingForITK.size());
434 
435  // Create the encoded strip word
436  auto stripWord = FPGADataFormatUtilities::fill_STRIP_EF_RDO(
437  lastBit, // last bit indicating module boundary
438  chipID, // chip ID
439  ITkStripID, // cluster number
440  stripEncodingForITK.at(stripID), // cluster map
441  0x0F0F // spare bits
442  );
443 
444  uint32_t encodedCluster = FPGADataFormatUtilities::get_dataformat_STRIP_EF_RDO(stripWord);
445 
446  // **Pack two clusters into a single 64-bit word**
447  if (!firstClusterFilled) {
448  packedWord = (static_cast<uint64_t>(encodedCluster) << 32); // Store first cluster in upper 32 bits
449  firstClusterFilled = true;
450  } else {
451  packedWord |= static_cast<uint64_t>(encodedCluster); // Store second cluster in lower 32 bits
452  encodedData.push_back(packedWord); // Push the full packed word
453  firstClusterFilled = false; // Reset flag
454  packedWord = 0; // Clear for the next pair
455  }
456 
457  // If this is the last cluster in the module and a single cluster is left, push it
458  if (lastBit && firstClusterFilled) {
459  encodedData.push_back(packedWord);
460  }
461 
462  }
463  // Reset the header flag for the next module
464  filledHeader = false;
465  } // end for each RDO in the strip collection
466 
467  return StatusCode::SUCCESS;
468 }

◆ fillFooter()

StatusCode FPGADataFormatTool::fillFooter ( std::vector< uint64_t > &  encodedData) const
private

Definition at line 488 of file FPGADataFormatTool.cxx.

489 {
490  // Fill the event header
491  auto footer_w1 = FPGADataFormatUtilities::fill_EVT_FTR_w1 (FPGADataFormatUtilities::EVT_FTR_FLAG, 0, 0);
492  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_EVT_FTR_w1(footer_w1));
493 
494  // Fill the event header
495  auto footer_w2 = FPGADataFormatUtilities::fill_EVT_FTR_w2 (0);
496  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_EVT_FTR_w2(footer_w2));
497 
498  // Fill the event header
499  auto footer_w3 = FPGADataFormatUtilities::fill_EVT_FTR_w3 (encodedData.size(), 44939973);
500  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_EVT_FTR_w3(footer_w3));
501 
502  return StatusCode::SUCCESS;
503 }

◆ fillHeader()

StatusCode FPGADataFormatTool::fillHeader ( std::vector< uint64_t > &  encodedData) const
private

Definition at line 471 of file FPGADataFormatTool.cxx.

472 {
473  // Fill the event header
474  auto header_w1 = FPGADataFormatUtilities::fill_EVT_HDR_w1 (FPGADataFormatUtilities::EVT_HDR_FLAG, 1, 0, 0);
475  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_EVT_HDR_w1(header_w1));
476 
477  // Fill the event header
478  auto header_w2 = FPGADataFormatUtilities::fill_EVT_HDR_w2 (242000, 0);
479  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_EVT_HDR_w2(header_w2));
480 
481  // Fill the event header
482  auto header_w3 = FPGADataFormatUtilities::fill_EVT_HDR_w3 (0, 0);
483  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_EVT_HDR_w3(header_w3));
484 
485  return StatusCode::SUCCESS;
486 }

◆ fillHit()

void FPGADataFormatTool::fillHit ( const FPGATrackSimHit *  hit,
bool  isLast,
bool  isLastofSlice,
std::vector< uint64_t > &  encodedData 
) const
private

Definition at line 516 of file FPGADataFormatTool.cxx.

517 {
518  int cluster1D=0;
519  int cluster2D=0;
520  if(hit->getOriginalHit().getCluster1ID() >=0)
521  {
522  cluster1D=hit->getOriginalHit().getCluster1ID();
523  }
524 
525  if(hit->getOriginalHit().getCluster2ID() >=0)
526  {
527  cluster2D=hit->getOriginalHit().getCluster2ID();
528  }
529 
530  ATH_MSG_DEBUG("\tphiregion: " << hit->getLayer());
531  ATH_MSG_DEBUG("\tR: " << hit->getR());
532  ATH_MSG_DEBUG("\tphi: " << hit->getGPhi());
533  ATH_MSG_DEBUG("\tZ: " << hit->getZ());
534  ATH_MSG_DEBUG("\tcluster1D: " << cluster1D);
535  ATH_MSG_DEBUG("\tcluster2D: " << cluster2D);
536 
537  auto ghit_w1 = FPGADataFormatUtilities::fill_GHITZ_w1(isLast, hit->getLayer(), hit->getR(), hit->getGPhi(), hit->getZ(), isLastofSlice, 0);
538  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_GHITZ_w1(ghit_w1));
539  // overwrite the information for now
540  cluster1D = hit->getIdentifierHash();
541  auto ghit_w2 = FPGADataFormatUtilities::fill_GHITZ_w2 (cluster1D, cluster2D, hit->getEtaModule(), 0);
542  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_GHITZ_w2(ghit_w2));
543 }

◆ fillModuleHeader()

StatusCode FPGADataFormatTool::fillModuleHeader ( const InDetDD::SiDetectorElement *  sielement,
std::vector< uint64_t > &  encodedData 
) const
private

Definition at line 505 of file FPGADataFormatTool.cxx.

506 {
507  auto mod_w1 = FPGADataFormatUtilities::fill_M_HDR_w1 (FPGADataFormatUtilities::M_HDR_FLAG, sielement->identify().get_identifier32().get_compact(),
508  sielement->identifyHash().value(), 0);
509  encodedData.push_back(FPGADataFormatUtilities::get_dataformat_M_HDR_w1(mod_w1));
510 
511  return StatusCode::SUCCESS;
512 }

◆ initialize()

StatusCode FPGADataFormatTool::initialize ( )
overridevirtual

Definition at line 9 of file FPGADataFormatTool.cxx.

9  {
10  ATH_MSG_INFO("Initializing IEFTrackingFPGADataFormatTool tool");
11 
12  ATH_CHECK(detStore()->retrieve(m_PIX_mgr, "ITkPixel"));
13  ATH_CHECK(detStore()->retrieve(m_pixelId, "PixelID"));
14  ATH_CHECK(detStore()->retrieve(m_SCT_mgr, "ITkStrip"));
15  ATH_CHECK(detStore()->retrieve(m_sctId, "SCT_ID"));
16 
17  return StatusCode::SUCCESS;
18 }

Member Data Documentation

◆ m_PIX_mgr

const InDetDD::SiDetectorManager* FPGADataFormatTool::m_PIX_mgr = nullptr
private

Definition at line 71 of file FPGADataFormatTool.h.

◆ m_pixelId

const PixelID* FPGADataFormatTool::m_pixelId = nullptr
private

Definition at line 68 of file FPGADataFormatTool.h.

◆ m_SCT_mgr

const InDetDD::SiDetectorManager* FPGADataFormatTool::m_SCT_mgr = nullptr
private

Definition at line 72 of file FPGADataFormatTool.h.

◆ m_sctId

const SCT_ID* FPGADataFormatTool::m_sctId = nullptr
private

Definition at line 69 of file FPGADataFormatTool.h.

The documentation for this class was generated from the following files:
python.PyKernel.retrieve
def retrieve(aClass, aKey=None)
Definition: PyKernel.py:110
FPGADataFormatUtilities::SLICE_HDR_FLAG
const int SLICE_HDR_FLAG
Definition: FPGADataFormatUtilities.h:378
FPGADataFormatUtilities::fill_GTRACK_HDR_w3
GTRACK_HDR_w3 fill_GTRACK_HDR_w3(const double &qoverpt, const double &phi, const double &eta, const uint64_t &spare)
Definition: FPGADataFormatUtilities.h:835
FPGADataFormatTool::fillFooter
StatusCode fillFooter(std::vector< uint64_t > &encodedData) const
Definition: FPGADataFormatTool.cxx:488
InDetDD::SiDetectorManager::getDetectorElement
virtual const SiDetectorElement * getDetectorElement(const Identifier &id) const =0
access to individual elements using Identifier or IdentiferHash
PixelID::phi_index
int phi_index(const Identifier &id) const
Definition: PixelID.h:654
FPGADataFormatTool::fillHeader
StatusCode fillHeader(std::vector< uint64_t > &encodedData) const
Definition: FPGADataFormatTool.cxx:471
TRTCalib_Extractor.hits
hits
Definition: TRTCalib_Extractor.py:35
FPGATrackSimHit::getEtaModule
int getEtaModule(bool old=false) const
Definition: FPGATrackSimHit.h:87
FPGATrackSimHit::isStrip
bool isStrip() const
Definition: FPGATrackSimHit.h:65
FPGADataFormatTool::convertFPGASlices
StatusCode convertFPGASlices(const FPGATrackSimHitCollection *hitsInSlices, bool doPixel, bool doStrip, std::vector< uint64_t > &encodedData, const EventContext &ctx) const
Definition: FPGADataFormatTool.cxx:82
FPGADataFormatUtilities::get_dataformat_EVT_HDR_w3
uint64_t get_dataformat_EVT_HDR_w3(const EVT_HDR_w3 &in)
Definition: FPGADataFormatUtilities.h:113
FPGADataFormatUtilities::get_dataformat_EVT_FTR_w2
uint64_t get_dataformat_EVT_FTR_w2(const EVT_FTR_w2 &in)
Definition: FPGADataFormatUtilities.h:249
ATH_MSG_INFO
#define ATH_MSG_INFO(x)
Definition: AthMsgStreamMacros.h:31
find
std::string find(const std::string &s)
return a remapped string
Definition: hcg.cxx:135
FPGATrackSimTrack
Definition: FPGATrackSimTrack.h:18
xAOD::uint32_t
setEventNumber uint32_t
Definition: EventInfo_v1.cxx:127
FPGADataFormatUtilities::EVT_HDR_FLAG
const int EVT_HDR_FLAG
Definition: FPGADataFormatUtilities.h:20
FPGADataFormatTool::convertFPGATracks
StatusCode convertFPGATracks(const FPGATrackSimTrackCollection *tracks, std::vector< uint64_t > &encodedData, const EventContext &ctx) const
Definition: FPGADataFormatTool.cxx:214
FPGADataFormatUtilities::fill_GTRACK_HDR_w1
GTRACK_HDR_w1 fill_GTRACK_HDR_w1(const uint64_t &flag, const uint64_t &type, const uint64_t &eta_region, const uint64_t &phi_region, const uint64_t &phi_bin, const uint64_t &z_bin, const uint64_t &second_stage, const uint64_t &layer_bitmask)
Definition: FPGADataFormatUtilities.h:813
FPGADataFormatUtilities::fill_STRIP_EF_RDO
STRIP_EF_RDO fill_STRIP_EF_RDO(const uint64_t &last, const uint64_t &chipid, const uint64_t &strip_num, const uint64_t &cluster_map, const uint64_t &spare)
Definition: FPGADataFormatUtilities.h:2309
Identifier::get_identifier32
Identifier32 get_identifier32() const
Get the 32-bit version Identifier, will be invalid if >32 bits needed.
FPGADataFormatUtilities::get_dataformat_M_HDR_w1
uint64_t get_dataformat_M_HDR_w1(const M_HDR_w1 &in)
Definition: FPGADataFormatUtilities.h:343
FPGATrackSimHit::getCluster2ID
int getCluster2ID() const
Definition: FPGATrackSimHit.h:193
SCT_RDORawData
Definition: SCT_RDORawData.h:24
SCT_ID::barrel_ec
int barrel_ec(const Identifier &id) const
Values of different levels (failure returns 0)
Definition: SCT_ID.h:728
FPGADataFormatTool::m_PIX_mgr
const InDetDD::SiDetectorManager * m_PIX_mgr
Definition: FPGADataFormatTool.h:71
FPGADataFormatUtilities::get_dataformat_SLICE_HDR_w1
uint64_t get_dataformat_SLICE_HDR_w1(const SLICE_HDR_w1 &in)
Definition: FPGADataFormatUtilities.h:419
FPGATrackSimHit::getLayer
int getLayer() const
Definition: FPGATrackSimHit.cxx:87
FPGADataFormatUtilities::fill_GTRACK_HDR_w2
GTRACK_HDR_w2 fill_GTRACK_HDR_w2(const double &score, const double &d0, const double &z0, const uint64_t &spare)
Definition: FPGADataFormatUtilities.h:826
FPGADataFormatUtilities::fill_EVT_HDR_w2
EVT_HDR_w2 fill_EVT_HDR_w2(const uint64_t &runnumber, const uint64_t &time)
Definition: FPGADataFormatUtilities.h:129
FPGADataFormatUtilities::get_dataformat_GHITZ_w2
uint64_t get_dataformat_GHITZ_w2(const GHITZ_w2 &in)
Definition: FPGADataFormatUtilities.h:1187
FPGADataFormatUtilities::fill_EVT_FTR_w3
EVT_FTR_w3 fill_EVT_FTR_w3(const uint64_t &word_count, const uint64_t &crc)
Definition: FPGADataFormatUtilities.h:276
Identifier32::get_compact
value_type get_compact() const
Get the compact id.
Definition: Identifier32.h:44
InDetDD::SolidStateDetectorElementBase::identifyHash
virtual IdentifierHash identifyHash() const override final
identifier hash (inline)
FPGADataFormatTool::convertStripRDO
StatusCode convertStripRDO(const SCT_RDO_Container &stripRDO, std::vector< uint64_t > &encodedData, const std::vector< IdentifierHash > &hashList, const EventContext &ctx) const
Definition: FPGADataFormatTool.cxx:339
FPGATrackSimHit
Definition: FPGATrackSimHit.h:41
FPGATrackSimHit::getGPhi
float getGPhi() const
Definition: FPGATrackSimHit.h:153
FPGADataFormatUtilities::fill_EVT_HDR_w1
EVT_HDR_w1 fill_EVT_HDR_w1(const uint64_t &flag, const uint64_t &l0id, const uint64_t &bcid, const uint64_t &spare)
Definition: FPGADataFormatUtilities.h:120
FPGATrackSimHit::getIdentifier
unsigned int getIdentifier() const
Definition: FPGATrackSimHit.h:80
FPGADataFormatUtilities::M_HDR_FLAG
const int M_HDR_FLAG
Definition: FPGADataFormatUtilities.h:308
FPGADataFormatUtilities::get_dataformat_PIXEL_EF_RDO
uint64_t get_dataformat_PIXEL_EF_RDO(const PIXEL_EF_RDO &in)
Definition: FPGADataFormatUtilities.h:2201
FPGADataFormatUtilities::fill_SLICE_HDR_w1
SLICE_HDR_w1 fill_SLICE_HDR_w1(const uint64_t &flag, const uint64_t &sliceid, const uint64_t &eta_region, const uint64_t &phi_region, const uint64_t &spare)
Definition: FPGADataFormatUtilities.h:429
FPGADataFormatUtilities::fill_GHITZ_w1
GHITZ_w1 fill_GHITZ_w1(const uint64_t &last, const uint64_t &lyr, const double &rad, const double &phi, const double &z, const uint64_t &lastofslice, const uint64_t &spare)
Definition: FPGADataFormatUtilities.h:1196
FPGADataFormatUtilities::get_dataformat_EVT_HDR_w2
uint64_t get_dataformat_EVT_HDR_w2(const EVT_HDR_w2 &in)
Definition: FPGADataFormatUtilities.h:106
FPGADataFormatUtilities::get_dataformat_EVT_FTR_w3
uint64_t get_dataformat_EVT_FTR_w3(const EVT_FTR_w3 &in)
Definition: FPGADataFormatUtilities.h:255
FPGADataFormatUtilities::EVT_FTR_FLAG
const int EVT_FTR_FLAG
Definition: FPGADataFormatUtilities.h:176
lumiFormat.i
int i
Definition: lumiFormat.py:85
FPGATrackSimHit::getOriginalHit
const FPGATrackSimHit getOriginalHit() const
Definition: FPGATrackSimHit.cxx:131
ATH_MSG_DEBUG
#define ATH_MSG_DEBUG(x)
Definition: AthMsgStreamMacros.h:29
generateReferenceFile.encoding
encoding
Definition: generateReferenceFile.py:15
FPGADataFormatUtilities::get_dataformat_STRIP_EF_RDO
uint64_t get_dataformat_STRIP_EF_RDO(const STRIP_EF_RDO &in)
Definition: FPGADataFormatUtilities.h:2294
InDetRawDataCollection
Definition: InDetRawDataCollection.h:31
FPGADataFormatTool::fillModuleHeader
StatusCode fillModuleHeader(const InDetDD::SiDetectorElement *sielement, std::vector< uint64_t > &encodedData) const
Definition: FPGADataFormatTool.cxx:505
PixelID::eta_index
int eta_index(const Identifier &id) const
Definition: PixelID.h:660
xAOD::uint64_t
uint64_t
Definition: EventInfo_v1.cxx:123
ATH_CHECK
#define ATH_CHECK
Definition: AthCheckMacros.h:40
FPGADataFormatUtilities::fill_EVT_HDR_w3
EVT_HDR_w3 fill_EVT_HDR_w3(const uint64_t &status, const uint64_t &crc)
Definition: FPGADataFormatUtilities.h:136
FPGADataFormatUtilities::get_dataformat_GHITZ_w1
uint64_t get_dataformat_GHITZ_w1(const GHITZ_w1 &in)
Definition: FPGADataFormatUtilities.h:1175
FPGATrackSimHit::getIdentifierHash
unsigned getIdentifierHash() const
Definition: FPGATrackSimHit.h:81
FPGATrackSimHit::isPixel
bool isPixel() const
Definition: FPGATrackSimHit.h:64
FPGADataFormatTool::fillHit
void fillHit(const FPGATrackSimHit *hit, bool isLast, bool isLastofSlice, std::vector< uint64_t > &encodedData) const
Definition: FPGADataFormatTool.cxx:516
FPGATrackSimHit::getZ
float getZ() const
Definition: FPGATrackSimHit.h:151
python.PyKernel.detStore
detStore
Definition: PyKernel.py:41
FPGADataFormatTool::m_pixelId
const PixelID * m_pixelId
Definition: FPGADataFormatTool.h:68
InDetDD::SiDetectorElement
Definition: SiDetectorElement.h:109
FPGADataFormatTool::m_sctId
const SCT_ID * m_sctId
Definition: FPGADataFormatTool.h:69
IdentifierHash::value
value_type value() const
FPGADataFormatUtilities::get_dataformat_EVT_FTR_w1
uint64_t get_dataformat_EVT_FTR_w1(const EVT_FTR_w1 &in)
Definition: FPGADataFormatUtilities.h:241
FPGADataFormatUtilities::fill_PIXEL_EF_RDO
PIXEL_EF_RDO fill_PIXEL_EF_RDO(const uint64_t &last, const uint64_t &row, const uint64_t &col, const uint64_t &tot, const uint64_t &lvl1, const uint64_t &spare)
Definition: FPGADataFormatUtilities.h:2212
FPGATrackSimHit::getR
float getR() const
Definition: FPGATrackSimHit.h:152
FPGADataFormatUtilities::get_dataformat_GTRACK_HDR_w1
uint64_t get_dataformat_GTRACK_HDR_w1(const GTRACK_HDR_w1 &in)
Definition: FPGADataFormatUtilities.h:782
FPGATrackSimHit::getCluster1ID
int getCluster1ID() const
Definition: FPGATrackSimHit.h:190
SCT_ID::strip
int strip(const Identifier &id) const
Definition: SCT_ID.h:764
SCT_ID::eta_module
int eta_module(const Identifier &id) const
Definition: SCT_ID.h:746
convertTimingResiduals.offset
offset
Definition: convertTimingResiduals.py:71
FPGADataFormatTool::convertFPGAHits
StatusCode convertFPGAHits(const FPGATrackSimHitCollection *hits, bool doPixel, bool doStrip, std::vector< uint64_t > &encodedData, const EventContext &ctx) const
Definition: FPGADataFormatTool.cxx:152
PixelRDORawData
Definition: PixelRDORawData.h:23
FPGADataFormatTool::convertPixelRDO
StatusCode convertPixelRDO(const PixelRDO_Container &pixelRDO, std::vector< uint64_t > &encodedData, const std::vector< IdentifierHash > &hashList, const EventContext &ctx) const
Definition: FPGADataFormatTool.cxx:285
InDetRawData::identify
virtual Identifier identify() const override final
Definition: InDetRawData.h:41
FPGADataFormatTool::m_SCT_mgr
const InDetDD::SiDetectorManager * m_SCT_mgr
Definition: FPGADataFormatTool.h:72
xAOD::track
@ track
Definition: TrackingPrimitives.h:513
FPGADataFormatUtilities::fill_EVT_FTR_w2
EVT_FTR_w2 fill_EVT_FTR_w2(const uint64_t &error_flags)
Definition: FPGADataFormatUtilities.h:270
FPGADataFormatUtilities::fill_EVT_FTR_w1
EVT_FTR_w1 fill_EVT_FTR_w1(const uint64_t &flag, const uint64_t &spare, const uint64_t &hdr_crc)
Definition: FPGADataFormatUtilities.h:262
test_pyathena.counter
counter
Definition: test_pyathena.py:15
FPGADataFormatUtilities::get_dataformat_EVT_HDR_w1
uint64_t get_dataformat_EVT_HDR_w1(const EVT_HDR_w1 &in)
Definition: FPGADataFormatUtilities.h:97
FPGADataFormatUtilities::get_dataformat_GTRACK_HDR_w2
uint64_t get_dataformat_GTRACK_HDR_w2(const GTRACK_HDR_w2 &in)
Definition: FPGADataFormatUtilities.h:795
InDetDD::SolidStateDetectorElementBase::identify
virtual Identifier identify() const override final
identifier of this detector element (inline)
keylayer_zslicemap.slices
slices
Definition: keylayer_zslicemap.py:112
FPGADataFormatUtilities::get_dataformat_GTRACK_HDR_w3
uint64_t get_dataformat_GTRACK_HDR_w3(const GTRACK_HDR_w3 &in)
Definition: FPGADataFormatUtilities.h:804
FPGADataFormatUtilities::fill_GHITZ_w2
GHITZ_w2 fill_GHITZ_w2(const uint64_t &cluster1, const uint64_t &cluster2, const uint64_t &row, const uint64_t &spare)
Definition: FPGADataFormatUtilities.h:1208
FPGADataFormatUtilities::fill_M_HDR_w1
M_HDR_w1 fill_M_HDR_w1(const uint64_t &flag, const uint64_t &modid, const uint64_t &modhash, const uint64_t &spare)
Definition: FPGADataFormatUtilities.h:352
Identifier
Definition: IdentifierFieldParser.cxx:14
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