51def TileTTL1OverlayCfg(flags, name="TileTTL1Overlay", **kwargs):
52 """TileTTL1Overlay configuration using ComponentAccumulator"""
53 acc = ComponentAccumulator()
54 acc.merge(TileHitToTTL1Cfg(flags))
55
56 kwargs.setdefault("BkgTileTTL1Key", f"{flags.Overlay.BkgPrefix}TileTTL1Cnt")
57 kwargs.setdefault("SignalTileTTL1Key", f"{flags.Overlay.SigPrefix}TileTTL1Cnt")
58 kwargs.setdefault("OutputTileTTL1Key", "TileTTL1Cnt")
59 inputs = [f'TileTTL1Container#{kwargs["BkgTileTTL1Key"]}']
60
61 if flags.Detector.EnableMBTS:
62 kwargs.setdefault("BkgTileMBTSTTL1Key", f"{flags.Overlay.BkgPrefix}TileTTL1MBTS")
63 kwargs.setdefault("SignalTileMBTSTTL1Key", f"{flags.Overlay.SigPrefix}TileTTL1MBTS")
64 kwargs.setdefault("OutputTileMBTSTTL1Key", "TileTTL1MBTS")
65 inputs.append(f'TileTTL1Container#{kwargs["BkgTileMBTSTTL1Key"]}')
66 else:
67 kwargs.setdefault("BkgTileMBTSTTL1Key", "")
68 kwargs.setdefault("SignalTileMBTSTTL1Key", "")
69 kwargs.setdefault("OutputTileMBTSTTL1Key", "")
70
71 from SGComps.SGInputLoaderConfig import SGInputLoaderCfg
72 acc.merge(SGInputLoaderCfg(flags, inputs))
73
74 acc.addEventAlgo(CompFactory.LVL1.TileTTL1Overlay(name, **kwargs))
75
76 if flags.Output.doWriteRDO:
77 from OutputStreamAthenaPool.OutputStreamConfig import OutputStreamCfg
78 acc.merge(OutputStreamCfg(flags, streamName='RDO', ItemList=[
79 'TileTTL1Container#TileTTL1Cnt',
80 ]))
81 if flags.Detector.EnableMBTS:
82 acc.merge(OutputStreamCfg(flags, streamName='RDO', ItemList=[
83 'TileTTL1Container#TileTTL1MBTS',
84 ]))
85
86 if flags.Output.doWriteRDO_SGNL:
87 from OutputStreamAthenaPool.OutputStreamConfig import OutputStreamCfg
88 acc.merge(OutputStreamCfg(flags, streamName='RDO_SGNL', ItemList=[
89 f'TileTTL1Container#{flags.Overlay.SigPrefix}TileTTL1Cnt',
90 ]))
91 if flags.Detector.EnableMBTS:
92 acc.merge(OutputStreamCfg(flags, streamName='RDO_SGNL', ItemList=[
93 f'TileTTL1Container#{flags.Overlay.SigPrefix}TileTTL1MBTS',
94 ]))
95
96 return acc