5#ifndef TopoCore_L1TopoConfigOutputList
6#define TopoCore_L1TopoConfigOutputList
10#include <unordered_set>
64 unsigned int firstBit) :
107 bool hasTrigger(
const std::string & trigger)
const;
const TXC::TriggerLine & getTrigger(const std::string &trigger) const
bool hasTrigger(const std::string &trigger) const
std::unordered_set< unsigned int > m_triggercounters
std::unordered_set< std::string > m_triggernames
const std::vector< OutputListElement > & getOutputList() const
std::vector< OutputListElement > m_outputListElements
void addTriggerLine(const TriggerLine &trigger)
std::vector< TriggerLine > m_triggerlines
L1TopoConfigOutputList(L1TopoConfigOutputList &&) noexcept=default
virtual ~L1TopoConfigOutputList()
void addOutputListElement(const OutputListElement &output)
const std::vector< TriggerLine > & getTriggerLines() const
const std::string & algoname() const
OutputListElement(const std::string &algoname, unsigned int algoId, unsigned int module, unsigned int fpga, unsigned int clock, unsigned int firstBit)
unsigned int module() const
unsigned int firstbit() const
unsigned int clock() const
unsigned int fpga() const
unsigned int algoid() const
unsigned int algoid() const
TriggerLine(const std::string &name, const std::string &algoname, unsigned int algoId, unsigned int module, unsigned int fpga, unsigned int clock, unsigned int bit)
unsigned int fpga() const
unsigned int counter() const
unsigned int module() const
const std::string & name() const
unsigned int clock() const
const std::string & algoname() const
std::ostream & operator<<(std::ostream &, const TXC::L1TopoConfigAlg &)