8#include "Identifier/Identifier.h"
27 return ((moduleId==169922560) or (moduleId==170801152) or (moduleId==172556288) or (moduleId==172621824) or
28 (moduleId==174342144) or (moduleId==174610432) or (moduleId==174962688));
32 return ((moduleId==170983424) or (moduleId==173268992) or (moduleId==174301184) or (moduleId==175015936));
45 if (std::abs(bec) == 2) {
141 if (chip.
isEnd())
return false;
147 if (inChipId ==
None) {
148 ATH_MSG_WARNING(
"Chip " << chip.
id() <<
" is not an end but port " << chip.
inPort() <<
" is not mapped to anything");
154 const std::vector<SCT_Chip>& chips = *
m_chips;
155 if (chips.at(inChipId).outPort()!=chip.
inPort()) {
156 ATH_MSG_WARNING(
"Chip" << chip.
id() <<
" is not an end and is listening on Port " << chip.
inPort() <<
" but nothing is talking to it");
167 if (not chip.
isEnd())
return false;
170 const std::vector<SCT_Chip>& chips = *
m_chips;
171 for (
const SCT_Chip& thisChip: chips) {
173 ATH_MSG_WARNING(
"Chip " << chip.
id() <<
" is configured as end but something is trying to talk to it");
187 thisChip.initializeMaskFromInts(masked, masked, masked, masked);
196 if (remainingDepth < 0) {
204 if (chip.
id()==link*6) {
215 }
else if (chip.
id() == link*6) {
219 ATH_MSG_DEBUG(
"Link " << link <<
" is enabled but chip " << chip.
id() <<
" is not a master");
260 if (chipsOnThisLink.size()!=6)
return false;
264 for (
int linkItr: chipsOnThisLink) {
265 if (linkItr!=ichip)
return false;
274 if (not
msgLvl(MSG::DEBUG))
return;
278 msg(MSG::DEBUG) <<
"Readout status " << moduleId <<
": "
283 msg(MSG::DEBUG) <<
" Link0 = " << std::boolalpha <<
m_linkActive[0] <<
" (";
286 msg(MSG::DEBUG) <<
"X";
288 for (
unsigned int ilink0{0}; ilink0 <
m_chipsOnLink0.size(); ++ilink0) {
293 msg(MSG::DEBUG) <<
") Link1 = " << std::boolalpha <<
m_linkActive[1] <<
" (";
296 msg(MSG::DEBUG) <<
"X";
298 for (
unsigned int ilink1{0}; ilink1 <
m_chipsOnLink1.size(); ++ilink1) {
303 msg(MSG::DEBUG) <<
") " << (standard ?
"Standard" :
"Non-standard") <<
endmsg;
#define ATH_MSG_WARNING(x)
static bool modified1(Identifier moduleId)
static bool modified0(Identifier moduleId)
Header file for the SCT_ReadoutData class.
MsgStream & msg() const
The standard message stream.
bool msgLvl(const MSG::Level lvl) const
Test the output level.
AthMessaging(IMessageSvc *msgSvc, const std::string &name)
Constructor.
Class which stores infomration on the SCT chips: id, config, mask.
short inPort() const
Active input port.
bool isMaster() const
Is chip a master.
bool isEnd() const
Is chip an end.
bool canBeMaster() const
Can chip be a master (i.e position 0 or 6)
bool slaveConfiguredAsMaster() const
Is this a slave chip mistakenly configured as a master.
void clearChipReadout()
Set all chips out of readout and clear both links to start.
bool isChipReadOut(const SCT_Chip &chip) const
Test if chip is in readout or not.
void setModuleType(const Identifier &moduleId, int bec)
Set the module type.
SCT_Parameters::ChipType inputChip(const SCT_Chip &chip) const
Find the ID of the input chip for chip.
std::vector< int > m_chipsOnLink1
bool hasConnectedInput(const SCT_Chip &chip) const
Chip has a correctly connected input.
void setLinkStatus(bool link0ok, bool link1ok)
Set link status.
bool m_linkActive[2]
Links status for link 0 and 1.
void setChipIn(const SCT_Chip &chip, int link)
Set chip in readout and which link it is on.
std::bitset< SCT_Parameters::NChips > m_chipInReadout
Bitset indicating whether a chip is readout or not.
std::vector< SCT_PortMap > m_chipMap
Vector of port mapping from the chips in an SCT module.
bool followReadoutUpstream(int link, const SCT_Chip &chip, int remainingDepth=12)
Follow the readout to the input side.
SCT_ReadoutData(IMessageSvc *msgSvc=nullptr)
void setChipMap()
Fill the chip mapping.
void maskChipsNotInReadout()
Mask the chips that are not in the readout.
void setChipOut(const SCT_Chip &chip)
Set chip out of readout and reset link.
std::vector< int > m_chipsOnLink0
The chips read out on link 0.
void checkLink(int link)
Check which chips are in the readout for a particular link and if the readout is sane.
void setChips(std::vector< SCT_Chip > &chips)
Set SCT_Chip vectors.
SCT_Parameters::ModuleType m_type
The type of this module (Barrel, Modified Barrel (0 or 1), Endcap)
bool isEndBeingTalkedTo(const SCT_Chip &chip) const
Chip is an end but is being talked to.
bool isLinkStandard(int link) const
is the readout for a particular link sane
SCT_Parameters::ChipType outputChip(const SCT_Chip &chip) const
Find the ID of the output chip for chip.
void printStatus(const Identifier &moduleId) const
Print readout status.
std::vector< SCT_Chip > * m_chips
Private data.
void sort(typename DataModel_detail::iterator< DVL > beg, typename DataModel_detail::iterator< DVL > end)
Specialization of sort for DataVector/List.