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ATLAS Offline Software
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uint64_t | get_dataformat_EVT_HDR_w1 (const EVT_HDR_w1 &in) |
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uint64_t | get_dataformat_EVT_HDR_w2 (const EVT_HDR_w2 &in) |
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uint64_t | get_dataformat_EVT_HDR_w3 (const EVT_HDR_w3 &in) |
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EVT_HDR_w1 | fill_EVT_HDR_w1 (const uint64_t &flag, const uint64_t &l0id, const uint64_t &bcid, const uint64_t &spare) |
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EVT_HDR_w2 | fill_EVT_HDR_w2 (const uint64_t &runnumber, const uint64_t &time) |
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EVT_HDR_w3 | fill_EVT_HDR_w3 (const uint64_t &status, const uint64_t &crc) |
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uint64_t | get_dataformat_EVT_FTR_w1 (const EVT_FTR_w1 in) |
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uint64_t | get_dataformat_EVT_FTR_w2 (const EVT_FTR_w2 in) |
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uint64_t | get_dataformat_EVT_FTR_w3 (const EVT_FTR_w3 in) |
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EVT_FTR_w1 | fill_EVT_FTR_w1 (const uint64_t flag, const uint64_t spare, const uint64_t hdr_crc) |
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EVT_FTR_w2 | fill_EVT_FTR_w2 (const uint64_t error_flags) |
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EVT_FTR_w3 | fill_EVT_FTR_w3 (const uint64_t word_count, const uint64_t crc) |
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uint64_t | get_dataformat_M_HDR_w3 (const M_HDR_w3 in) |
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M_HDR_w3 | fill_M_HDR_w3 (const uint64_t flag, const uint64_t modid, const uint64_t spare) |
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uint64_t | get_dataformat_PIXEL_EF_RDO (const PIXEL_EF_RDO in) |
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PIXEL_EF_RDO | fill_PIXEL_EF_RDO (const uint64_t last, const uint64_t row, const uint64_t col, const uint64_t tot, const uint64_t lvl1, const uint64_t id, const uint64_t spare) |
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uint64_t | get_dataformat_STRIP_EF_RDO (const STRIP_EF_RDO in) |
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STRIP_EF_RDO | fill_STRIP_EF_RDO (const uint64_t last, const uint64_t chipid, const uint64_t strip_num, const uint64_t cluster_map, const uint64_t id, const uint64_t spare) |
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◆ EVT_FTR_w1
◆ EVT_FTR_w2
◆ EVT_FTR_w3
◆ EVT_HDR_w1
◆ EVT_HDR_w2
◆ EVT_HDR_w3
◆ M_HDR_w3
◆ PIXEL_EF_RDO
◆ STRIP_EF_RDO
◆ fill_EVT_FTR_w1()
◆ fill_EVT_FTR_w2()
EVT_FTR_w2 FPGADataFormatUtilites::fill_EVT_FTR_w2 |
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const uint64_t |
error_flags | ) |
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◆ fill_EVT_FTR_w3()
EVT_FTR_w3 FPGADataFormatUtilites::fill_EVT_FTR_w3 |
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const uint64_t |
word_count, |
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const uint64_t |
crc |
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) |
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◆ fill_EVT_HDR_w1()
◆ fill_EVT_HDR_w2()
EVT_HDR_w2 FPGADataFormatUtilites::fill_EVT_HDR_w2 |
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const uint64_t & |
runnumber, |
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const uint64_t & |
time |
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) |
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◆ fill_EVT_HDR_w3()
EVT_HDR_w3 FPGADataFormatUtilites::fill_EVT_HDR_w3 |
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const uint64_t & |
status, |
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const uint64_t & |
crc |
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) |
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◆ fill_M_HDR_w3()
◆ fill_PIXEL_EF_RDO()
◆ fill_STRIP_EF_RDO()
Definition at line 327 of file FPGADataFormatUtilities.h.
330 temp.chipid = chipid;
331 temp.strip_num = strip_num;
332 temp.cluster_map = cluster_map;
◆ get_dataformat_EVT_FTR_w1()
uint64_t FPGADataFormatUtilites::get_dataformat_EVT_FTR_w1 |
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const EVT_FTR_w1 |
in | ) |
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◆ get_dataformat_EVT_FTR_w2()
uint64_t FPGADataFormatUtilites::get_dataformat_EVT_FTR_w2 |
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const EVT_FTR_w2 |
in | ) |
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◆ get_dataformat_EVT_FTR_w3()
uint64_t FPGADataFormatUtilites::get_dataformat_EVT_FTR_w3 |
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const EVT_FTR_w3 |
in | ) |
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◆ get_dataformat_EVT_HDR_w1()
uint64_t FPGADataFormatUtilites::get_dataformat_EVT_HDR_w1 |
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const EVT_HDR_w1 & |
in | ) |
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◆ get_dataformat_EVT_HDR_w2()
uint64_t FPGADataFormatUtilites::get_dataformat_EVT_HDR_w2 |
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const EVT_HDR_w2 & |
in | ) |
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◆ get_dataformat_EVT_HDR_w3()
uint64_t FPGADataFormatUtilites::get_dataformat_EVT_HDR_w3 |
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const EVT_HDR_w3 & |
in | ) |
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◆ get_dataformat_M_HDR_w3()
uint64_t FPGADataFormatUtilites::get_dataformat_M_HDR_w3 |
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const M_HDR_w3 |
in | ) |
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◆ get_dataformat_PIXEL_EF_RDO()
uint64_t FPGADataFormatUtilites::get_dataformat_PIXEL_EF_RDO |
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const PIXEL_EF_RDO |
in | ) |
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◆ get_dataformat_STRIP_EF_RDO()
uint64_t FPGADataFormatUtilites::get_dataformat_STRIP_EF_RDO |
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const STRIP_EF_RDO |
in | ) |
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◆ EVT_FTR_FLAG
const int FPGADataFormatUtilites::EVT_FTR_FLAG = 0xcd |
◆ EVT_FTR_W1_FLAG_bits
const int FPGADataFormatUtilites::EVT_FTR_W1_FLAG_bits = 8 |
◆ EVT_FTR_W1_FLAG_lsb
const int FPGADataFormatUtilites::EVT_FTR_W1_FLAG_lsb = 56 |
◆ EVT_FTR_W1_HDR_CRC_bits
const int FPGADataFormatUtilites::EVT_FTR_W1_HDR_CRC_bits = 32 |
◆ EVT_FTR_W1_HDR_CRC_lsb
const int FPGADataFormatUtilites::EVT_FTR_W1_HDR_CRC_lsb = 0 |
◆ EVT_FTR_W1_SPARE_bits
const int FPGADataFormatUtilites::EVT_FTR_W1_SPARE_bits = 24 |
◆ EVT_FTR_W1_SPARE_lsb
const int FPGADataFormatUtilites::EVT_FTR_W1_SPARE_lsb = 32 |
◆ EVT_FTR_W2_ERROR_FLAGS_bits
const int FPGADataFormatUtilites::EVT_FTR_W2_ERROR_FLAGS_bits = 64 |
◆ EVT_FTR_W2_ERROR_FLAGS_lsb
const int FPGADataFormatUtilites::EVT_FTR_W2_ERROR_FLAGS_lsb = 0 |
◆ EVT_FTR_W3_CRC_bits
const int FPGADataFormatUtilites::EVT_FTR_W3_CRC_bits = 32 |
◆ EVT_FTR_W3_CRC_lsb
const int FPGADataFormatUtilites::EVT_FTR_W3_CRC_lsb = 0 |
◆ EVT_FTR_W3_WORD_COUNT_bits
const int FPGADataFormatUtilites::EVT_FTR_W3_WORD_COUNT_bits = 32 |
◆ EVT_FTR_W3_WORD_COUNT_lsb
const int FPGADataFormatUtilites::EVT_FTR_W3_WORD_COUNT_lsb = 32 |
◆ EVT_HDR_FLAG
const int FPGADataFormatUtilites::EVT_HDR_FLAG = 0xab |
◆ EVT_HDR_LWORDS
const int FPGADataFormatUtilites::EVT_HDR_LWORDS = 3 |
◆ EVT_HDR_W1_BCID_bits
const int FPGADataFormatUtilites::EVT_HDR_W1_BCID_bits = 12 |
◆ EVT_HDR_W1_BCID_lsb
const int FPGADataFormatUtilites::EVT_HDR_W1_BCID_lsb = 4 |
◆ EVT_HDR_W1_FLAG_bits
const int FPGADataFormatUtilites::EVT_HDR_W1_FLAG_bits = 8 |
◆ EVT_HDR_W1_FLAG_lsb
const int FPGADataFormatUtilites::EVT_HDR_W1_FLAG_lsb = 56 |
◆ EVT_HDR_W1_L0ID_bits
const int FPGADataFormatUtilites::EVT_HDR_W1_L0ID_bits = 40 |
◆ EVT_HDR_W1_L0ID_lsb
const int FPGADataFormatUtilites::EVT_HDR_W1_L0ID_lsb = 16 |
◆ EVT_HDR_W1_SPARE_bits
const int FPGADataFormatUtilites::EVT_HDR_W1_SPARE_bits = 4 |
◆ EVT_HDR_W1_SPARE_lsb
const int FPGADataFormatUtilites::EVT_HDR_W1_SPARE_lsb = 0 |
◆ EVT_HDR_W2_RUNNUMBER_bits
const int FPGADataFormatUtilites::EVT_HDR_W2_RUNNUMBER_bits = 32 |
◆ EVT_HDR_W2_RUNNUMBER_lsb
const int FPGADataFormatUtilites::EVT_HDR_W2_RUNNUMBER_lsb = 32 |
◆ EVT_HDR_W2_TIME_bits
const int FPGADataFormatUtilites::EVT_HDR_W2_TIME_bits = 32 |
◆ EVT_HDR_W2_TIME_lsb
const int FPGADataFormatUtilites::EVT_HDR_W2_TIME_lsb = 0 |
◆ EVT_HDR_W3_CRC_bits
const int FPGADataFormatUtilites::EVT_HDR_W3_CRC_bits = 32 |
◆ EVT_HDR_W3_CRC_lsb
const int FPGADataFormatUtilites::EVT_HDR_W3_CRC_lsb = 0 |
◆ EVT_HDR_W3_STATUS_bits
const int FPGADataFormatUtilites::EVT_HDR_W3_STATUS_bits = 32 |
◆ EVT_HDR_W3_STATUS_lsb
const int FPGADataFormatUtilites::EVT_HDR_W3_STATUS_lsb = 32 |
◆ M_HDR_FLAG
const int FPGADataFormatUtilites::M_HDR_FLAG = 0x55 |
◆ M_HDR_W1_FLAG_bits
const int FPGADataFormatUtilites::M_HDR_W1_FLAG_bits = 8 |
◆ M_HDR_W1_FLAG_lsb
const int FPGADataFormatUtilites::M_HDR_W1_FLAG_lsb = 56 |
◆ M_HDR_W1_MODID_bits
const int FPGADataFormatUtilites::M_HDR_W1_MODID_bits = 32 |
◆ M_HDR_W1_MODID_lsb
const int FPGADataFormatUtilites::M_HDR_W1_MODID_lsb = 24 |
◆ M_HDR_W1_SPARE_bits
const int FPGADataFormatUtilites::M_HDR_W1_SPARE_bits = 24 |
◆ M_HDR_W1_SPARE_lsb
const int FPGADataFormatUtilites::M_HDR_W1_SPARE_lsb = 0 |
◆ PIXEL_EF_RDO_COL_bits
const int FPGADataFormatUtilites::PIXEL_EF_RDO_COL_bits = 10 |
◆ PIXEL_EF_RDO_COL_lsb
const int FPGADataFormatUtilites::PIXEL_EF_RDO_COL_lsb = 43 |
◆ PIXEL_EF_RDO_ID_bits
const int FPGADataFormatUtilites::PIXEL_EF_RDO_ID_bits = 13 |
◆ PIXEL_EF_RDO_ID_lsb
const int FPGADataFormatUtilites::PIXEL_EF_RDO_ID_lsb = 25 |
◆ PIXEL_EF_RDO_LAST_bits
const int FPGADataFormatUtilites::PIXEL_EF_RDO_LAST_bits = 1 |
◆ PIXEL_EF_RDO_LAST_lsb
const int FPGADataFormatUtilites::PIXEL_EF_RDO_LAST_lsb = 63 |
◆ PIXEL_EF_RDO_LVL1_bits
const int FPGADataFormatUtilites::PIXEL_EF_RDO_LVL1_bits = 1 |
◆ PIXEL_EF_RDO_LVL1_lsb
const int FPGADataFormatUtilites::PIXEL_EF_RDO_LVL1_lsb = 38 |
◆ PIXEL_EF_RDO_ROW_bits
const int FPGADataFormatUtilites::PIXEL_EF_RDO_ROW_bits = 10 |
◆ PIXEL_EF_RDO_ROW_lsb
const int FPGADataFormatUtilites::PIXEL_EF_RDO_ROW_lsb = 53 |
◆ PIXEL_EF_RDO_SPARE_bits
const int FPGADataFormatUtilites::PIXEL_EF_RDO_SPARE_bits = 25 |
◆ PIXEL_EF_RDO_SPARE_lsb
const int FPGADataFormatUtilites::PIXEL_EF_RDO_SPARE_lsb = 0 |
◆ PIXEL_EF_RDO_TOT_bits
const int FPGADataFormatUtilites::PIXEL_EF_RDO_TOT_bits = 4 |
◆ PIXEL_EF_RDO_TOT_lsb
const int FPGADataFormatUtilites::PIXEL_EF_RDO_TOT_lsb = 39 |
◆ STRIP_EF_RDO_CHIPID_bits
const int FPGADataFormatUtilites::STRIP_EF_RDO_CHIPID_bits = 4 |
◆ STRIP_EF_RDO_CHIPID_lsb
const int FPGADataFormatUtilites::STRIP_EF_RDO_CHIPID_lsb = 27 |
◆ STRIP_EF_RDO_CLUSTER_MAP_bits
const int FPGADataFormatUtilites::STRIP_EF_RDO_CLUSTER_MAP_bits = 3 |
◆ STRIP_EF_RDO_CLUSTER_MAP_lsb
const int FPGADataFormatUtilites::STRIP_EF_RDO_CLUSTER_MAP_lsb = 16 |
◆ STRIP_EF_RDO_ID_bits
const int FPGADataFormatUtilites::STRIP_EF_RDO_ID_bits = 13 |
◆ STRIP_EF_RDO_ID_lsb
const int FPGADataFormatUtilites::STRIP_EF_RDO_ID_lsb = 3 |
◆ STRIP_EF_RDO_LAST_bits
const int FPGADataFormatUtilites::STRIP_EF_RDO_LAST_bits = 1 |
◆ STRIP_EF_RDO_LAST_lsb
const int FPGADataFormatUtilites::STRIP_EF_RDO_LAST_lsb = 31 |
◆ STRIP_EF_RDO_SPARE_bits
const int FPGADataFormatUtilites::STRIP_EF_RDO_SPARE_bits = 3 |
◆ STRIP_EF_RDO_SPARE_lsb
const int FPGADataFormatUtilites::STRIP_EF_RDO_SPARE_lsb = 0 |
◆ STRIP_EF_RDO_STRIP_NUM_bits
const int FPGADataFormatUtilites::STRIP_EF_RDO_STRIP_NUM_bits = 8 |
◆ STRIP_EF_RDO_STRIP_NUM_lsb
const int FPGADataFormatUtilites::STRIP_EF_RDO_STRIP_NUM_lsb = 19 |
setEventNumber setTimeStamp bcid
def time(flags, cells_name, *args, **kw)