ATLAS Offline Software
Menu_Physics_pp_run3_v1_inputs.py
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1 # Copyright (C) 2002-2022 CERN for the benefit of the ATLAS collaboration
2 
3 from collections import OrderedDict as odict
4 
5 from ..Base.L1MenuFlags import L1MenuFlags
6 from ..Base.MenuConfObj import TopoMenuDef
7 
8 
9 def defineInputsMenu():
10 
11  ctpinBoards = odict() # Ctpin/Slot9 (CTPCAL, NIM1, NIM2)
12  topoBoards = odict() # Topo1, Topo2, Topo3
13  muctpiBoard = odict() # MuCTPi
14 
15 
16  #-----------------------------------
17  # SLOT 9 / CON 1 (CTPCal, NIM1,NIM2)
18  # https://twiki.cern.ch/twiki/bin/view/Atlas/LevelOneCentralTriggerSetup#CTPIN_Slot_9
19  #-----------------------------------
20  ctpinBoards["Ctpin9"] = odict()
21  ctpinBoards["Ctpin9"]["connectors"] = []
22  ctpinBoards["Ctpin9"]["connectors"] += [
23  {
24  "name" : "CTPCAL",
25  "format" : "multiplicity",
26  "nbitsDefault" : 1,
27  "type" : "ctpin",
28  "legacy" : False,
29  "thresholds" : [
30  'BCM_AtoC', 'BCM_CtoA', 'BCM_Wide', # 3 x 1-bit BCM
31  ('BCM_Comb',3), # 1x 3-bit BCM
32  'BCM6', 'BCM7', 'BCM8', # 2-hit BCM, for Run 3. 8 is not used
33  (None, 6),
34  'BMA0', 'BMA1', # 2x BMA demonstrator
35  'BPTX0','BPTX1', # 2x BPTX
36  'LUCID_A', 'LUCID_C', # 2x LUCID
37  (None,4),
38  'ZDC_0', 'ZDC_1', 'ZDC_2', # 3x ZDC
39  'CAL0','CAL1','CAL2', # 3 x CALREQ
40  ]
41  },
42  {
43  "name" : "NIM1",
44  "format" : "multiplicity",
45  "nbitsDefault" : 1,
46  "type" : "ctpin",
47  "legacy" : False,
48  "thresholds" : [
49  'MBTS_A0', 'MBTS_A1', 'MBTS_A2', 'MBTS_A3', 'MBTS_A4' , 'MBTS_A5', 'MBTS_A6', 'MBTS_A7', 'MBTS_A8', 'MBTS_A9', 'MBTS_A10', 'MBTS_A11',
50  'MBTS_A12', 'MBTS_A13', 'MBTS_A14', 'MBTS_A15', # 16x MBTSSI
51  ('MBTS_A',3), # 1x MBTS_A
52  'NIML1A', # L1A for CTP monitoring itself
53  'NIMLHCF', # LHCF
54  'AFP_NSA', 'AFP_FSA', 'AFP_FSA_TOF_T0', 'AFP_FSA_TOF_T1', 'AFP_FSA_TOF_T2', 'AFP_FSA_TOF_T3', # 2xAFP
55  'BMA2', 'BMA3', # 2x BMA demonstrator
56  ]
57  },
58  {
59  "name" : "NIM2",
60  "format" : "multiplicity",
61  "nbitsDefault" : 1,
62  "type" : "ctpin",
63  "legacy" : False,
64  "thresholds" : [
65  'MBTS_C0', 'MBTS_C1', 'MBTS_C2', 'MBTS_C3', 'MBTS_C4', 'MBTS_C5', 'MBTS_C6', 'MBTS_C7', 'MBTS_C8', 'MBTS_C9', 'MBTS_C10', 'MBTS_C11',
66  'MBTS_C12', 'MBTS_C13', 'MBTS_C14', 'MBTS_C15', # 16x MBTSSI
67  ('MBTS_C',3), # 1x MBTS_C
68  'NIMTGC', # TGC
69  'NIMRPC', # RPC
70  'NIMTRT', # TRT
71  'AFP_NSC', 'AFP_FSC', 'AFP_FSC_TOF_T0', 'AFP_FSC_TOF_T1', 'AFP_FSC_TOF_T2', 'AFP_FSC_TOF_T3' # 2xAFP
72  ]
73  }
74  ]
75 
76 
77  #
78  # new topo board for multiplicities
79  #
80  topoBoards["Topo1"] = odict([("connectors",[])])
81  topoBoards["Topo1"]["connectors"].append({ # first optical connector
82  "name" : "Topo1Opt0",
83  "format" : "multiplicity",
84  "nbitsDefault" : 2,
85  "type" : "optical",
86  "legacy" : False,
87  "thresholds" : [ # Topo1A: eFex EM, eFex TAU, gJ, gLJ
88  # eEM thresholds for commissioning
89  ('eEM5',3), ('eEM7',3), ('eEM9',3), ('eEM10L',3),
90 
91  (None,3), (None,3), (None,3), (None,3),
92 
93  'eEM12L', 'eEM15', 'eEM18', 'eEM18L', 'eEM18M',
94  'eEM22M', 'eEM24L',
95  #beam splashes
96  'eEM22A', 'eEM22C',
97  #ATR-26333, adding eEM12, potentially more efficient than eEM12L in central HI collisions
98  'eEM12',
99  # variable eEM thresholds
100  'eEM24VM', 'eEM26', 'eEM26L', 'eEM26M', 'eEM26T', 'eEM28M', 'eEM40L',
101  #ATR-26979, eEMSPARE1 was replaced by eEM1, eEMSPARE2 was replaced by eEM2, decrement other eEMSPARE thresholds
102  'eEM1', 'eEM2',
103 
104  # eEM thresholds for production
105  'eEMSPARE1',
106 
107  ('ZeroBiasA', 1)
108  ],
109 
110  })
111 
112  topoBoards["Topo1"]["connectors"].append({ # second optical connector
113  "name" : "Topo1Opt1",
114  "format" : "multiplicity",
115  "nbitsDefault" : 2,
116  "type" : "optical",
117  "fpga" : 0,
118  "legacy" : False,
119  "thresholds" : [ # Topo1A: eFex EM, eFex TAU, gJ, gLJ
120  # eTAU thresholds for commissioning
121  ('eTAU12',3), ('eTAU20',3), ('eTAU1',3),
122 
123  (None,3),
124 
125  'eTAU20L', 'eTAU20M', 'eTAU30', 'eTAU30M',
126  'eTAU35', 'eTAU35M', 'eTAU40HM','eTAU60', 'eTAU80', 'eTAU140',
127 
128  # eTAU thresholds for production
129  #'eTAUSPARE6', 'eTAUSPARE7',
130 
131  None, None,
132 
133  # gLJ thresholds for commissioning
134  'gLJ80p0ETA25', 'gLJ100p0ETA25', 'gLJ140p0ETA25', 'gLJ160p0ETA25',
135 
136  # gLJ thresholds for production
137  'gLJSPARE1', 'gLJSPARE2', 'gLJSPARE3', 'gLJSPARE4',
138 
139  None,
140 
141  # gJ thresholds for commissioning
142  ('gJ20p0ETA25',3), ('gJ20p25ETA49',3), ('gJSPARE1',3),
143 
144  (None,3),
145 
146  'gJ50p0ETA25', 'gJ100p0ETA25',
147  'gJ400p0ETA25',
148 
149  ]
150  })
151 
152  topoBoards["Topo1"]["connectors"].append({ # third optical connector
153  "name" : "Topo1Opt2",
154  "format" : "multiplicity",
155  "nbitsDefault" : 2,
156  "type" : "optical",
157  "fpga" : 1,
158  "legacy" : False,
159  "thresholds" : [ # Topo1B: jFex small-R jet, jFex large-R jet, combined eFex/jFex TAU, gFex+jFex EX, gFex+jFex SumET, jFex TAU
160  # jJ thresholds for commissioning
161  ('jJ20',3), ('jJ30',3), ('jJ30p0ETA25',3), ('jJ40',3), ('jJ40p0ETA25',3),
162  ('jJ50',3), ('jJ55',3), ('jJ55p0ETA23',3), ('jJ60',3),
163  ('jJSPARE1',3), ('jJSPARE2',3),
164 
165  (None,3),
166 
167  'jJ70p0ETA23', 'jJ80', 'jJ80p0ETA25', 'jJ85p0ETA21', 'jJ90', 'jJ125',
168  'jJ140', 'jJ160', 'jJ180', 'jJ500',
169 
170  'jJ15p30ETA49','jJ20p30ETA49',
171  'jJ40p30ETA49', 'jJ50p30ETA49', 'jJ60p30ETA49', 'jJ90p30ETA49', 'jJ125p30ETA49',
172 
173  # jJ thresholds for production
174  'jJSPARE3', 'jJSPARE4',
175 
176  None, None,
177 
178  # jLJ thresholds for commissioning
179  'jLJ80', 'jLJ120', 'jLJ140', 'jLJ180',
180 
181  # jLJ thresholds for production
182  'jLJ60', 'jLJ100', 'jLJ160', 'jLJ200',
183 
184  ]
185  })
186 
187  topoBoards["Topo1"]["connectors"].append({ # fourth optical connector
188  "name" : "Topo1Opt3",
189  "format" : "multiplicity",
190  "nbitsDefault" : 2,
191  "type" : "optical",
192  "fpga" : 1,
193  "legacy" : False,
194  "thresholds" : [ # Topo1B: jFex small-R jet, jFex large-R jet, combined eFex/jFex TAU, gFex+jFex EX, gFex+jFex SumET, jFex TAU
195  # jTAU thresholds for commissioning
196  ('jTAU20',3),
197 
198  (None,3),
199 
200  'jTAU30', 'jTAU30M',
201  # jTAU thresholds for production
202  'jTAU1',
203 
204  None,
205 
206  # cTAU thresholds for commissioning
207  ('cTAU12M',3), ('cTAU20M',3),# ('cTAUSPARE1',3),
208  (None,3),
209 
210  'cTAU30M', 'cTAU35M',
211  # cTAU thresholds for production
212  'cTAUSPARE2',
213 
214  None,
215 
216  # jEM thresholds for commissioning
217  'jEM20', 'jEM20M',
218  # jEM thresholds for production
219  'jEMSPARE1',
220 
221  # LAr saturation for Phase-I
222  ('LArSaturation',1),
223  # ZeroBias Topo Algo
224  ('ZeroBiasB', 1),
225 
226  # (None,1),
227 
228  # energy thresholds
229  # commissioning
230  # jXE
231  ('jXE60',1), ('jXE70',1), ('jXE80',1), ('jXE90',1), ('jXE100',1), ('jXE110',1), ('jXE120',1), ('jXE500',1),
232  # gXE
233  #('gXERHO70',1), ('gXERHO100',1),
234  ('gXENC70',1), ('gXENC100',1),
235  ('gXEJWOJ60',1), ('gXEJWOJ70',1), ('gXEJWOJ80',1), ('gXEJWOJ100',1), ('gXEJWOJ110',1), ('gXEJWOJ120',1), ('gXEJWOJ500',1),
236  # gTE
237  ('gTE200',1),
238 
239  # MHT
240  ('gMHT500',1),
241 
242  # test thresholds
243  ('jXEC100',1),
244  ('jTE200',1), ('jTEC200',1), ('jTEFWD100',1), ('jTEFWDA100',1), ('jTEFWDC100',1),
245  # additional heavy ion jTE items
246  ('jTE3',1), ('jTE4',1), ('jTE10',1), ('jTE5',1), ('jTE20',1), ('jTE50',1),
247  ('jTE100',1) , ('jTE600',1), ('jTE1500',1), ('jTE3000',1), ('jTE10000',1),
248  ('jTEFWDA1',1), ('jTEFWDC1',1), ('jTEFWDA5',1), ('jTEFWDC5',1),
249 
250  # spare energy thresholds for commissioning
251  ('jXESPARE1',1), ('jXESPARE2',1), ('jXESPARE3',1), ('jXESPARE4',1), ('jXESPARE5',1), ('jXESPARE6',1), ('jXESPARE7',1), ('jXESPARE8',1),
252 
253  # production
254  # decrement jXESPARE for additional heavy ion jTE thresholds
255  #('jXESPARE9',1), ('jXESPARE10',1), ('jXESPARE11',1), ('jXESPARE12',1), ('jXESPARE13',1),
256  #('jXESPARE14',1),
257 
258  ]
259  })
260 
261  topoBoards["Topo2"] = odict()
262  topoBoards["Topo2"]["connectors"] = []
263  topoBoards["Topo2"]["connectors"].append({
264  "name" : "Topo2El",
265  "format" : "topological",
266  "type" : "electrical",
267  "legacy" : False,
268  "algorithmGroups" : [
269  {
270  "fpga" : 0,
271  "clock" : 0,
272  "algorithms" : [
273  TopoMenuDef( '2INVM9-0DR15-MU5VFab-MU3Vab', outputbits = 0 ), # BLS
274  TopoMenuDef( '2INVM9-0DR15-2MU3Vab', outputbits = 1 ), # BLS
275  TopoMenuDef( 'INVM_DR_2MU5VFab', outputbits = (2,3), outputlines = [ '2INVM9-2DR15-2MU5VFab', # BLS
276  '8INVM15-0DR22-2MU5VFab' ] ), # BLS
277  TopoMenuDef( '5DETA99-5DPHI99-2MU3VFab', outputbits = 4 ), # Low-mass DY
278  TopoMenuDef( '5DETA99-5DPHI99-MU5VFab-MU3Vab', outputbits = 5 ), # Low-mass DY
279  TopoMenuDef( '5DETA99-5DPHI99-2MU5VFab', outputbits = 6 ), # Low-mass DY
280  TopoMenuDef( 'DR_2MU5VFab', outputbits = (7,8) , outputlines = [ '0DR15-2MU5VFab' , # LVF
281  '10DR99-2MU5VFab'] ), # Msonly Narrow Scan
282  TopoMenuDef( '8INVM15-0DR22-CMU5VFab-CMU3Vab', outputbits = 9 ), # BLS
283  TopoMenuDef( 'LATE-MU10s1', outputbits = 10 ),
284  TopoMenuDef( 'INVM_DR_2MU3VFab', outputbits = (11,12), outputlines = ['2INVM9-0DR15-2MU3VFab',
285  '7INVM11-25DR99-2MU3VFab'] ), #BLS, ATR-21566
286  ]
287  },
288 
289  {
290  "fpga" : 0,
291  "clock" : 1,
292  "algorithms" : [
293  TopoMenuDef( '0INVM10-3MU3Vab', outputbits = 0 ), # BLS
294  TopoMenuDef( '0DR04-MU3Vab-CjJ40ab', outputbits = 1 ), # Bjet, TODO: not a primary
295  TopoMenuDef( '0DR04-MU5VFab-CjJ80ab', outputbits = 2 ), # Bjet, TODO: not a primary
296  TopoMenuDef( '2DISAMB_jJ55ab_DR_eTAU_eTAU', outputbits = (3,4), outputlines = [ '2DISAMB-jJ55ab-0DR25-eTAU30ab-eTAU20ab',
297  '2DISAMB-jJ55ab-0DR28-eTAU30ab-eTAU20ab' ]),
298  TopoMenuDef( 'DR_eTAU30ab_eTAU20ab', outputbits = (5,6), outputlines = [ '0DR25-eTAU30ab-eTAU20ab',
299  '0DR28-eTAU30ab-eTAU20ab' ]),
300  TopoMenuDef( '2DISAMB-jJ55ab-0DR28-eTAU30abm-eTAU20abm', outputbits = 7 ),
301  TopoMenuDef( '0DR28-eTAU30abm-eTAU20abm', outputbits = 8 ),
302  TopoMenuDef( '0INVM10-3MU3VFab', outputbits = 9 ), # BLS
303  TopoMenuDef( '2DISAMB-jJ40ab-0DR10-eTAU20ab-eTAU12ab', outputbits = 10),
304  ]
305  },
306 
307  {
308  "fpga" : 1,
309  "clock" : 0,
310  "algorithms" : [
311  TopoMenuDef( 'INVM_DPHI_eEMsm6', outputbits = (0,1), outputlines = [ '0INVM70-27DPHI32-eEM12sm1-eEM12sm6',
312  '0INVM70-27DPHI32-eEM15sm1-eEM15sm6' ] ),
313 
314  TopoMenuDef( 'ZEE-eEM24sm2', outputbits = 2 ),
315  TopoMenuDef( '0DR03-eEM9ab-CjJ40ab', outputbits = 3 ),
316  TopoMenuDef( 'INVM_eEMs6', outputbits = (4,5), outputlines = [ '1INVM5-eEM9s1-eEMs6',
317  '1INVM5-eEM15s1-eEMs6'] ),
318  TopoMenuDef( '27DPHI32-eEMs1-eEMs6', outputbits = 6 ),
319  TopoMenuDef( '0INVM70-27DPHI32-eEM9s1-eEM9s6', outputbits = 7 ),
320  TopoMenuDef( '0INVM70-27DPHI32-eEM9sl1-eEM9sl6', outputbits = 8 ),
321  TopoMenuDef( '0INVM9-eEM9ab-eEMab', outputbits = 9 ),
322  TopoMenuDef( 'INVM_BOOSTDR_Ranges_eEM12sl6', outputbits = (10,11), outputlines = ['0INVM30-2DR15-eEM12sl1-eEM12sl6',
323  '25INVM70-13DR25-eEM12sl1-eEM12sl6']),
324 
325  ]
326  },
327 
328  {
329  "fpga" : 1,
330  "clock" : 1,
331  "algorithms" : [
332  TopoMenuDef( 'jINVM_DPHI_NFF', outputbits = (0,3), outputlines = ['400INVM-0DPHI26-jJ60s6-AjJ50s6',
333  '400INVM-0DPHI24-jJ60s6-AjJ50s6',
334  '400INVM-0DPHI22-jJ60s6-AjJ50s6',
335  '400INVM-0DPHI20-jJ60s6-AjJ50s6'] ),
336  TopoMenuDef( 'jINVM', outputbits = (4,7), outputlines = ['300INVM-AjJ60s6-AjJ50s6',
337  '400INVM-AjJ60s6-AjJ50s6',
338  '500INVM-AjJ60s6-AjJ50s6',
339  '700INVM-AjJ60s6-AjJ50s6'] ),
340  TopoMenuDef( 'jINVM_DPHI', outputbits = (8,11), outputlines = ['400INVM-0DPHI26-AjJ60s6-AjJ50s6',
341  '400INVM-0DPHI24-AjJ60s6-AjJ50s6',
342  '400INVM-0DPHI22-AjJ60s6-AjJ50s6',
343  '400INVM-0DPHI20-AjJ60s6-AjJ50s6'] ),
344  TopoMenuDef( '0DPHI10-jXE40delay-jJ40s', outputbits = 12),
345  ]
346  }
347  ]
348  })
349 
350  topoBoards["Topo3"] = odict()
351  topoBoards["Topo3"]["connectors"] = []
352  topoBoards["Topo3"]["connectors"].append({
353  "name" : "Topo3El",
354  "format" : "topological",
355  "type" : "electrical",
356  "legacy" : False,
357  "algorithmGroups" : [
358  {
359  "fpga" : 0,
360  "clock" : 0,
361  "algorithms" : [
362  TopoMenuDef( 'HT190-jJ40s5pETA21', outputbits = 0 ),
363  TopoMenuDef( 'jINVM_NFF', outputbits = (1,4), outputlines = ['300INVM-jJ60s6-AjJ50s6',
364  '400INVM-jJ60s6-AjJ50s6',
365  '500INVM-jJ60s6-AjJ50s6',
366  '700INVM-jJ60s6-AjJ50s6',] ), # TODO: needed?
367  TopoMenuDef( 'HT150-jJ50s5pETA32', outputbits = 5 ),
368  TopoMenuDef( '400INVM-AjJ60s6pETA32-AjJ50s6p30ETA49', outputbits = 6 ),
369  TopoMenuDef( 'SC111-CjJ40abpETA26', outputbits = 7 ),
370  TopoMenuDef( '0DETA20-jJ90s1-jJs2', outputbits = 8 ),
371  TopoMenuDef( '100RATIO-0MATCH-eTAU40si2-eEMall', outputbits = 9 ),
372  TopoMenuDef( 'NOT-0MATCH-eTAU40si1-eEMall', outputbits = 10),
373  TopoMenuDef( '0DETA24-eTAU30s2-eTAU12s2', outputbits = 11),
374  TopoMenuDef( '0DETA24-4DPHI99-eTAU30ab-eTAU12ab', outputbits = 12),
375 
376  ]
377  },
378 
379  {
380  "fpga" : 0,
381  "clock" : 1,
382  "algorithms" : [
383  TopoMenuDef( 'KF-jXE-AjJall', outputbits = (0,5), outputlines = [ 'KF-jXE40-AjJall',
384  'KF-jXE50-AjJall',
385  'KF-jXE55-AjJall',
386  'KF-jXE60-AjJall',
387  'KF-jXE65-AjJall',
388  'KF-jXE75-AjJall'] ),
389  TopoMenuDef( 'ZAFB_DPHI', outputbits = (6,7), outputlines = [ '60INVM-04DPHI32-eEM18abm-jEM20s625ETA49',
390  '60INVM-25DPHI32-eEM18abm-jEM20s625ETA49'] ),
391  TopoMenuDef( 'CEP_CjJ', outputbits = (8,9), outputlines = [ 'CEP-CjJ90s6',
392  'CEP-CjJ100s6'] ),
393  ]
394  },
395 
396  {
397  "fpga" : 1,
398  "clock" : 0,
399  "algorithms" : [
400  TopoMenuDef( 'INVM_DR_eEM_MU', outputbits = (0,1), outputlines = ['0INVM10-0DR15-eEM10abl-MU8Fab',
401  '0INVM10-0DR15-eEM15abl-MU5VFab' ]) #LFV
402 
403  ]
404  },
405 
406  {
407  "fpga" : 1,
408  "clock" : 1,
409  "algorithms" : [
410  TopoMenuDef( '7INVM14-MU5VFab-MU3VFab', outputbits = 0 ), #BLS, ATR-22782
411  TopoMenuDef( '7INVM14-2MU3Vab', outputbits = 1 ), #BLS, ATR-22782
412  TopoMenuDef( 'INVM_2MU3VFab', outputbits = (2,3), outputlines = ['7INVM14-2MU3VFab',
413  '7INVM22-2MU3VFab' ] ), #BLS, ATR-21566
414  TopoMenuDef( '7INVM22-MU5VFab-MU3VFab', outputbits = 4 ), #BLS, ATR-21566
415  TopoMenuDef ( '7INVM22_DR_2MU3Vab', outputbits = (5,6), outputlines = ['7INVM22-0DR20-2MU3Vab',
416  '7INVM22-0DR12-2MU3Vab']),
417  TopoMenuDef( '2INVM9-0DR15-C-MU5VFab-MU3Vab', outputbits = 7 ), #BLS, test
418  TopoMenuDef( '0INVM10C-3MU3Vab', outputbits = 8), #BLS, test
419  TopoMenuDef( '7INVM14-0DR25-MU5VFab-MU3VFab', outputbits = 9), #BLS
420  TopoMenuDef( '7INVM22-0DR20-2MU3VFab', outputbits = 10), #BLS, ATR-21566
421  ]
422  }
423  ]
424  })
425 
426  muctpiBoard["MuCTPi"] = odict()
427  muctpiBoard["MuCTPi"]["connectors"] = []
428  muctpiBoard["MuCTPi"]["connectors"].append({
429  "name" : "MuCTPiOpt0",
430  "format" : "multiplicity",
431  "nbitsDefault" : 2,
432  "type" : "optical",
433  "legacy" : False,
434  "thresholds" : [
435  ('MU3V',3), ('MU3VF',3), ('MU3VC',3), ('MU3EOF',3), ('MU5VF',3),
436  'MU8F', 'MU8VF', 'MU8FC', 'MU8FH', 'MU8VFC', 'MU9VF', 'MU9VFC', 'MU12FCH',
437  'MU14FCH', 'MU14FCHR', 'MU15VFCH', 'MU15VFCHR', 'MU18VFCH', 'MU20VFC',
438  'MU4BO', 'MU4BOM', 'MU10BO', 'MU10BOM', 'MU12BOM',
439  'MU8EOF', 'MU14EOF',
440  # 57 bits for standard muon thresholds
441  (None,7),
442  # 64th bit for NSW monitoring
443  ('NSWMon', 1)
444  ]
445 
446  })
447 
448  muctpiBoard["MuCTPi"]["connectors"].append({
449  "name" : "MuCTPiEl",
450  "format" : "topological",
451  "type" : "electrical",
452  "legacy" : False,
453  "algorithmGroups" : [
454  {
455  "fpga" : 0,
456  "clock" : 0,
457  "algorithms" : []
458  },
459  {
460  "fpga" : 0,
461  "clock" : 1,
462  "algorithms" : [
463  TopoMenuDef( "MUCTP-0DR15-2MU5VFab", outputbits = 0 ),
464  ]
465  },
466  {
467  "fpga" : 1,
468  "clock" : 0,
469  "algorithms" : []
470  },
471  {
472  "fpga" : 1,
473  "clock" : 1,
474  "algorithms" : []
475  }
476  ]
477  })
478 
479 
480  L1MenuFlags.boards().clear()
481 
482  L1MenuFlags.boards().update( topoBoards ) # Topo1, Topo2, Topo3
483 
484  L1MenuFlags.boards().update( muctpiBoard ) # MuCTPi
485 
486  L1MenuFlags.boards().update( ctpinBoards ) # CTPIN/Slot9 NIM1, NIM2, CALREQ
487 
488  #----------------------------------------------
489 
490  def remapThresholds():
491  # remap thresholds. TODO: add checks in case the remap does not fulfill HW constraints?
492  for boardName, boardDef in L1MenuFlags.boards().items():
493  if "connectors" in boardDef:
494  for c in boardDef["connectors"]:
495  if "thresholds" in c:
496  thresholdsToRemove = []
497  for thrIndex, thrName in enumerate(c["thresholds"]):
498  nBits = 0
499  if type(thrName)==tuple:
500  (thrName,nBits) = thrName
501  if thrName in L1MenuFlags.ThresholdMap():
502  if (L1MenuFlags.ThresholdMap()[thrName] != ''):
503  if nBits > 0:
504  c["thresholds"][thrIndex] = (L1MenuFlags.ThresholdMap()[thrName],nBits)
505  else:
506  c["thresholds"][thrIndex] = L1MenuFlags.ThresholdMap()[thrName]
507  else:
508  thresholdsToRemove.append(thrIndex)
509  for i in reversed(thresholdsToRemove):
510  del c["thresholds"][i]
511 
512  #----------------------------------------------
513 
514  remapThresholds()
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