ATLAS Offline Software
Menu_Physics_pp_run3_v1_inputs_legacy.py
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1 # Copyright (C) 2002-2019 CERN for the benefit of the ATLAS collaboration
2 
3 from collections import OrderedDict as odict
4 
5 from ..Base.L1MenuFlags import L1MenuFlags
6 from ..Base.MenuConfObj import TopoMenuDef
7 from ..Config.LegacyTopoMergerMap import createMergerBoard
8 
9 def defineLegacyInputsMenu():
10 
11  legacyBoards = odict()
12  legacyTopoBoards = odict()
13 
14  #----------------------------------------
15  # SLOT 7 / CON 0-3 (EM1, EM2, TAU1, TAU2)
16  # https://twiki.cern.ch/twiki/bin/view/Atlas/LevelOneCentralTriggerSetup#CTPIN_Slot_7
17  #----------------------------------------
18  legacyBoards["Ctpin7"] = odict()
19  legacyBoards["Ctpin7"]["legacy"] = True
20  legacyBoards["Ctpin7"]["connectors"] = []
21  legacyBoards["Ctpin7"]["connectors"] += [
22  {
23  "name" : "EM1",
24  "format" : "multiplicity",
25  "nbitsDefault" : 3,
26  "type" : "ctpin",
27  "legacy" : True,
28  "thresholds" : [ 'EM3', 'EM7', 'EM8VH', 'EM10VH', 'EM12', 'EM15', 'EM15VH', 'EM15VHI' ],
29  "zeroBias" : "ZB_EM15"
30  },
31  {
32  "name" : "EM2",
33  "format" : "multiplicity",
34  "nbitsDefault" : 3,
35  "type" : "ctpin",
36  "legacy" : True,
37  "thresholds" : [ 'EM18VHI', 'EM20VH', 'EM20VHI', 'EM22VH', 'EM22VHI', 'EM24VHI', 'EM24VHIM', 'EM30VHI' ]
38  },
39  {
40  "name" : "TAU1",
41  "format" : "multiplicity",
42  "nbitsDefault" : 3,
43  "type" : "ctpin",
44  "legacy" : True,
45  "thresholds" : [ 'HA5', 'HA8', 'HA12', 'HA12IL', 'HA12IM', 'HA15', 'HA20', 'HA20IL' ]
46  },
47 
48  {
49  "name" : "TAU2",
50  "format" : "multiplicity",
51  "nbitsDefault" : 3,
52  "type" : "ctpin",
53  "legacy" : True,
54  "thresholds" : [ 'HA20IM', 'HA25', 'HA25IM', 'HA30', 'HA40', 'HA60', 'HA90', 'HA100' ]
55  }
56  ]
57 
58 
59  #--------------------------------------
60  # SLOT 8 / CON 0 (JET1, JET2, EN1, EN2)
61  # https://twiki.cern.ch/twiki/bin/view/Atlas/LevelOneCentralTriggerSetup#CTPIN_Slot_8
62  #--------------------------------------
63  legacyBoards["Ctpin8"] = odict()
64  legacyBoards["Ctpin8"]["legacy"] = True
65  legacyBoards["Ctpin8"]["connectors"] = []
66  legacyBoards["Ctpin8"]["connectors"] += [
67  {
68  # 10 x 3-bit JET (can have multiplicity 4 or more)
69  "name" : "JET1",
70  "format" : "multiplicity",
71  "nbitsDefault" : 3,
72  "type" : "ctpin",
73  "legacy" : True,
74  "thresholds" : [
75  'J12', 'J12p0ETA25', 'J15', 'J15p0ETA25','J20', 'J25','J25p0ETA23','J30', # 8 x JETs and central jets
76  'J12p0ETA28', 'J20p0ETA49', # 2 x VBF
77  ]
78  },
79  {
80  # 15 x 2-bit JET (can have maximum multiplicity of 3) (SLOT 8, CON 1)
81  "name" : "JET2",
82  "format" : "multiplicity",
83  "nbitsDefault" : 2,
84  "type" : "ctpin",
85  "legacy" : True,
86  "thresholds" : [
87  'J35p0ETA23', 'J40p0ETA25', # 3 x central Jet
88  'J40', 'J50', 'J75', 'J85', 'J100', 'J120', 'J45p0ETA21', 'J400', # 6 jets + 1 central jet
89  'J15p31ETA49', 'J20p31ETA49', 'J30p31ETA49', 'J50p31ETA49', 'J75p31ETA49', # 6 x FJ
90  ]
91  },
92  {
93  # 24 x 1-bit thresholds
94  "name" : "EN1",
95  "format" : "multiplicity",
96  "nbitsDefault" : 1,
97  "type" : "ctpin",
98  "legacy" : True,
99  "thresholds" : [
100  'TE5', 'TE10', 'TE15', 'TE20', 'TE25', 'TE30', 'TE40', 'TE50', # 8 x TE
101  'XE10', 'XE20', 'XE25', 'XE30', 'XE35', 'XE40', 'XE45', 'XE50', # 8 x XE
102  'XS20', 'XS30', 'XS40', 'XS45', 'XS50', 'XS55', 'XS60', 'XS65', # 8 x XS
103  ]
104  },
105  {
106  # 8 x 1-bit thresholds
107  "name" : "EN2",
108  "format" : "multiplicity",
109  "nbitsDefault" : 1,
110  "type" : "ctpin",
111  "legacy" : True,
112  "thresholds" : [
113  'TE5p0ETA24', 'TE10p0ETA24', 'TE15p0ETA24', 'TE20p0ETA24', 'TE25p0ETA24', 'TE30p0ETA24', 'TE40p0ETA24', 'TE70p0ETA24', # 8 x TE
114  'XE55', 'XE60', 'XE65', 'XE70', 'XE75', 'XE80', 'XE150', 'XE300', # 8 x XE
115  ]
116  }
117  ]
118 
119 
120  #----------------
121  # Legacy L1TOPO 0
122  #----------------
123  legacyTopoBoards["LegacyTopo0"] = odict()
124  legacyTopoBoards["LegacyTopo0"]["legacy"] = True
125  legacyTopoBoards["LegacyTopo0"]["connectors"] = [
126  {
127  "name" : "LegacyTopo0",
128  "format" : "topological",
129  "type" : "electrical",
130  "legacy" : True,
131  "algorithmGroups" : [
132  {
133  "fpga" : 0,
134  "clock" : 0,
135  "algorithms" : [
136  TopoMenuDef( "INVM_AJ_HighMass", outputbits = (0,3), outputlines = [ "900INVM9999-AJ30s6-AJ20s6",
137  "800INVM9999-AJ30s6-AJ20s6",
138  "700INVM9999-AJ30s6-AJ20s6",
139  "500INVM9999-AJ30s6-AJ20s6" ] ),
140  TopoMenuDef( "INVM_AJ_LowMass", outputbits = (4,7), outputlines = [ "400INVM9999-AJ30s6-AJ20s6",
141  "300INVM9999-AJ30s6-AJ20s6",
142  "200INVM9999-AJ30s6-AJ20s6",
143  "100INVM9999-AJ30s6-AJ20s6" ] ),
144  TopoMenuDef( "0INVM9-EM7ab-EMab", outputbits = 8 ),
145  TopoMenuDef( "HT150-J20s5pETA31", outputbits = 9 ),
146  TopoMenuDef( "HT190-J15s5pETA21", outputbits = 10 ),
147  TopoMenuDef( "INVM_EMs6", outputbits = (11,13), outputlines = [ "1INVM5-EMs1-EMs6",
148  "1INVM5-EM7s1-EMs6",
149  "1INVM5-EM12s1-EMs6" ] ),
150  TopoMenuDef( "05MINDPHI-EM12s6-XE0", outputbits = 14 ),
151  TopoMenuDef( "400INVM9999-AJ30s6pETA31-AJ20s6p31ETA49", outputbits = 15 ),
152  ]
153  },
154  {
155  "fpga" : 0,
156  "clock" : 1,
157  "algorithms" : [
158  TopoMenuDef( "05MINDPHI-EM15s6-XE0", outputbits = 0 ),
159  TopoMenuDef( "25MT-EM12s6-XE0", outputbits = 1 ),
160  TopoMenuDef( "ZEE-EM20shi2", outputbits = 2 ),
161  TopoMenuDef( "35MT-EM15s6-XE0", outputbits = 3 ),
162  TopoMenuDef( "0DR03-EM7ab-CJ15ab", outputbits = 4 ),
163  TopoMenuDef( "10MINDPHI-J20s2-XE30", outputbits = 5 ),
164  TopoMenuDef( "10MINDPHI-J20s2-XE50", outputbits = 6 ),
165  TopoMenuDef( "100RATIO-0MATCH-TAU30si2-EMall", outputbits = 7 ),
166  TopoMenuDef( "NOT-0MATCH-TAU30si1-EMall", outputbits = 8 ),
167  TopoMenuDef( "LAR-EM20shi1", outputbits = 9 ),
168  TopoMenuDef( "LAR-J100s1", outputbits = 10 ),
169  TopoMenuDef( "NOT-02MATCH-EM10s1-AJj15allpETA49", outputbits = 11 ),
170  TopoMenuDef( "27DPHI32-EMs1-EMs6", outputbits = 12 ),
171  TopoMenuDef( "35MT-EM12s6-XE0", outputbits = 13 ),
172  TopoMenuDef( "15MINDPHI-EM12s6-XE0", outputbits = 14 ),
173  TopoMenuDef( "15MINDPHI-EM15s6-XE0", outputbits = 15 ),
174  ]
175  },
176  {
177  "fpga" : 1,
178  "clock" : 0,
179  "algorithms" : [
180  TopoMenuDef( "1DISAMB-EM15his2-TAU12abi-J25ab", outputbits = 2 ),
181  TopoMenuDef( "1DISAMB-J25ab-0DR28-EM15his2-TAU12abi", outputbits = 3 ),
182  TopoMenuDef( "2INVM9-2MU6ab", outputbits = 4 ),
183  TopoMenuDef( "2INVM8-ONEBARREL-MU6ab-MU4ab", outputbits = 6 ),
184  TopoMenuDef( "5DETA99-5DPHI99-MU6ab-MU4ab", outputbits = 8 ),
185  TopoMenuDef( "5DETA99-5DPHI99-2MU6ab", outputbits = 9 ),
186  TopoMenuDef( "1DISAMB-TAU20abi-TAU12abi-J25ab", outputbits = 10 ),
187  TopoMenuDef( "0DR28-MU10ab-TAU12abi", outputbits = 11 ),
188  TopoMenuDef( "0DETA20-0DPHI20-TAU20abi-TAU12abi", outputbits = 12 ),
189  TopoMenuDef( "DISAMB-0DR28-EM15his2-TAU12abi", outputbits = 15 ),
190  ]
191  },
192  {
193  "fpga" : 1,
194  "clock" : 1,
195  "algorithms" : [
196  TopoMenuDef( "DISAMB-30INVM-EM20his2-TAU12ab", outputbits = 0 ),
197  TopoMenuDef( "0DR22-2MU6ab", outputbits = 4 ),
198  TopoMenuDef( "7INVM15-2MU4ab", outputbits = 5 ),
199  TopoMenuDef( "0DR22-MU6ab-MU4ab", outputbits = 6 ),
200  TopoMenuDef( "0DR15-2MU4ab", outputbits = 7 ),
201  TopoMenuDef( "0DR24-2MU4ab", outputbits = 8 ),
202  TopoMenuDef( "0DR15-2MU6ab", outputbits = 9 ),
203  TopoMenuDef( "2INVM9-2MU4ab", outputbits = 10 ),
204  TopoMenuDef( "2INVM9-MU6ab-MU4ab", outputbits = 11 ),
205  TopoMenuDef( "INVM_NFF", outputbits = (12,15), outputlines = [ "600INVM9999-J30s6-AJ20s6",
206  "500INVM9999-J30s6-AJ20s6",
207  "400INVM9999-J30s6-AJ20s6",
208  "200INVM9999-J30s6-AJ20s6" ])
209  ]
210  }
211  ]
212  }
213  ]
214 
215  legacyTopoBoards["LegacyTopo1"] = odict()
216  legacyTopoBoards["LegacyTopo1"]["legacy"] = True
217  legacyTopoBoards["LegacyTopo1"]["connectors"] = [
218  {
219  "name" : "LegacyTopo1",
220  "format" : "topological",
221  "type" : "electrical",
222  "legacy" : True,
223  "algorithmGroups" : [
224  {
225  "fpga" : 0,
226  "clock" : 0,
227  "algorithms" : [
228  TopoMenuDef( "05MINDPHI-AJj10s6-XE0", outputbits = 0 ),
229  TopoMenuDef( "10MINDPHI-AJj10s6-XE0", outputbits = 1 ),
230  TopoMenuDef( "15MINDPHI-AJj10s6-XE0", outputbits = 2 ),
231  TopoMenuDef( "0DR04-MU4ab-CJ15ab", outputbits = 3 ),
232  TopoMenuDef( "0DR04-MU4ab-CJ20ab", outputbits = 4 ),
233  TopoMenuDef( "0DR04-MU4ab-CJ30ab", outputbits = 5 ),
234  TopoMenuDef( "0DR04-MU6ab-CJ20ab", outputbits = 6 ),
235  TopoMenuDef( "0DR04-MU6ab-CJ25ab", outputbits = 7 ),
236  TopoMenuDef( "10MINDPHI-CJ20ab-XE50", outputbits = 8 ),
237  TopoMenuDef( "0DR24-2CMU4ab", outputbits = 9 ),
238  TopoMenuDef( "FTK-J100s1", outputbits = 10 ),
239  TopoMenuDef( "MULT-CMU4ab", outputbits = (11,12), outputlines = [ "MULT-CMU4ab[0]",
240  "MULT-CMU4ab[1]" ] ),
241  TopoMenuDef( "MULT-CMU6ab", outputbits = (13,14), outputlines = [ "MULT-CMU6ab[0]",
242  "MULT-CMU6ab[1]" ] ),
243  TopoMenuDef( "FTK-MU10s1", outputbits = 15 ),
244  ]
245  },
246  {
247  "fpga" : 0,
248  "clock" : 1,
249  "algorithms" : [
250  TopoMenuDef( "0DETA04-EM8abi-MU10ab", outputbits = 3 ),
251  TopoMenuDef( "0DETA04-EM15abi-MUab", outputbits = 4 ),
252  TopoMenuDef( "0DR24-CMU4ab-MU4ab", outputbits = 5 ),
253  TopoMenuDef( "0DPHI03-EM8abi-MU10ab", outputbits = 6 ),
254  TopoMenuDef( "2INVM8-CMU4ab-MU4ab", outputbits = 7 ),
255  TopoMenuDef( "0DPHI03-EM15abi-MUab", outputbits = 8 ),
256  TopoMenuDef( "10MINDPHI-AJ20s2-XE50", outputbits = 9 ),
257  TopoMenuDef( "LATE-MU10s1", outputbits = 10 ),
258  TopoMenuDef( "SC111-CJ15abpETA26", outputbits = 11 ),
259  TopoMenuDef( "SC85-CJ15abpETA26", outputbits = 12 ),
260  TopoMenuDef( "FTK-EM20s1", outputbits = 13 ),
261  ]
262  },
263  {
264  "fpga" : 1,
265  "clock" : 0,
266  "algorithms" : [
267  TopoMenuDef( "KF-XE-AJall", outputbits = (0,5),outputlines = [ "KF-XE40-AJall",
268  "KF-XE50-AJall",
269  "KF-XE55-AJall",
270  "KF-XE60-AJall",
271  "KF-XE65-AJall",
272  "KF-XE75-AJall" ] ),
273  TopoMenuDef( "0MATCH-4AJ20pETA31-4AJj15pETA31", outputbits = 6 ),
274  TopoMenuDef( "HT190-AJ15allpETA21", outputbits = 7 ),
275  TopoMenuDef( "HT150-AJ20allpETA31", outputbits = 8 ),
276  TopoMenuDef( "HT150-AJj15allpETA49", outputbits = 9 ),
277  TopoMenuDef( "HT20-AJj15allpETA49", outputbits = 10 ),
278  TopoMenuDef( "0DETA20-J50s1-Js2", outputbits = 12 ),
279  TopoMenuDef( "05RATIO-XE0-HT0-AJj15allpETA49", outputbits = 13 ),
280  TopoMenuDef( "63DETA127-FJ20s1-FJ20s2", outputbits = 14 ),
281  TopoMenuDef( "90RATIO2-XE0-HT0-AJj15allpETA49", outputbits = 15 )
282  ]
283  },
284  {
285  "fpga" : 1,
286  "clock" : 1,
287  "algorithms" : [
288  TopoMenuDef( "250RATIO2-XE0-HT0-AJj15allpETA49", outputbits = 0 ),
289  TopoMenuDef( "10MINDPHI-J20ab-XE50", outputbits = 1 ),
290  TopoMenuDef( "0DR28-TAU20abi-TAU12abi", outputbits = 2 ),
291  TopoMenuDef( "1DISAMB-J25ab-0DR28-TAU20abi-TAU12abi", outputbits = 3 ),
292  TopoMenuDef( "1DISAMB-TAU12abi-J25ab", outputbits = 4 ),
293  TopoMenuDef( "0DR10-MU10ab-MU6ab", outputbits = 5 ),
294  TopoMenuDef( "2DR99-2MU4ab", outputbits = 6 ),
295  TopoMenuDef( "0DR34-2MU4ab", outputbits = 7 ),
296  TopoMenuDef( "2DR15-2MU6ab", outputbits = 8 ),
297  TopoMenuDef( "0DR15-MU6ab-MU4ab", outputbits = 9 ),
298  TopoMenuDef( "0DR25-TAU20abi-TAU12abi", outputbits = 10 ),
299  TopoMenuDef( "1DISAMB-J25ab-0DR25-TAU20abi-TAU12abi", outputbits = 11 ),
300  TopoMenuDef( "8INVM15-MU6ab-MU4ab", outputbits = 12 ),
301  TopoMenuDef( "8INVM15-2MU6ab", outputbits = 13 ),
302  TopoMenuDef( "2INVM8-2MU4ab", outputbits = 14 ),
303  TopoMenuDef( "2INVM8-MU6ab-MU4ab", outputbits = 15 ),
304  ]
305  }
306  ]
307  }
308  ]
309 
310 
311  L1MenuFlags.legacyBoards().clear()
312 
313  L1MenuFlags.legacyBoards().update( legacyBoards ) # EM1/2, TAU1/2, JET1/2, EN1/2
314 
315  L1MenuFlags.legacyBoards().update( createMergerBoard( legacyTopoBoards["LegacyTopo0"], legacyTopoBoards["LegacyTopo1"] ) )
316 
317  L1MenuFlags.legacyBoards().update( legacyTopoBoards) # LegacyTopo0/1
318 
python.L1.Base.MenuConfObj.TopoMenuDef
Definition: MenuConfObj.py:6
python.L1.Config.LegacyTopoMergerMap.createMergerBoard
def createMergerBoard(legacyBoard0, legacyBoard1)
Definition: LegacyTopoMergerMap.py:48
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Definition: dqt_zlumi_pandas.py:42
VKalVrtAthena::varHolder_detail::clear
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Definition: NtupleVars.h:48
python.L1.Menu.Menu_Physics_pp_run3_v1_inputs_legacy.defineLegacyInputsMenu
def defineLegacyInputsMenu()
Definition: Menu_Physics_pp_run3_v1_inputs_legacy.py:9
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