ATLAS Offline Software
Menu_Physics_HI_run3_v1_inputs_legacy.py
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1 # Copyright (C) 2002-2019 CERN for the benefit of the ATLAS collaboration
2 
3 from collections import OrderedDict as odict
4 
5 from ..Base.L1MenuFlags import L1MenuFlags
6 from ..Base.MenuConfObj import TopoMenuDef
7 from ..Config.LegacyTopoMergerMap import createMergerBoard
8 
9 def defineLegacyInputsMenu():
10 
11  legacyBoards = odict()
12  legacyTopoBoards = odict()
13 
14  #----------------------------------------
15  # SLOT 7 / CON 0-3 (EM1, EM2, TAU1, TAU2)
16  # https://twiki.cern.ch/twiki/bin/view/Atlas/LevelOneCentralTriggerSetup#CTPIN_Slot_7
17  #----------------------------------------
18  legacyBoards["Ctpin7"] = odict()
19  legacyBoards["Ctpin7"]["legacy"] = True
20  legacyBoards["Ctpin7"]["connectors"] = []
21  legacyBoards["Ctpin7"]["connectors"] += [
22  {
23  "name" : "EM1",
24  "format" : "multiplicity",
25  "nbitsDefault" : 3,
26  "type" : "ctpin",
27  "legacy" : True,
28  "thresholds" : [ 'EM3', 'EM7', 'EM8VH', 'EM10', 'EM10VH', 'EM12', 'EM14', 'EM15' ],
29  "zeroBias" : "ZB_EM15"
30  },
31  {
32  "name" : "EM2",
33  "format" : "multiplicity",
34  "nbitsDefault" : 3,
35  "type" : "ctpin",
36  "legacy" : True,
37  "thresholds" : [ 'EM15HI', 'EM16', 'EM18VH', 'EM20', 'EM20VH', 'EM20VHI', 'EM22', 'EM22VHI' ]
38  },
39  {
40  "name" : "TAU1",
41  "format" : "multiplicity",
42  "nbitsDefault" : 3,
43  "type" : "ctpin",
44  "legacy" : True,
45  "thresholds" : [ 'HA1', 'HA2', 'HA3', 'HA8', 'HA12', 'HA12IL', 'HA12IM', 'HA12IT' ]
46  },
47 
48  {
49  "name" : "TAU2",
50  "format" : "multiplicity",
51  "nbitsDefault" : 3,
52  "type" : "ctpin",
53  "legacy" : True,
54  "thresholds" : [ 'HA15', 'HA20', 'HA20IL', 'HA20IM', 'HA20IT', 'HA25IT', 'HA30', 'HA60' ]
55  }
56  ]
57 
58 
59  #--------------------------------------
60  # SLOT 8 / CON 0 (JET1, JET2, EN1, EN2)
61  # https://twiki.cern.ch/twiki/bin/view/Atlas/LevelOneCentralTriggerSetup#CTPIN_Slot_8
62  #--------------------------------------
63  legacyBoards["Ctpin8"] = odict()
64  legacyBoards["Ctpin8"]["legacy"] = True
65  legacyBoards["Ctpin8"]["connectors"] = []
66  legacyBoards["Ctpin8"]["connectors"] += [
67  {
68  # 10 x 3-bit JET (can have multiplicity 4 or more)
69  "name" : "JET1",
70  "format" : "multiplicity",
71  "nbitsDefault" : 3,
72  "type" : "ctpin",
73  "legacy" : True,
74  "thresholds" : [
75  # 8 x JETs and central jets
76  'J12', 'J12p0ETA25', 'J15', 'J15p0ETA25','J20', 'J25','J25p0ETA23','J30',
77  # 2 x VBF
78  'J20p0ETA49', 'J30p0ETA49',
79  ]
80  },
81  {
82  # 15 x 2-bit JET (can have maximum multiplicity of 3) (SLOT 8, CON 1)
83  "name" : "JET2",
84  "format" : "multiplicity",
85  "nbitsDefault" : 2,
86  "type" : "ctpin",
87  "legacy" : True,
88  "thresholds" : [
89  # 3 x Central Jet
90  'JJ15p23ETA49','J20p28ETA31','J40p0ETA25',
91  # 6 Jets
92  'J40', 'J50', 'J75', 'J85', 'J100', 'J400',
93  # 6 x FJ
94  'J15p31ETA49', 'J20p31ETA49', 'J30p31ETA49', 'J50p31ETA49', 'J75p31ETA49', 'J100p31ETA49',
95  ]
96  },
97  {
98  # 24 x 1-bit thresholds
99  "name" : "EN1",
100  "format" : "multiplicity",
101  "nbitsDefault" : 1,
102  "type" : "ctpin",
103  "legacy" : True,
104  "thresholds" : [
105  'TE3', 'TE4', 'TE5', 'TE10', 'TE20', 'TE50', 'TE100', 'TE200', # 8 x TE
106  'XE10', 'XE20', 'XE25', 'XE30', 'XE35', 'XE40', 'XE45', 'XE50', # 8 x XE
107  'XS20', 'XS30', 'XS40', 'XS45', 'XS50', 'XS55', 'XS60', 'XS65', # 8 x XS
108  ]
109  },
110  {
111  # 8 x 1-bit thresholds
112  "name" : "EN2",
113  "format" : "multiplicity",
114  "nbitsDefault" : 1,
115  "type" : "ctpin",
116  "legacy" : True,
117  "thresholds" : [
118  # 8 x restricted eta range in |eta|<4.9
119  'TE3p0ETA49','TE7p0ETA49','TE600p0ETA49', 'TE1500p0ETA49',
120  'TE3000p0ETA49', 'TE3500p0ETA49', 'TE6500p0ETA49', 'TE8000p0ETA49',
121  'XE55', 'XE60', 'XE65', 'XE70', 'XE75', 'XE80', 'XE150', 'XE300', # 8 x XE
122  ]
123  }
124  ]
125 
126 
127  #----------------
128  # Legacy L1TOPO 0
129  #----------------
130  legacyTopoBoards["LegacyTopo0"] = odict()
131  legacyTopoBoards["LegacyTopo0"]["legacy"] = True
132  legacyTopoBoards["LegacyTopo0"]["connectors"] = [
133  {
134  "name" : "LegacyTopo0",
135  "format" : "topological",
136  "type" : "electrical",
137  "legacy" : True,
138  "algorithmGroups" : [
139  {
140  "fpga" : 0,
141  "clock" : 0,
142  "algorithms" : [
143  TopoMenuDef( "INVM_AJ_HighMass", outputbits = (0,3), outputlines = [ "900INVM9999-AJ30s6-AJ20s6",
144  "800INVM9999-AJ30s6-AJ20s6",
145  "700INVM9999-AJ30s6-AJ20s6",
146  "500INVM9999-AJ30s6-AJ20s6" ] ),
147  TopoMenuDef( "INVM_AJ_LowMass", outputbits = (4,7), outputlines = [ "400INVM9999-AJ30s6-AJ20s6",
148  "300INVM9999-AJ30s6-AJ20s6",
149  "200INVM9999-AJ30s6-AJ20s6",
150  "100INVM9999-AJ30s6-AJ20s6" ] ),
151  TopoMenuDef( "0INVM9-EM7ab-EMab", outputbits = 8 ),
152  TopoMenuDef( "HT150-J20s5pETA31", outputbits = 9 ),
153  TopoMenuDef( "HT190-J15s5pETA21", outputbits = 10 ),
154  TopoMenuDef( "INVM_EMs6", outputbits = (11,13), outputlines = [ "1INVM5-EMs1-EMs6",
155  "1INVM5-EM7s1-EMs6",
156  "1INVM5-EM12s1-EMs6" ] ),
157  TopoMenuDef( "05MINDPHI-EM12s6-XE0", outputbits = 14 ),
158  TopoMenuDef( "400INVM9999-AJ30s6pETA31-AJ20s6p31ETA49", outputbits = 15 ),
159  ]
160  },
161  {
162  "fpga" : 0,
163  "clock" : 1,
164  "algorithms" : [
165  TopoMenuDef( "05MINDPHI-EM15s6-XE0", outputbits = 0 ),
166  TopoMenuDef( "25MT-EM12s6-XE0", outputbits = 1 ),
167  TopoMenuDef( "ZEE-EM20shi2", outputbits = 2 ),
168  TopoMenuDef( "35MT-EM15s6-XE0", outputbits = 3 ),
169  TopoMenuDef( "0DR03-EM7ab-CJ15ab", outputbits = 4 ),
170  TopoMenuDef( "10MINDPHI-J20s2-XE30", outputbits = 5 ),
171  TopoMenuDef( "10MINDPHI-J20s2-XE50", outputbits = 6 ),
172  TopoMenuDef( "100RATIO-0MATCH-TAU30si2-EMall", outputbits = 7 ),
173  TopoMenuDef( "NOT-0MATCH-TAU30si1-EMall", outputbits = 8 ),
174  TopoMenuDef( "LAR-EM20shi1", outputbits = 9 ),
175  TopoMenuDef( "LAR-J100s1", outputbits = 10 ),
176  TopoMenuDef( "NOT-02MATCH-EM10s1-AJj15allpETA49", outputbits = 11 ),
177  TopoMenuDef( "27DPHI32-EMs1-EMs6", outputbits = 12 ),
178  TopoMenuDef( "35MT-EM12s6-XE0", outputbits = 13 ),
179  TopoMenuDef( "15MINDPHI-EM12s6-XE0", outputbits = 14 ),
180  TopoMenuDef( "15MINDPHI-EM15s6-XE0", outputbits = 15 ),
181  ]
182  },
183  {
184  "fpga" : 1,
185  "clock" : 0,
186  "algorithms" : [
187  TopoMenuDef( "1DISAMB-EM15his2-TAU12abi-J25ab", outputbits = 2 ),
188  TopoMenuDef( "1DISAMB-J25ab-0DR28-EM15his2-TAU12abi", outputbits = 3 ),
189  TopoMenuDef( "2INVM9-2MU6ab", outputbits = 4 ),
190  TopoMenuDef( "2INVM8-ONEBARREL-MU6ab-MU4ab", outputbits = 6 ),
191  TopoMenuDef( "5DETA99-5DPHI99-MU6ab-MU4ab", outputbits = 8 ),
192  TopoMenuDef( "5DETA99-5DPHI99-2MU6ab", outputbits = 9 ),
193  TopoMenuDef( "1DISAMB-TAU20abi-TAU12abi-J25ab", outputbits = 10 ),
194  TopoMenuDef( "0DR28-MU10ab-TAU12abi", outputbits = 11 ),
195  TopoMenuDef( "0DETA20-0DPHI20-TAU20abi-TAU12abi", outputbits = 12 ),
196  TopoMenuDef( "DISAMB-0DR28-EM15his2-TAU12abi", outputbits = 15 ),
197  ]
198  },
199  {
200  "fpga" : 1,
201  "clock" : 1,
202  "algorithms" : [
203  TopoMenuDef( "DISAMB-30INVM-EM20his2-TAU12ab", outputbits = 0 ),
204  TopoMenuDef( "0DR22-2MU6ab", outputbits = 4 ),
205  TopoMenuDef( "7INVM15-2MU4ab", outputbits = 5 ),
206  TopoMenuDef( "0DR22-MU6ab-MU4ab", outputbits = 6 ),
207  TopoMenuDef( "0DR15-2MU4ab", outputbits = 7 ),
208  TopoMenuDef( "0DR24-2MU4ab", outputbits = 8 ),
209  TopoMenuDef( "0DR15-2MU6ab", outputbits = 9 ),
210  TopoMenuDef( "2INVM9-2MU4ab", outputbits = 10 ),
211  TopoMenuDef( "2INVM9-MU6ab-MU4ab", outputbits = 11 ),
212  TopoMenuDef( "INVM_NFF", outputbits = (12,15), outputlines = [ "600INVM9999-J30s6-AJ20s6",
213  "500INVM9999-J30s6-AJ20s6",
214  "400INVM9999-J30s6-AJ20s6",
215  "200INVM9999-J30s6-AJ20s6" ])
216  ]
217  }
218  ]
219  }
220  ]
221 
222  legacyTopoBoards["LegacyTopo1"] = odict()
223  legacyTopoBoards["LegacyTopo1"]["legacy"] = True
224  legacyTopoBoards["LegacyTopo1"]["connectors"] = [
225  {
226  "name" : "LegacyTopo1",
227  "format" : "topological",
228  "type" : "electrical",
229  "legacy" : True,
230  "algorithmGroups" : [
231  {
232  "fpga" : 0,
233  "clock" : 0,
234  "algorithms" : [
235  TopoMenuDef( "05MINDPHI-AJj10s6-XE0", outputbits = 0 ),
236  TopoMenuDef( "10MINDPHI-AJj10s6-XE0", outputbits = 1 ),
237  TopoMenuDef( "15MINDPHI-AJj10s6-XE0", outputbits = 2 ),
238  TopoMenuDef( "0DR04-MU4ab-CJ15ab", outputbits = 3 ),
239  TopoMenuDef( "0DR04-MU4ab-CJ20ab", outputbits = 4 ),
240  TopoMenuDef( "0DR04-MU4ab-CJ30ab", outputbits = 5 ),
241  TopoMenuDef( "0DR04-MU6ab-CJ20ab", outputbits = 6 ),
242  TopoMenuDef( "0DR04-MU6ab-CJ25ab", outputbits = 7 ),
243  TopoMenuDef( "10MINDPHI-CJ20ab-XE50", outputbits = 8 ),
244  TopoMenuDef( "0DR24-2CMU4ab", outputbits = 9 ),
245  TopoMenuDef( "FTK-J100s1", outputbits = 10 ),
246  TopoMenuDef( "MULT-CMU4ab", outputbits = (11,12), outputlines = [ "MULT-CMU4ab[0]",
247  "MULT-CMU4ab[1]" ] ),
248  TopoMenuDef( "MULT-CMU6ab", outputbits = (13,14), outputlines = [ "MULT-CMU6ab[0]",
249  "MULT-CMU6ab[1]" ] ),
250  TopoMenuDef( "FTK-MU10s1", outputbits = 15 ),
251  ]
252  },
253  {
254  "fpga" : 0,
255  "clock" : 1,
256  "algorithms" : [
257  TopoMenuDef( "0DETA04-EM8abi-MU10ab", outputbits = 3 ),
258  TopoMenuDef( "0DETA04-EM15abi-MUab", outputbits = 4 ),
259  TopoMenuDef( "0DR24-CMU4ab-MU4ab", outputbits = 5 ),
260  TopoMenuDef( "0DPHI03-EM8abi-MU10ab", outputbits = 6 ),
261  TopoMenuDef( "2INVM8-CMU4ab-MU4ab", outputbits = 7 ),
262  TopoMenuDef( "0DPHI03-EM15abi-MUab", outputbits = 8 ),
263  TopoMenuDef( "10MINDPHI-AJ20s2-XE50", outputbits = 9 ),
264  TopoMenuDef( "LATE-MU10s1", outputbits = 10 ),
265  TopoMenuDef( "SC111-CJ15abpETA26", outputbits = 11 ),
266  TopoMenuDef( "SC85-CJ15abpETA26", outputbits = 12 ),
267  TopoMenuDef( "FTK-EM20s1", outputbits = 13 ),
268  ]
269  },
270  {
271  "fpga" : 1,
272  "clock" : 0,
273  "algorithms" : [
274  TopoMenuDef( "KF-XE-AJall", outputbits = (0,5),outputlines = [ "KF-XE40-AJall",
275  "KF-XE50-AJall",
276  "KF-XE55-AJall",
277  "KF-XE60-AJall",
278  "KF-XE65-AJall",
279  "KF-XE75-AJall" ] ),
280  TopoMenuDef( "0MATCH-4AJ20pETA31-4AJj15pETA31", outputbits = 6 ),
281  TopoMenuDef( "HT190-AJ15allpETA21", outputbits = 7 ),
282  TopoMenuDef( "HT150-AJ20allpETA31", outputbits = 8 ),
283  TopoMenuDef( "HT150-AJj15allpETA49", outputbits = 9 ),
284  TopoMenuDef( "HT20-AJj15allpETA49", outputbits = 10 ),
285  TopoMenuDef( "0DETA20-J50s1-Js2", outputbits = 12 ),
286  TopoMenuDef( "05RATIO-XE0-HT0-AJj15allpETA49", outputbits = 13 ),
287  TopoMenuDef( "63DETA127-FJ20s1-FJ20s2", outputbits = 14 ),
288  TopoMenuDef( "90RATIO2-XE0-HT0-AJj15allpETA49", outputbits = 15 )
289  ]
290  },
291  {
292  "fpga" : 1,
293  "clock" : 1,
294  "algorithms" : [
295  TopoMenuDef( "250RATIO2-XE0-HT0-AJj15allpETA49", outputbits = 0 ),
296  TopoMenuDef( "10MINDPHI-J20ab-XE50", outputbits = 1 ),
297  TopoMenuDef( "0DR28-TAU20abi-TAU12abi", outputbits = 2 ),
298  TopoMenuDef( "1DISAMB-J25ab-0DR28-TAU20abi-TAU12abi", outputbits = 3 ),
299  TopoMenuDef( "1DISAMB-TAU12abi-J25ab", outputbits = 4 ),
300  TopoMenuDef( "0DR10-MU10ab-MU6ab", outputbits = 5 ),
301  TopoMenuDef( "2DR99-2MU4ab", outputbits = 6 ),
302  TopoMenuDef( "0DR34-2MU4ab", outputbits = 7 ),
303  TopoMenuDef( "2DR15-2MU6ab", outputbits = 8 ),
304  TopoMenuDef( "0DR15-MU6ab-MU4ab", outputbits = 9 ),
305  TopoMenuDef( "0DR25-TAU20abi-TAU12abi", outputbits = 10 ),
306  TopoMenuDef( "1DISAMB-J25ab-0DR25-TAU20abi-TAU12abi", outputbits = 11 ),
307  TopoMenuDef( "8INVM15-MU6ab-MU4ab", outputbits = 12 ),
308  TopoMenuDef( "8INVM15-2MU6ab", outputbits = 13 ),
309  TopoMenuDef( "2INVM8-2MU4ab", outputbits = 14 ),
310  TopoMenuDef( "2INVM8-MU6ab-MU4ab", outputbits = 15 ),
311  ]
312  }
313  ]
314  }
315  ]
316 
317 
318  L1MenuFlags.legacyBoards().clear()
319 
320  L1MenuFlags.legacyBoards().update( legacyBoards ) # EM1/2, TAU1/2, JET1/2, EN1/2
321 
322  L1MenuFlags.legacyBoards().update( legacyTopoBoards) # LegacyTopo0/1
323 
324  L1MenuFlags.legacyBoards().update( createMergerBoard( legacyTopoBoards["LegacyTopo0"], legacyTopoBoards["LegacyTopo1"] ) )
325 
python.L1.Base.MenuConfObj.TopoMenuDef
Definition: MenuConfObj.py:6
python.L1.Config.LegacyTopoMergerMap.createMergerBoard
def createMergerBoard(legacyBoard0, legacyBoard1)
Definition: LegacyTopoMergerMap.py:48
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update
Definition: dqt_zlumi_pandas.py:42
VKalVrtAthena::varHolder_detail::clear
void clear(T &var)
Definition: NtupleVars.h:48
python.L1.Menu.Menu_Physics_HI_run3_v1_inputs_legacy.defineLegacyInputsMenu
def defineLegacyInputsMenu()
Definition: Menu_Physics_HI_run3_v1_inputs_legacy.py:9
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