ATLAS Offline Software
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F100StreamIntegrationAlg.h
Go to the documentation of this file.
1/*
2 Copyright (C) 2002-2025 CERN for the benefit of the ATLAS collaboration
3*/
4
8
9#ifndef EFTRACKING_FPGA_INTEGRATION_F100StreamIntegrationAlg_H
10#define EFTRACKING_FPGA_INTEGRATION_F100StreamIntegrationAlg_H
11
12// EFTracking include
16
17// Athena include
20#include "GaudiKernel/ServiceHandle.h"
21#include "GaudiKernel/IChronoSvc.h"
24
26{
34 {
35 public:
36 using IntegrationBase::IntegrationBase;
37 virtual StatusCode initialize() override final;
38 virtual StatusCode execute(const EventContext &ctx) const override final;
39 virtual StatusCode finalize() override final;
40
41 private:
42 ServiceHandle<IChronoSvc> m_chronoSvc{"ChronoStatSvc", name()};
43
44 SG::ReadHandleKey<std::vector<uint64_t>> m_FPGAPixelRDO{this, "FPGAEncodedPixelKey", "FPGAEncodedPixelRDOs", "Pixel RDO converted to FPGA format"};
45 SG::ReadHandleKey<std::vector<uint64_t>> m_FPGAStripRDO{this, "FPGAEncodedStripKey", "FPGAEncodedStripRDOs", "Strip RDO converted to FPGA format"};
46
47 SG::ReadHandleKey<int> m_FPGAPixelRDOSize{this, "FPGAEncodedPixelSizeKey", "FPGAEncodedPixelSizeRDOs", "Pixel RDO converted to FPGA format"};
48 SG::ReadHandleKey<int> m_FPGAStripRDOSize{this, "FPGAEncodedStripSizeKey", "FPGAEncodedStripSizeRDOs", "Strip RDO converted to FPGA format"};
49
50 SG::WriteHandleKey<std::vector<uint32_t>> m_FPGAPixelOutput{this, "FPGAOutputPixelKey", "FPGAPixelOutput", "Pixel output from FPGA format"};
51 SG::WriteHandleKey<std::vector<uint32_t>> m_FPGAStripOutput{this, "FPGAOutputStripKey", "FPGAStripOutput", "Strip output from FPGA format"};
52
53 Gaudi::Property<int> m_FPGAThreads{this, "FPGAThreads", 1, "number of FPGA threads to initialize"};
54
55 Gaudi::Property<std::string> m_xclbin{this, "xclbin", "", "xclbin path and name"};
56
57
58 Gaudi::Property<std::string> m_pixelEdmKernelName{this, "PixelEDMPrepKernelName", "", "Name of the FPGA kernel"};
59
60 Gaudi::Property<std::string> m_stripEdmKernelName{this, "StripEDMPrepKernelName", "", "Name of the FPGA kernel"};
61
62 Gaudi::Property<std::string> m_pixelStartClusterKernelName{this, "PixelStartClusterKernelName", "", "Name of the pixel clustering start kernel"};
63 Gaudi::Property<std::string> m_pixelEndClusterKernelName{this, "PixelEndClusterKernelName", "", "Name of the pixel clustering end kernel"};
64 Gaudi::Property<std::string> m_pixelEndClusterEdmKernelName{this, "PixelEndClusterEdmKernelName", "", "Name of the pixel clustering end kernel"};
65
66 Gaudi::Property<std::string> m_stripStartClusterKernelName{this, "StripStartClusterKernelName", "", "Name of the strip clustering start kernel"};
67 Gaudi::Property<std::string> m_stripEndClusterKernelName{this, "StripEndClusterKernelName", "", "Name of the strip clustering end kernel"};
68
69
70 Gaudi::Property<std::string> m_pixelL2GKernelName{this, "PixelL2GKernelName", "", "Name of the pixel L2G kernel"};
71 Gaudi::Property<std::string> m_stripL2GKernelName{this, "StripL2GKernelName", "", "Name of the strip L2G kernel"};
72
73
74
75 mutable std::atomic<ulonglong> m_numEvents{0};
76 mutable std::atomic<cl_ulong> m_pixelInputTime{0};
77 mutable std::atomic<cl_ulong> m_stripInputTime{0};
78 mutable std::atomic<cl_ulong> m_pixelClusteringTime{0};
79 mutable std::atomic<cl_ulong> m_stripClusteringTime{0};
80 mutable std::atomic<cl_ulong> m_pixelL2GTime{0};
81 mutable std::atomic<cl_ulong> m_stripL2GTime{0};
82 mutable std::atomic<cl_ulong> m_pixelEdmPrepTime{0};
83 mutable std::atomic<cl_ulong> m_stripEdmPrepTime{0};
84 mutable std::atomic<cl_ulong> m_pixelOutputTime{0};
85 mutable std::atomic<cl_ulong> m_stripOutputTime{0};
86 mutable std::atomic<cl_ulong> m_kernelTime{0};
87
88 // Kernels
89 // Clustering
90 mutable std::vector<cl::Kernel> m_pixelStartClusteringKernels ATLAS_THREAD_SAFE;
91 mutable std::vector<cl::Kernel> m_pixelEndClusteringClusterKernels ATLAS_THREAD_SAFE;
92 mutable std::vector<cl::Kernel> m_pixelEndClusteringEDMKernels ATLAS_THREAD_SAFE;
93 mutable std::vector<cl::Kernel> m_stripStartClusteringKernels ATLAS_THREAD_SAFE;
94 mutable std::vector<cl::Kernel> m_stripEndClusteringKernels ATLAS_THREAD_SAFE;
95
96 // L2G
97 mutable std::vector<cl::Kernel> m_pixelL2GKernels ATLAS_THREAD_SAFE;
98 mutable std::vector<cl::Kernel> m_stripL2GKernels ATLAS_THREAD_SAFE;
99
100 // EDM prep
101 mutable std::vector<cl::Kernel> m_pixelEdmPrepKernels ATLAS_THREAD_SAFE;
102 mutable std::vector<cl::Kernel> m_stripEdmPrepKernels ATLAS_THREAD_SAFE;
103
104 // Buffers for input
105 std::vector<cl::Buffer> m_pixelClusterInputBufferList;
106 std::vector<cl::Buffer> m_stripClusterInputBufferList;
107 // Buffers for Clustering
108 std::vector<cl::Buffer> m_pixelClusterOutputBufferList;
109 std::vector<cl::Buffer> m_stripClusterOutputBufferList;
110 std::vector<cl::Buffer> m_pixelClusterEDMOutputBufferList;
111 std::vector<cl::Buffer> m_stripClusterEDMOutputBufferList;
112 // L2G
113 std::vector<cl::Buffer> m_pixelL2GOutputBufferList;
114 std::vector<cl::Buffer> m_stripL2GOutputBufferList;
115 std::vector<cl::Buffer> m_pixelL2GEDMOutputBufferList;
116 std::vector<cl::Buffer> m_stripL2GEDMOutputBufferList;
117 // EDMPrep
118 std::vector<cl::Buffer> m_edmPixelOutputBufferList;
119 std::vector<cl::Buffer> m_edmStripOutputBufferList;
120
121 // Command queue
122 std::vector<cl::CommandQueue> m_acc_queues;
123 void getListofCUs(std::vector<std::string>& cuNames);
124
125
126 };
127}
128
129#endif // EFTRACKING_FPGA_INTEGRATION_F100StreamIntegrationAlg_H
This is the class for the benchmark algorithm specific to the FPGA integration and output conversion.
Gaudi::Property< std::string > m_stripStartClusterKernelName
Name of the strip clustering kernel start.
std::atomic< cl_ulong > m_pixelL2GTime
Time for pixel L2G.
std::vector< cl::Kernel > m_pixelStartClusteringKernels ATLAS_THREAD_SAFE
SG::WriteHandleKey< std::vector< uint32_t > > m_FPGAPixelOutput
Gaudi::Property< std::string > m_stripL2GKernelName
Name of the strip L2G kernelS.
Gaudi::Property< std::string > m_pixelEdmKernelName
Name of the FPGA kernel.
std::atomic< cl_ulong > m_stripEdmPrepTime
Time for strip EDM preparation.
std::atomic< ulonglong > m_numEvents
Number of events processed.
std::atomic< cl_ulong > m_stripInputTime
Time for strip input buffer write.
std::atomic< cl_ulong > m_pixelEdmPrepTime
Time for pixel EDM preparation.
SG::WriteHandleKey< std::vector< uint32_t > > m_FPGAStripOutput
Gaudi::Property< std::string > m_pixelEndClusterKernelName
Name of the pixel clustering kernel start.
Gaudi::Property< std::string > m_pixelEndClusterEdmKernelName
Name of the pixel clustering kernel start.
virtual StatusCode execute(const EventContext &ctx) const override final
Should be overriden by derived classes to perform meaningful work.
Gaudi::Property< std::string > m_stripEndClusterKernelName
Name of the strip clustering kernel start.
std::atomic< cl_ulong > m_pixelInputTime
Time for pixel input buffer write.
std::atomic< cl_ulong > m_pixelOutputTime
Time for pixel output buffer read.
SG::ReadHandleKey< std::vector< uint64_t > > m_FPGAPixelRDO
SG::ReadHandleKey< std::vector< uint64_t > > m_FPGAStripRDO
void getListofCUs(std::vector< std::string > &cuNames)
virtual StatusCode initialize() override final
Detect the OpenCL devices and prepare OpenCL context.
Gaudi::Property< std::string > m_pixelL2GKernelName
Name of the pixel L2G kernel.
Gaudi::Property< std::string > m_stripEdmKernelName
Name of the FPGA kernel.
ServiceHandle< IChronoSvc > m_chronoSvc
Service for timing the algorithm.
std::atomic< cl_ulong > m_kernelTime
Time for kernel execution.
Gaudi::Property< std::string > m_xclbin
Path and name of the xclbin file.
std::atomic< cl_ulong > m_stripL2GTime
Time for strip L2G.
std::atomic< cl_ulong > m_pixelClusteringTime
Time for pixel clustering.
std::atomic< cl_ulong > m_stripClusteringTime
Time for strip clustering.
std::atomic< cl_ulong > m_stripOutputTime
Time for strip output buffer read.
Gaudi::Property< std::string > m_pixelStartClusterKernelName
Name of the pixel clustering kernel start.
The base class for the EFTracking FPGA integration development.
Property holding a SG store/key/clid from which a ReadHandle is made.
Property holding a SG store/key/clid from which a WriteHandle is made.
The class for enconding RDO to FPGA format.