3from AthenaConfiguration.ComponentFactory
import CompFactory
4from AthenaConfiguration.ComponentAccumulator
import ComponentAccumulator
7 acc = ComponentAccumulator()
9 kwarg.setdefault(
'bdfID', flags.FPGADataPrep.bdfID)
10 kwarg.setdefault(
'xclbin', flags.FPGADataPrep.xclbin)
12 kwarg.setdefault(
'RunSlicing',
False)
13 kwarg.setdefault(
'RunInsideOut',
False)
14 kwarg.setdefault(
'RunInsideOutOnSlicingEngine',
False)
15 kwarg.setdefault(
'RunFullF150',
True)
16 kwarg.setdefault(
'outputTextFile',
False)
17 kwarg.setdefault(
'doEmulation',
False)
19 kwarg.setdefault(
'SlicingEngineInputName',
'configurableLengthWideLoader')
20 kwarg.setdefault(
'SlicingEngineOutputName',
'dynamicLengthWideUnloader')
22 kwarg.setdefault(
'InsideOutInputName',
'krnl_mm2s')
23 kwarg.setdefault(
'InsideOutOutputName',
'mem_write')
25 kwarg.setdefault(
'PixelClusterKernelName',
'pixel_clustering_tool')
26 kwarg.setdefault(
'StripClusterKernelName',
'processHits')
27 kwarg.setdefault(
'StripL2GKernelName',
'l2g_strip_tool')
28 kwarg.setdefault(
'PixelEDMPrepKernelName',
'PixelEDMPrep')
29 kwarg.setdefault(
'StripEDMPrepKernelName',
'StripEDMPrep')
30 from FPGATrackSimConfTools.FPGATrackSimHelperFunctions
import convertRegionsExpressionToArray
31 kwarg.setdefault(
'FPGATrackSimHitKey_1st',
'FPGAHits_1st_reg' + str(convertRegionsExpressionToArray(flags.Trigger.FPGATrackSim.regionList)[0]))
32 kwarg.setdefault(
'FPGATrackSimTrack1stKey',
'FPGATracks_1st_reg' + str(convertRegionsExpressionToArray(flags.Trigger.FPGATrackSim.regionList)[0]))
35 from EFTrackingFPGAPipeline.DataPrepConfig
import xAODClusterMakerCfg
36 clusterMakerTool = acc.popToolsAndMerge(xAODClusterMakerCfg(flags))
37 kwarg.setdefault(
'xAODClusterMaker', clusterMakerTool)
40 from EFTrackingFPGAUtility.FPGADataFormatter
import FPGATestVectorToolCfg
41 testVectorTool = acc.popToolsAndMerge(FPGATestVectorToolCfg(flags))
42 kwarg.setdefault(
'TestVectorTool', testVectorTool)
45 kwarg.setdefault(
'OutputConversionTool', outputTool)
48 acc.addService(CompFactory.ChronoStatSvc(
50 PrintSystemTime =
True,
51 PrintEllapsedTime =
True
54 alg = CompFactory.EFTrackingFPGAIntegration.F150KernelTesterAlg(**kwarg)
60 acc = ComponentAccumulator()
62 kwarg.setdefault(
'FPGAOutputTrackKey',
"FPGATrackOutput")
63 kwarg.setdefault(
'FPGASpacePointsKey',
"ITkPixelSpacePoints")
64 kwarg.setdefault(
'OutputSeeds',
"ActsValidateF150PixelSeeds")
66 alg = CompFactory.EFTrackingFPGAIntegration.F150EDMConversionAlg(**kwarg)
74 acc = ComponentAccumulator()
76 kwarg.setdefault(
'name', name)
77 acc.setPrivateTools(CompFactory.OutputConversionTool(**kwarg))
83if __name__ ==
"__main__":
84 from AthenaConfiguration.AllConfigFlags
import initConfigFlags
85 from AthenaConfiguration.MainServicesConfig
import MainServicesCfg
87 flags = initConfigFlags()
91 FinalProtoTrackChainxAODTracksKey=
"FPGA"
92 flags.Detector.EnableCalo =
False
95 flags.Tracking.ITkMainPass.doAthenaToActsSpacePoint=
True
96 flags.Tracking.ITkMainPass.doAthenaToActsCluster=
True
97 from ActsConfig.ActsCIFlags
import actsLegacyWorkflowFlags
98 actsLegacyWorkflowFlags(flags)
99 flags.Acts.doRotCorrection =
False
102 flags.Concurrency.NumThreads=1
104 flags.Scheduler.ShowDataDeps=
True
105 flags.Scheduler.CheckDependencies=
True
106 flags.Debug.DumpEvtStore=
False
110 flags.Input.Files = [
"/cvmfs/atlas-nightlies.cern.ch/repo/data/data-art/PhaseIIUpgrade/RDO/ATLAS-P2-RUN4-03-00-00/mc21_14TeV.601229.PhPy8EG_A14_ttbar_hdamp258p75_SingleLep.recon.RDO.e8481_s4149_r14700/RDO.33629020._000047.pool.root.1"]
114 flags.Trigger.FPGATrackSim.tracking =
False
115 flags.Trigger.FPGATrackSim.Hough.genScan =
True
116 flags.Trigger.FPGATrackSim.Hough.secondStage =
False
120 flags = flags.cloneAndReplace(
"Tracking.ActiveConfig",
"Tracking.MainPass")
121 cfg=MainServicesCfg(flags)
123 from AthenaPoolCnvSvc.PoolReadConfig
import PoolReadCfg
124 cfg.merge(PoolReadCfg(flags))
127 from xAODTruthCnv.xAODTruthCnvConfig
import GEN_AOD2xAODCfg
128 cfg.merge(GEN_AOD2xAODCfg(flags))
130 from JetRecConfig.JetRecoSteering
import addTruthPileupJetsToOutputCfg
131 cfg.merge(addTruthPileupJetsToOutputCfg(flags))
133 if flags.Detector.EnableCalo:
134 from CaloRec.CaloRecoConfig
import CaloRecoCfg
135 cfg.merge(CaloRecoCfg(flags))
137 if flags.Tracking.recoChain:
138 from InDetConfig.TrackRecoConfig
import InDetTrackRecoCfg
139 cfg.merge(InDetTrackRecoCfg(flags))
143 from InDetConfig.InDetPrepRawDataFormationConfig
import ITkXAODToInDetClusterConversionCfg
144 cfg.merge(ITkXAODToInDetClusterConversionCfg(flags))
145 from FPGATrackSimConfTools.FPGATrackSimDataPrepConfig
import FPGATrackSimDataPrepAlgCfg
146 cfg.merge(FPGATrackSimDataPrepAlgCfg(flags))
147 from FPGATrackSimConfTools.FPGATrackSimMultiRegionConfig
import FPGATrackSimMultiRegionTrackingCfg
148 cfg.merge(FPGATrackSimMultiRegionTrackingCfg(flags))
155 cfg.foreach_component(
"AthEventSeq/*").OutputLevel = DEBUG
157 cfg.printConfig(withDetails=
True, summariseProps=
True)
159 cfg.run(flags.Exec.MaxEvents)
F150EDMConversionAlgCfg(flags, **kwarg)
KernelTesterCfg(flags, name='F150BenchmarkAlg', **kwarg)
FPGAOutputConversionToolCfg(flags, name='FPGAOutputConversionTool', **kwarg)