F1X0IntegrationAlg.h

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/*
    Copyright (C) 2002-2025 CERN for the benefit of the ATLAS collaboration
*/
 
#ifndef EFTRACKING_FPGA_INTEGRATION_F1X0IntegrationAlg_H
#define EFTRACKING_FPGA_INTEGRATION_F1X0IntegrationAlg_H
 
// EFTracking include
#include "EFTrackingFPGAPipeline/IntegrationBase.h"
#include "EFTrackingFPGAUtility/xAODClusterMaker.h"
#include "EFTrackingFPGAUtility/EFTrackingTransient.h"
 
// Athena include
#include "InDetRawData/PixelRDO_Container.h"
#include "InDetRawData/SCT_RDO_Container.h"
#include "GaudiKernel/ServiceHandle.h"        
#include "GaudiKernel/IChronoSvc.h"
#include <TrigSteeringEvent/TrigRoiDescriptorCollection.h>
#include <IRegionSelector/IRegSelTool.h>
 
#include "AthenaMonitoringKernel/Monitored.h"
 
namespace EFTrackingFPGAIntegration
{
    class F1X0IntegrationAlg : public IntegrationBase
    {
    public:
        using IntegrationBase::IntegrationBase;
        virtual StatusCode initialize() override final;
        virtual StatusCode execute(const EventContext &ctx) const override final;
        virtual StatusCode finalize() override final;
 
    private:
        ServiceHandle<IChronoSvc> m_chronoSvc{"ChronoStatSvc", name()}; 
 
        SG::ReadHandleKey<std::vector<uint64_t>> m_FPGAPixelRDO{this, "FPGAEncodedPixelKey", "FPGAEncodedPixelRDOs", "Pixel RDO converted to FPGA format"};
        SG::ReadHandleKey<std::vector<uint64_t>> m_FPGAStripRDO{this, "FPGAEncodedStripKey", "FPGAEncodedStripRDOs", "Strip RDO converted to FPGA format"};
 
        SG::WriteHandleKey<std::vector<uint32_t>> m_FPGAPixelOutput{this, "FPGAOutputPixelKey", "FPGAPixelOutput", "Pixel output from FPGA format"};
        SG::WriteHandleKey<std::vector<uint32_t>> m_FPGAStripOutput{this, "FPGAOutputStripKey", "FPGAStripOutput", "Strip output from FPGA format"};
 
        SG::ReadHandleKey<int> m_FPGAPixelRDOSize{this, "FPGAEncodedPixelSizeKey", "FPGAEncodedPixelSizeRDOs", "Size of the Pixel RDO converted to FPGA format"};
        SG::ReadHandleKey<int> m_FPGAStripRDOSize{this, "FPGAEncodedStripSizeKey", "FPGAEncodedStripSizeRDOs", "Size of the Strip RDO converted to FPGA format"};
 
 
        Gaudi::Property<int> m_FPGAThreads{this, "FPGAThreads", 1, "number of FPGA threads to initialize"}; 
        
        Gaudi::Property<std::string> m_xclbin{
            this, "xclbin", "", "xclbin path and name"}; 
 
        Gaudi::Property<bool> m_doF110{
            this, "doF110", "", "Run F110 instead of F100"}; 
 
        Gaudi::Property<std::string> m_pixelEdmKernelName{
            this, "PixelEDMPrepKernelName", "", "Name of the FPGA kernel"}; 
 
        Gaudi::Property<std::string> m_stripEdmKernelName{
            this, "StripEDMPrepKernelName", "", "Name of the FPGA kernel"}; 
 
        Gaudi::Property<std::string> m_pixelClusterKernelName{
            this, "PixelClusterKernelName", "", "Name of the pixel clustering kernel"}; 
 
        Gaudi::Property<std::string> m_stripClusterKernelName{
            this, "StripClusterKernelName", "", "Name of the strip clustering kernel"}; 
 
        Gaudi::Property<std::string> m_pixelL2GKernelName{
            this, "PixelL2GKernelName", "", "Name of the pixel L2G kernel"}; 
 
        Gaudi::Property<std::string> m_stripL2GKernelName{
            this, "StripL2GKernelName", "", "Name of the strip L2G kernel"}; 
 
        ToolHandle< GenericMonitoringTool > m_monTool  { this, "MonTool", "", "Monitoring tool" };
 
        mutable std::atomic<ulonglong> m_numEvents{0};          
        mutable std::atomic<cl_ulong> m_pixelInputTime{0};      
        mutable std::atomic<cl_ulong> m_stripInputTime{0};      
        mutable std::atomic<cl_ulong> m_pixelClusteringTime{0}; 
        mutable std::atomic<cl_ulong> m_stripClusteringTime{0}; 
        mutable std::atomic<cl_ulong> m_pixelL2GTime{0};        
        mutable std::atomic<cl_ulong> m_stripL2GTime{0};        
        mutable std::atomic<cl_ulong> m_edmPrepTime{0};         
        mutable std::atomic<cl_ulong> m_pixelEdmPrepTime{0};    
        mutable std::atomic<cl_ulong> m_stripEdmPrepTime{0};    
        mutable std::atomic<cl_ulong> m_pixelOutputTime{0};     
        mutable std::atomic<cl_ulong> m_stripOutputTime{0};     
        mutable std::atomic<cl_ulong> m_kernelTime{0};          
 
        // Kernels
        // Clustering
        mutable std::vector<cl::Kernel> m_pixelClusteringKernels ATLAS_THREAD_SAFE;
        mutable std::vector<cl::Kernel> m_stripClusteringKernels ATLAS_THREAD_SAFE;
 
        // L2G
        mutable std::vector<cl::Kernel> m_pixelL2GKernels ATLAS_THREAD_SAFE;
        mutable std::vector<cl::Kernel> m_stripL2GKernels ATLAS_THREAD_SAFE;
 
        // EDM prep
        mutable std::vector<cl::Kernel> m_pixelEdmPrepKernels ATLAS_THREAD_SAFE;
        mutable std::vector<cl::Kernel> m_stripEdmPrepKernels ATLAS_THREAD_SAFE;
 
        // Buffers for input
        std::vector<cl::Buffer> m_pixelClusterInputBufferList;
        std::vector<cl::Buffer> m_stripClusterInputBufferList;
        // Buffers for Clustering
        std::vector<cl::Buffer> m_pixelClusterOutputBufferList;
        std::vector<cl::Buffer> m_stripClusterOutputBufferList;
        std::vector<cl::Buffer> m_pixelClusterEDMOutputBufferList;
        std::vector<cl::Buffer> m_stripClusterEDMOutputBufferList;
        // L2G
        std::vector<cl::Buffer> m_pixelL2GOutputBufferList;
        std::vector<cl::Buffer> m_stripL2GOutputBufferList;
        std::vector<cl::Buffer> m_pixelL2GEDMOutputBufferList;
        std::vector<cl::Buffer> m_stripL2GEDMOutputBufferList;
        // EDMPrep
        std::vector<cl::Buffer> m_edmPixelOutputBufferList;
        std::vector<cl::Buffer> m_edmStripOutputBufferList;
 
        // Command queue
        std::vector<cl::CommandQueue> m_acc_queues;
        void getListofCUs(std::vector<std::string>& cuNames);
 
 
    };
}
 
#endif // EFTRACKING_FPGA_INTEGRATION_F1X0IntegrationAlg_H