377 ):
378 menu = json.load(open(json_name))
379
380 gsim_alg_prefix = "GlobalSim_"
381
382 cfg = ComponentAccumulator()
383
384
385 cfg.addSequence(CompFactory.AthSequencer('GlobalSimPrereqs'))
386
387 cfg.addSequence(CompFactory.AthSequencer('LArPreprocessing'), parentName='GlobalSimPrereqs')
388 from GlobalSimulation.LArCellPreparationAlgConfig import LArCellPreparationAlgCfg
389 cfg.merge( LArCellPreparationAlgCfg(
390 flags,
391 name = gsim_alg_prefix+'LArCellPreparationAlg',
392 GlobalLArCellsKey='GlobalLArCells',
393 ),
394 sequenceName='LArPreprocessing'
395 )
396
397 cfg.addSequence(CompFactory.AthSequencer('GlobalSimulation'))
398
399 cfg.addService( CompFactory.GlobalSim.GraphSvc(SequenceNameFilter='GlobalSimulation'), create=True )
400
401 all_vector_outputs =
set()
402
403
404
405
406
407 tobs_to_providers = {}
408 for pname, provider in menu['algorithms'].items():
409 log.debug(f"{pname} --> {provider}")
410 output = expand_io(provider['output'])
411 log.debug('Outputs:')
412 log.debug(pformat(output))
413 _provider = dict(provider)
414 if '/' in pname:
415 _provider['type'], _provider['name'] = pname.split('/',1)
416 else:
417 _provider['type'] = _provider['name'] = pname
418 if gsim_alg_prefix:
419 _provider['name'] = gsim_alg_prefix + _provider['name']
420 _provider['input'] = expand_io(provider['input'])
421 _provider['output'] = output
422 _provider['parameters'] = {}
423 _provider['parameters'].update(provider.get('parameters',{}))
424 for otuple in output:
425 assert otuple[1] not in tobs_to_providers, f"Duplicate provider for {otuple}"
426 tobs_to_providers[otuple[1]] = _provider
427
428 log.debug(pformat(tobs_to_providers))
429
430
431 if txt_inputs:
432 for key, (bitspec, filepath) in txt_inputs.items():
433 if key in tobs_to_providers:
434 log.warning(f"Replacing {key} algorithm of type {tobs_to_providers[key]} with text reader")
435 else:
436 log.info(f"Inserting text reader to provide {key}")
437 tobs_to_providers[key] = {
438 'type': 'TOBTextReader',
439 'name': f'{key}_{bitspec}_from_txt',
440 'input': [],
441 'output': [('Output',key)],
442 'parameters': {
443 'BitSpec': bitspec,
444 'InputFile': filepath
445 }
446 }
447
448
449
450 active_thresholds =
set()
451 TIP_bits = 0
452 if not ignore_menu_items:
453 for item, item_dict in menu['items'].items():
454 for threshold in item_dict['thresholds']:
455 active_thresholds.add(threshold)
456
457 for threshold in active_thresholds:
458 hypo_ca, vector_outputs, hypo_dict = L0HypoCfg(
459 flags,
460 threshold,
461 hypo_specs = menu['hypotheses'],
462 tobs_to_providers = tobs_to_providers,
463 triggerlines = menu['connectors']['L0Global']['triggerlines']
464 )
465 cfg.merge(hypo_ca,'GlobalSimulation')
466 all_vector_outputs |= vector_outputs
467
468
469 hypo_bits = sum([1<<i for i in range(hypo_dict['startbit'],hypo_dict['startbit']+hypo_dict['nbits'])])
470 assert TIP_bits & hypo_bits == 0, f"TIP bits for {threshold} overlap other thresholds"
471 TIP_bits = TIP_bits + hypo_bits
472
473
474 for tob in force_config_TOBs:
475 log.info(f"Explicitly configuring {tob} from menu")
476 tob_cfgs, vector_outputs = config_TOB_providers(flags,tobs_to_providers,{tob})
477
478 for ca in reversed(tob_cfgs):
479 cfg.merge(ca,'GlobalSimulation')
480 all_vector_outputs |= vector_outputs
481
482
483
484 if txt_outputs:
485 for key, (bitspec, filepath) in txt_outputs.items():
486 log.info(f"Inserting text writer to record {key}")
487 cfg.addEventAlgo(
488 CompFactory.GlobalSim.TOBTextWriter(
489 f'{key}_{bitspec}_to_txt',
490 Input=key,
491 BitSpec=bitspec,
492 OutputFile=filepath
493 )
494 )
495
496
497 from OutputStreamAthenaPool.OutputStreamConfig import addToAOD
498 cfg.merge(addToAOD(flags,all_vector_outputs))
499
500 if print_detailed_config:
501 cfg.printConfig(summariseProps=True)
502
503 return cfg
504
505